Linux: Update kernel 5.4.80 (#1019)

* Avoid trying to boot non-existing kernel image in fail-over case

The A/B update system automatically switches to the other boot slot when
booting fails. However, in a fresh installation, only boot slot A
exists. If booting fails three times (e.g. if somebody plugs out power
before the slot can be marked as good), then the system switches to boot
slot B which does not contain a kernel image yet. Avoid trying to boot
the non-existing kernel image.

With this change, if slot B is empty U-Boot will restore both slots to 3
attempts and retry booting from slot A on next reboot:

```
Trying to boot slot B, 2 attempts remaining. Loading kernel ...
** Unrecognized filesystem type **
No valid slot found, resetting tries to 3
storing env...
```

Co-authored-by: Pascal Vizeli <pascal.vizeli@syshack.ch>

.github/ISSUE_TEMPLATE.md

@@ -1,23 +1,21 @@
 <!-- READ THIS FIRST:
 - If you need additional help with this template please refer to https://www.home-assistant.io/help/reporting_issues/
-- Make sure you are running the latest version before reporting an issue: https://github.com/home-assistant/core/releases
-- Do not report issues for integrations here, please refer to https://github.com/home-assistant/core/issues
+- Make sure you are running the latest version before reporting an issue: https://github.com/home-assistant/home-assistant/releases
+- Do not report issues for components here, plaese refer to https://github.com/home-assistant/home-assistant/issues
 - This is for bugs only. Feature and enhancement requests should go in our community forum: https://community.home-assistant.io/c/feature-requests
 - Provide as many details as possible. Paste logs, configuration sample and code into the backticks. Do not delete any text from this template!
-- If you have a problem with an add-on, make an issue in its repository.
-- If you are using Raspberry Pi overlays in config.txt and your system doesn't work anymore please report this to the Raspberry Pi kernel project.
-
+- If you have a problem with a Add-on, make a issue on there repository.
 -->
 
 **HassOS release with the issue:**
 <!--
-- Frontend -> Configuration -> Info
+- Frontend -> Developer tools -> Info
 - Or use this command: hass --version
 -->
 
 **Supervisor logs:**
 <!--
-- Frontend -> Supervisor -> System
+- Frontend -> Hass.io -> System
 - Or use this command: ha su logs
 -->
 

Documentation/README.md

@@ -0,0 +1,13 @@
+# Developer Documentation
+
+## Contents
+
+- [Getting started](./getting_started_development.md) - the place for developers to begin
+- [Development](./getting_started_development.md) - more deatils for developers
+- [Deployment](./deployment.md) - approach to git branching and releases
+- [Configuration](./configuration.md) - how users can configure HassOS
+- [Partition](./partition.md) - partition layout
+- [Network](./network.md) - approach to networking
+- [Bluetooth](./bluetooth.md) - approach to bluetooth
+- [Kernel](./kernel.md) - kernel versions
+- [Boards](./boards/README.md) - board specific documentation

Documentation/boards/README.md

@@ -0,0 +1,53 @@
+# Boards
+
+## Overview
+
+The following boards/devices are supported:
+
+- Raspberry Pi
+  - Pi 4 Model B (1 GB, 2 GB and 4 GB model) 32-bit (recommended)
+  - Pi 4 Model B (1 GB, 2 GB and 4 GB model) 64-bit
+  - Pi 3 Model B and B+ 32-bit (recommended)
+  - Pi 3 Model B and B+ 64-bit
+  - Pi 2 (not recommended)
+  - Pi Zero-W (not recommended)
+  - Pi (not recommended)
+- Hardkernel
+  - Odroid-C2
+  - Odroid-N2
+  - Odroid-XU4
+- Intel NUC
+  - Intel NUC5CPYH
+  - Intel NUC6CAYH
+  - Intel NUC10I3FNK2
+  - Gigabyte GB-BPCE-3455
+  - Others recent Intel NUC computers are likely to work too, only those listed above have been tested.
+- Asus
+  - Tinker Board
+- Virtual appliance (x86_64/UEFI):
+  - VMDK
+  - OVA ?
+  - VHDX ?
+  - VDI ?
+  - QCOW2 ?
+
+Notes:
+  - see ? above: are these currently supported? see ova documentation which explains issues with previous OVA distribution)
+
+## Board specifics
+
+|Board|Build|Config|Docs|
+|-----|----|------|----|
+|Pi4B 32-bit |`make rpi4`      |[rpi4](../../buildroot-external/configs/rpi4_defconfig)|[raspberrypi](./raspberrypi/)|
+|Pi4B 64-bit |`make rpi4_64`   |[rpi4_64](../../buildroot-external/configs/rpi4_64_defconfig)|[raspberrypi](./raspberrypi/)|
+|Pi3B 32-bit |`make rpi3`      |[rpi3](../../buildroot-external/configs/rpi3_defconfig)|[raspberrypi](./raspberrypi/)|
+|Pi3B 64-bit |`make rpi3_64`   |[rpi3_64](../../buildroot-external/configs/rpi3_64_defconfig)|[raspberrypi](./raspberrypi/)|
+|Pi2         |`make rpi2`      |[rpi2](../../buildroot-external/configs/rpi2_defconfig)|[raspberrypi](./raspberrypi/)|
+|Pi Zero     |`make rpi0_w`    |[rpi0_w](../../buildroot-external/configs/rpi0_w_defconfig)|[raspberrypi](./raspberrypi/)|
+|Pi          |`make rpi`       |[rpi](../../buildroot-external/configs/rpi_defconfig)|[raspberrypi](./raspberrypi/)|
+|Odroid-C2   |`make odroid_c2` |[odroid_c2](../../buildroot-external/configs/odroid_c2_defconfig)|[hardkernel](./hardkernel/)|
+|Odroid-N2   |`make odroid_n2` |[odroid_n2](../../buildroot-external/configs/odroid_n2_defconfig)|[hardkernel](./hardkernel/)|
+|Odroid-XU4  |`make odroid_xu4`|[odroid_xu4](../../buildroot-external/configs/odroid_xu4_defconfig)|[hardkernel](./hardkernel/)|
+|NUC         |`make intel_nuc` |[intel_nuc](../../buildroot-external/configs/intel_nuc_defconfig)|[intel](./intel/)|
+|Tinker Board|`make tinker`    |[tinker](../../buildroot-external/configs/tinker_defconfig)|[asus](./asus/)|
+|OVA         |`make ova`       |[ova](../../buildroot-external/configs/ova_defconfig)|[ova](./ova/)|

Documentation/boards/asus/README.md

@@ -0,0 +1,21 @@
+# Tinker Board
+
+## Supported Hardware
+
+| Device         | Release Date  | Support | Config   |
+|----------------|---------------|---------|----------|
+| Tinker RK3288  | April 2017    | yes     | [tinker](../../../buildroot-external/configs/tinker_defconfig) |
+| Tinker S RK3288| January 2018  | yes?    | [tinker](../../../buildroot-external/configs/tinker_defconfig)? |
+| Tinker Edge T  | November 2019 | no?     |          |
+| Tinker Edge R  | November 2019 | no?     |          |
+
+(? is the Tinker S supported?)
+<!--
+## eMMC
+
+eMMC support is provided transparently. Just flash the image to the eMMC by connecting your Tinker Board S to your PC via Micro-USB.
+-->
+
+## Serial console
+
+To access the terminal over serial console, add `console=ttyS2,115200` to `cmdline.txt`. GPIO pins are: 34 = GND / 32 = UART TXD / 33 = UART RXD.

Documentation/boards/hardkernel/README.md

@@ -0,0 +1,11 @@
+# ODROID
+
+## Supported Hardware
+
+| Device         | Release Date  | Support | Config    |
+|----------------|---------------|---------|-----------|
+| ODROID-XU4     | 2015          | yes     | [odroid_xu4](../../../buildroot-external/configs/odroid_xu4_defconfig)|
+| ODROID-C2      | 2016          | yes     | [odroid_c2](../../../buildroot-external/configs/odroid_c2_defconfig) |
+| ODROID-N2      | 2019          | yes     | [odroid_n2](../../../buildroot-external/configs/odroid_n2_defconfig) |
+
+See separate documentation for each board.

Documentation/boards/hardkernel/odroid-xu4.md

@@ -1,22 +1,24 @@
-# Odroid-XU4
+# ODROID-XU4
 
 ## eMMC
 
-The Odroid XU4 has a hidden boot sector that is only visible on the Odroid itself (can't be written by a card reader). There are a couple possibilities:
-1) If the eMMC already had a working image before flashing HassOS:
-* It will be booting to uBoot (but no further). 
-    * If you have the serial adapter, you should be able to enter `distro_bootcmd` at the uboot prompt to continue booting.
-    * If not, flash the HassOS image to an SD card and boot off that temporarily (while the eMMC is also plugged in).
-* Once booted, login at the prompts and then enter `dd if=/dev/mmcblk0 of=/dev/mmcblk0boot0 bs=512 skip=63 seek=62 count=1440` at the linux prompt.
-* Reboot with eMMC (don't forget to flip the boot switch to eMMC)
-2) Clean/wiped/corruped boot sector:
-* You'll need to follow [Hardkernel's instructions](https://forum.odroid.com/viewtopic.php?f=53&t=6173) to get a working boot sector. Then flash HassOS and follow instructions above.
-* Alternatively, you can try flash HassOS to both an SD and eMMC, then boot off the SD with the eMMC also plugged in, then run `dd if=/dev/mmcblk1 of=/dev/mmcblk0boot0 bs=512 skip=1 seek=0 count=16381` at the Linux prompt. Note that this is untested, but in theory should work..
+The ODROID XU4 uses the eMMC boot partition to boot from. Typically eMMC readers can't write to this eMMC boot partition. There are a couple of possibilities:
+
+1. **Working** e.g. the eMMC already had a working image before flashing HassOS:
+   - It will be booting to U-Boot (but no further).
+     - If you have the serial adapter, you should be able to enter `distro_bootcmd` at the uboot prompt to continue booting.
+     - If not, flash the HassOS image to an SD card and boot off that temporarily (while the eMMC is also plugged in).
+   - Once booted, login at the prompts and then enter `dd if=/dev/mmcblk0 of=/dev/mmcblk0boot0 bs=512 skip=63 seek=62 count=1440` at the linux prompt.
+   - Reboot with eMMC (don't forget to flip the boot switch to eMMC)
+2. **Not Working** e.g. a clean/wiped/corruped eMMC boot partition:
+   - You'll need to follow [Hardkernel's instructions](https://forum.odroid.com/viewtopic.php?f=53&t=6173) to get a working boot sector. Then flash HassOS and follow instructions above.
+   - Alternatively, you can try flash HassOS to both an SD and eMMC, then boot off the SD with the eMMC also plugged in, then run `dd if=/dev/mmcblk1 of=/dev/mmcblk0boot0 bs=512 skip=1 seek=0 count=16381` at the Linux prompt. Note that this is untested, but in theory should work..
 
 If you are getting permissions issues when using the dd command, try disabling RO:
 `echo 0 > /sys/block/mmcblk0boot0/force_ro`
 to re-enable after running dd:
 `echo 1 > /sys/block/mmcblk0boot0/force_ro`
+
 ## Console
 
 By default, console access is granted over the serial header and over HDMI. Certain startup messages will only appear on the serial console by default. To show the messages on the HDMI console instead, swap the order of the two consoles in the `cmdline.txt` file on the boot partition. You can also delete the SAC2 console if you don't plan on using the serial adapter.

Documentation/boards/intel/README.md

@@ -1,9 +1,23 @@
 # Intel NUC
 
-This board configuration supports the Intel NUC mini PCs and compatibles. 
-Probably most recent computers will work.
+## Supported Hardware
+
+This board configuration supports the Intel NUC mini PCs and compatibles. It should work for most recent NUC computers and, because this is a UEFI based image, it should in fact work with for any x86-64 based computer with UEFI. Hardware it has been tested with is listed below.
+
+## Tested Hardware
+
+| Device                | Release Date | Support | Config      |
+|-----------------------|--------------|---------|-------------|
+| Intel NUC5CPYH        | Q3 2015      | yes     | [intel_nuc](../../../buildroot-external/configs/intel_nuc_defconfig) |
+| Intel NUC6CAYH        | Q4 2016      | yes     | [intel_nuc](../../../buildroot-external/configs/intel_nuc_defconfig) |
+| Intel NUC10i3FNK2     | Q4 2019      | yes     | [intel_nuc](../../../buildroot-external/configs/intel_nuc_defconfig) |
+| Gigabyte GB-BPCE-3455 | 2017         | yes*    | [intel_nuc](../../../buildroot-external/configs/intel_nuc_defconfig) |
+
+\* needs 'nomodeset' in cmdline.txt if you want a console
+
+
+## Requirements
 
-Requirements:
 - x86-64 support
 - UEFI boot
 - SATA/AHCI storage
@@ -13,16 +27,6 @@ Requirements:
   - Realtek Gigabit NIC (r8169)
   - Intel Wireless Wifi 802.11ac (iwlwifi, see below)
 
-## Tested Hardware
-
-| Device | Quirks | 
-|--------|-----------|
-| Intel NUC5CPYH |  |
-| Intel NUC6CAYH |  |
-| Intel NUC10I3FNK2 |  |
-| Gigabyte GB-BPCE-3455 | needs 'nomodeset' in cmdline.txt if you want a console |
-
-
 ## Wifi
 
 The following cards are supported:
@@ -50,4 +54,3 @@ Currently there is no shiny installation method. Checklist:
 - Copy or download the hassos image into your live environment
 - zcat the image to local harddisk
 - Reboot
-

Documentation/boards/ova.md

@@ -1,18 +0,0 @@
-# Virtual Machine
-
-Using this VMDK in a virtual machine requires the following:
-
-- Operating system: Other 4.x or later Linux (64-bit)
-- Enabled support for UEFI boot
-- SATA disk controller
-- Minimal of 1GB RAM
-- At least 2x vCPU
-- An assigned network
-
-# OVA (Open Virtual Appliance)
-
-Currently, we only publish a VMDK virtual disk, due to issues with our previous OVA distribution. We are currently investigating our options to bring back the OVA distribution. However, the VMDK works on the following hypervisors:
-
-- HyperV
-- VirtualBox
-- VMware

Documentation/boards/ova/README.md

@@ -0,0 +1,22 @@
+# Virtual Machine
+
+## Supported Hypervisors
+
+| Hypervisor          | Vendor    | Support         | Config             |
+|---------------------|-----------|-----------------|--------------------|
+| HyperV              | Microsoft | yes, via VMDK   | [ova](../../../buildroot-external/configs/ova_defconfig)              |
+| VirtualBox          | Oracle    | yes, via VMDK   | [ova](../../../buildroot-external/configs/ova_defconfig)              |
+| VMware              | VMware    | yes, via VMDK   | [ova](../../../buildroot-external/configs/ova_defconfig)              |
+
+Currently we only publish a VMDK virtual disk due to issues with our previous OVA distribution. We are investigating our options to bring back the OVA distribution, however, the VMDK works for the hypervisors listed above.
+
+## Requirements
+
+Using this VMDK in a virtual machine requires the following:
+
+- Operating system: Other 4.x or later Linux (64-bit)
+- Enabled support for UEFI boot
+- SATA disk controller
+- Minimal of 1GB RAM
+- At least 2x vCPU
+- An assigned network

Documentation/boards/raspberrypi.md

@@ -1,54 +0,0 @@
-# Raspberry PI
-
-Supported Hardware:
-
-| Device | Board |
-|--------|-----------|
-| Raspberry Pi A+/B/B+| rpi |
-| Raspberry Pi Zero | rpi |
-| Raspberry Pi Zero W | rpi0-w |
-| Raspberry Pi 2 B | rpi2 |
-| Raspberry Pi 3 B/B+ | rpi3 / rpi3-64 |
-| Raspberry Pi 4 B | rpi4 / rpi4-64 |
-
-## Limitation 64bit
-
-The 64bit version is under development by RPi-Team. It work very nice but it could have some impacts. Actual we see that the SDcard access with ext4 are a bit slower than on 32bit.
-
-## Serial console
-
-For access to terminal over serial console, add `console=ttyAMA0,115200` to `cmdline.txt` and `enable_uart=1`, `dtoverlay=pi3-disable-bt` into `config.txt`. GPIO pins are: 6 = GND / 8 = UART TXD / 10 = UART RXD.
-
-## I2C
-
-Add `dtparam=i2c1=on` and `dtparam=i2c_arm=on` to `config.txt`. After that we create a module file on host with [config usb stick][config] or direct into `/etc/modules-load.d`.
-
-rpi-i2c.conf:
-```
-i2c-dev
-i2c-bcm2708
-```
-
-## USB Boot
-
-USB mass storage boot is available on Raspberry Pi 4 (64-bit only), 3B, 3B+, 3A+, and 2B v1.2.
-
-For Raspberry 3B, 3A+ and 2B v1.2, to enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
-
-For Raspberry 4, make sure to update the bootloader to a stable release
-supporting USB mass storage boot (see
-[bcm2711_bootloader_config.md](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711_bootloader_config.md#usbmassstorageboot). If no SD card is used add `sd_poll_once=on` to `dtparam` in `config.txt` (comma separated). This gets rid of `mmc0: timeout waiting for hardware interrupt` kernel errors.
-
-For more information see [RaspberryPi](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/msd.md).
-
-### Caveats
-
-* All bootable SD cards must be removed.
-* Boot time can be significantly longer with USB. This is due to the boot process first attempting to boot from SD card, failing, and resorting to USB.
-* Many USB drives simply do not work for boot. This is likely due to minimal driver support in uboot and will not be fixed. If you can't get it to boot on one drive, try a different brand/model. SanDisk Cruzer drives seem to have a higher rate of issues.
-
-## Tweaks
-
-If you don't need bluetooth, disabled it with add `dtoverlay=pi3-disable-bt` into `config.txt`.
-
-[config]: ../configuration.md#automatic

Documentation/boards/raspberrypi/README.md

@@ -0,0 +1,51 @@
+# Raspberry PI
+
+## Supported Hardware
+
+| Device              | Release Date  | Support         | Config             |
+|---------------------|---------------|-----------------|--------------------|
+| Raspberry Pi B/B+/A+|2012/2014/2014 | not recommended | [rpi](../../../buildroot-external/configs/rpi_defconfig)              |
+| Raspberry Pi 2 B    |2015           | not recommended | [rpi2](../../../buildroot-external/configs/rpi2_defconfig)             |
+| Raspberry Pi Zero   |2015           | not recommended | [rpi](../../../buildroot-external/configs/rpi_defconfig)              |
+| Raspberry Pi Zero W |2017           | not recommended | [rpi0_w](../../../buildroot-external/configs/rpi0_w_defconfig)           |
+| Raspberry Pi 3 B/B+ |2016/2018      | yes             | [rpi3](../../../buildroot-external/configs/rpi3_defconfig) / [rpi3_64](../../../buildroot-external/configs/rpi3_64_defconfig) |
+| Raspberry Pi 4 B    |2019           | yes*            | [rpi4](../../../buildroot-external/configs/rpi4_defconfig) / [rpi4_64](../../../buildroot-external/configs/rpi4_64_defconfig) |
+
+\*1,2 and 4 GiB versions of the Raspberry Pi 4 B are supported. Support for the 8 GiB version is coming soon is part of #740.
+
+## Limitation 64bit
+
+The 64bit version is under development by RPi-Team. It work very nice but it could have some impacts. Actual we see that the SDcard access with ext4 are a bit slower than on 32bit.
+
+## Serial console
+
+For access to terminal over serial console, add `console=ttyAMA0,115200` to `cmdline.txt` and `enable_uart=1`, `dtoverlay=pi3-disable-bt` into `config.txt`. GPIO pins are: 6 = GND / 8 = UART TXD / 10 = UART RXD.
+
+## I2C
+
+Add `dtparam=i2c1=on` and `dtparam=i2c_arm=on` to `config.txt`. After that we create a module file on host with [config usb stick][config] or direct into `/etc/modules-load.d`.
+
+rpi-i2c.conf:
+```
+i2c-dev
+i2c-bcm2708
+```
+
+## USB Boot
+
+USB mass storage boot is available on Raspberry Pi 3B, 3B+, 3A+, and 2B v1.2.
+To enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
+
+For more information see [RaspberryPi](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/msd.md).
+
+### Caveats
+
+* All bootable SD cards must be removed.
+* Boot time can be significantly longer with USB. This is due to the boot process first attempting to boot from SD card, failing, and resorting to USB.
+* Many USB drives simply do not work for boot. This is likely due to minimal driver support in uboot and will not be fixed. If you can't get it to boot on one drive, try a different brand/model. SanDisk Cruzer drives seem to have a higher rate of issues.
+
+## Tweaks
+
+If you don't need bluetooth, disabled it with add `dtoverlay=pi3-disable-bt` into `config.txt`.
+
+[config]: ../configuration.md#automatic

Documentation/boards/tinker.md

@@ -1,19 +0,0 @@
-# Tinker Board
-
-Supported Hardware:
-
-| Device | Board | 
-|--------|-----------|
-| Tinker RK3288 | tinker |
-| Tinker S RK3288 |  |
-
-<!--
-## eMMC
-
-eMMC support is provided transparently. Just flash the image to the eMMC by connecting your Tinker Board S to your PC via Micro-USB.
--->
-
-## Serial console
-
-To access the terminal over serial console, add `console=ttyS2,115200` to `cmdline.txt`. GPIO pins are: 34 = GND / 32 = UART TXD / 33 = UART RXD.
-

Documentation/configuration.md

@@ -59,4 +59,4 @@ FallbackNTP=0.pool.ntp.org 1.pool.ntp.org 2.pool.ntp.org 3.pool.ntp.org
 [systemd-modules]: https://www.freedesktop.org/software/systemd/man/modules-load.d.html
 [network.md]: network.md
 [hassos-release]: https://github.com/home-assistant/hassos/releases/
-[debug-homeassistant]: https://developers.home-assistant.io/docs/operating-system/debugging
+[debug-homeassistant]: https://developers.home-assistant.io/docs/en/hassio_debugging.html

Documentation/deployment.md

@@ -2,8 +2,8 @@
 
 We provide 3 different types of release builds:
 
-- development (dev)
-- staging (beta)
+- development (beta/dev)
+- staging (rc)
 - production (stable)
 
 ## Versioning
@@ -15,7 +15,7 @@ The development number they will be bump for the stable release version and the
 
 The branch `dev` ist the actual development branch and from there we never make a release. The `master` branch contains the development version and from there we build a beta release.
 
-If we create a new productive/staging release, we create a new branch `rel-{MAJOR}`. They will be used for the whole cycle of this release.
+If we create a new productive release, we create a new branch `rel-{MAJOR}`. They will be used for the whole cycle of this release.
 
 ## Upload release files
 

Documentation/kernel.md

@@ -5,14 +5,14 @@ Default Kernel tree: 5.4
 
 | Board | Version |
 |-------|---------|
-| Open Virtual Applicance | 5.4.53 |
+| Open Virtual Appliance | 5.4.80 |
 | Raspberry Pi | 4.19.127 |
 | Raspberry Pi 0-W | 4.19.127 |
 | Raspberry Pi 2 | 4.19.127 |
 | Raspberry Pi 3 | 4.19.127 |
 | Raspberry Pi 4 | 4.19.127 |
-| Tinker Board | 5.4.53 |
-| Odroid-C2 | 5.7.10 |
-| Odroid-N2 | 5.7.10 |
-| Odroid-XU4 | 5.7.10 |
-| Intel NUC | 5.4.53 |
+| Tinker Board | 5.4.80 |
+| Odroid-C2 | 5.7.19 |
+| Odroid-N2 | 5.7.19 |
+| Odroid-XU4 | 5.7.19 |
+| Intel NUC | 5.4.80 |

Documentation/network.md

@@ -148,6 +148,6 @@ If you now view the default connection `cat /etc/NetworkManager/system-connectio
 
 Doing a `nmcli con reload` does not always work, so restart the virtual machine or the physical system.
 
-[nm-manual]: https://developer.gnome.org/NetworkManager/stable/NetworkManager.conf.html
+[nm-manual]: https://developer.gnome.org/NetworkManager/stable/nm-settings.html
 [configuration-usb]: configuration.md
 [uuid]: https://www.uuidgenerator.net/

Documentation/partition.md

@@ -1,6 +1,6 @@
 # Partition
 
-The partition layout is a bit different than for regular setups. We prefer GPT, if possible. With SoCs which don't support GPT, we use the hybrid GPT. For more details about this topic, please refer to the [development](development.md) documentation.
+The partition layout is a bit different than for regular setups. We prefer GPT, if possible. With SoCs which don't support GPT, we use the hybrid GPT. For more details about this topic, please refer to the [development](development.mnd) documentation.
 
 The system is designed to have as less as possible write operations on the storage media. Which means that we have basically only write during the OTA update and 5-6 times per week on the overlay part. The data partition is having I/O. This is the reason which is should be run on a different drive.
 
@@ -36,33 +36,12 @@ Sometime the bootloader part can look different because there can be firmware or
 
 ## Data
 
-The data partition is the only partition with real I/O. It will be expanded automatically at boot to the full size of the disk.
+The data partition is the only partition with real I/O. It will be expanded automatic on boot time to the full size of the disk.
 
-
-## Using datactl to move the data partition.
-
-In a Home Assistant OS installation, the data is stored on the `/mnt/data` partition of the SD card. This is the only read+write partition on the SD drive. Using the `datactl` move command, this partition can be moved off of the SD card onto an externally connected drive, leaving the rest of the read-only system on the SD.
-
-The storage capacity of the external drive must be larger than the storage capacity of the existing SD card.
-
-The command needs to be run from the host console by either connecting a keyboard and monitor or making use of the [debug ssh access](https://developers.home-assistant.io/docs/operating-system/debugging/) over port 22222. The command will not work from within an SSH add-on container.
-
-Log in as `root` to get to the Home Assistant CLI and then enter `login` to continue to the host.
-
-Confirm your USB SSD/HD is connected and recognized using `fdisk -l`.
-
-It is recommended to use fdisk to remove the existing partition(s) before proceeding.
-
-- Type `fdisk /dev/XXX` (replacing XXX with your drive)
-- Type `d` to delete a partition.
-- Continue if needed, then write the changes.
-
-Creating a new partition is not necessary.
-
-With the drive now prepared, use the below command (again, replacing XXX with your drive)
+This partition can be offloaded to a different drive with the utility:
 
 ```sh
 $ datactl move /dev/xxx
 ```
 
-Hit any key to continue, and then the move will happen after the next reboot. Once complete, the external drive will be owned and used by the system.
+On next boot, the partition will be moved to the new drive. The drive needs to be bigger as the old one and we own the full new drive.

README.md

@@ -1,18 +1,52 @@
-# Home Assistant Operating system
+# Home Assistant Operating System
 
-Home Assistant Operating System (HassOS) is based on [buildroot](https://buildroot.org/). It's a hypervisor for Docker and supports various kind of hardware. It is also available as virtual appliance for different virtualization solutions. The whole system is optimized for hosting [Home Assistant](https://www.home-assistant.io) and its features (to be precise, the [Add-ons](https://www.home-assistant.io/addons/)). You can update the system by using OTA updates or offline updates.
+Home Assistant Operating System (formerly HassOS) is an operating system optimized for hosting [Home Assistant](https://www.home-assistant.io) and its [Add-ons](https://www.home-assistant.io/addons/).
 
-This is an embedded Linux which works different than a normal Linux distribution. The system is designed to run with minimal I/O and is optimized for its tasks.
+Home Assistant Operating System uses Docker as Container engine. It by default deploys the Home Assistant Supervisor as a container. Home Assistant Supervisor in turn uses the Docker container engine to control Home Assistant Core and Add-Ons in separate containers. Home Assistant Operating System is **not** based on a regular Linux distribution like Ubuntu. It is built using [buildroot](https://buildroot.org/) and it is optimized for running Home Assistant, especially on single board compute (SBC) devices like the Pi, ODROID, NUC and Tinker Board (see supported hardware below).
 
-If you don't have experience with embedded systems, buildroot or the build process Linux distributions, then please read up on those topics. All provided documentation here is focusing on developers with a background on embedded systems or a strong understanding of the internal workings of operating systems.
+## Features
 
-## Focus
+- Lightweight and memory-efficient
+- Minimized I/O
+- Over The Air (OTA) updates
+- Offline updates
+- Modular using Docker
 
-- Barebox as bootloader on EFI
-- U-Boot as bootloader
-- Linux/Buildroot LTS
-- RAUC for OTA updates
-- SquashFS LZ4 as filesystem
-- Docker-CE
-- AppArmor protected
-- ZRAM LZ4 for `/tmp`, `/var` and swap
+## Supported hardware
+
+- Raspberry Pi
+- Hardkernel ODROID
+- Intel NUC
+- Asus Tinker Board
+- Virtual appliances
+
+See full list and specific models [here](./Documentation/boards/README.md)
+
+## Getting Started
+
+If you just want to use Home Assistant the official [getting started guide](https://www.home-assistant.io/getting-started/) and [installation instructions](https://www.home-assistant.io/hassio/installation/) take you through how to download Home Assistant Operating System and get it running on your machine.
+
+If you're interested in finding out more about Home Assistant Operating System and how it works read on...
+
+## HassOS components
+
+- **Bootloader:**
+  - [Barebox](https://barebox.org/) for devices that support EFI
+  - [U-Boot](https://www.denx.de/wiki/U-Boot) for devices that don't support EFI
+- **Operating System:**
+  - [Buildroot](https://buildroot.org/) LTS Linux
+- **File Systems:**
+  - [SquashFS](https://www.kernel.org/doc/Documentation/filesystems/squashfs.txt) for read-only file systems (using LZ4 compression)
+  - [ZRAM](https://www.kernel.org/doc/Documentation/blockdev/zram.txt) for `/tmp`, `/var` and swap (using LZ4 compression)
+- **Container Platform:**
+  - [Docker Engine](https://docs.docker.com/engine/) for running Home Assistant components in containers
+- **Updates:**
+  - [RAUC](https://rauc.io/) for Over The Air (OTA) and USB updates
+- **Security:**
+  - [AppArmor](https://apparmor.net/) Linux kernel security module
+
+If you don't have experience with these, embedded systems, buildroot or the build process for Linux distributions, then please read up on these topics. The rest of the documentation in this project is for developers and assumes you have experience of embedded systems or a strong understanding of the internal workings of operating systems.
+
+## Developer Documentation
+
+All developer documentation is in the [Documentation](./Documentation) directory.

azure-pipelines-ci.yml

@@ -46,8 +46,8 @@ jobs:
           scripts/*.sh \
           buildroot-external/scripts/*.sh \
           buildroot-external/board/**/*.sh \
+          buildroot-external/ota/rauc-hook \
           buildroot-external/rootfs-overlay/usr/bin/* \
           buildroot-external/rootfs-overlay/usr/sbin/* \
           buildroot-external/rootfs-overlay/usr/libexec/* \
-          buildroot-external/rootfs-overlay/usr/lib/rauc/*
     displayName: 'Run ShellCheck'

buildroot-external/board/asus/tinker/patches/linux/2007-drivers-wifi-ath9k-reverse-do-not-use-bulk-on-EP3-and-EP4.patch

@@ -27,9 +27,9 @@ diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath
  
  	usb_anchor_urb(urb, &hif_dev->regout_submitted);
  	ret = usb_submit_urb(urb, GFP_KERNEL);
-@@ -723,11 +723,11 @@
- 			return;
- 		}
+@@ -735,11 +735,11 @@
+ 
+ 		rx_buf->skb = nskb;
  
 +		usb_fill_bulk_urb(urb, hif_dev->udev,
 +				 usb_rcvbulkpipe(hif_dev->udev,
@@ -38,7 +38,7 @@ diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath
  						 USB_REG_IN_PIPE),
  				 nskb->data, MAX_REG_IN_BUF_SIZE,
 +				 ath9k_hif_usb_reg_in_cb, nskb);
--				 ath9k_hif_usb_reg_in_cb, nskb, 1);
+-				 ath9k_hif_usb_reg_in_cb, rx_buf, 1);
  	}
  
  resubmit:

buildroot-external/board/asus/tinker/uboot-boot.ush

@@ -36,16 +36,17 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
   elif test "x${BOOT_SLOT}" = "xA"; then
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
-      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:2 ${kernel_addr_r} zImage"
-      setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
+      echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:2 ${kernel_addr_r} zImage; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
+      fi
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
-      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:4 ${kernel_addr_r} zImage"
-      setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
+      echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:4 ${kernel_addr_r} zImage"; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
     fi
   fi
 done
@@ -60,10 +61,8 @@ else
   reset
 fi
 
-echo "Loading kernel"
-run load_kernel
-echo " Starting kernel"
+echo "Starting kernel"
 bootz ${kernel_addr_r} - ${fdt_addr_r}
 
-echo "Fails on boot"
+echo "Boot failed, resetting..."
 reset

buildroot-external/board/hardkernel/kernel-amlogic.config

@@ -4954,7 +4954,7 @@ CONFIG_RTC_DRV_RK808=m
 # CONFIG_RTC_DRV_PCF8523 is not set
 # CONFIG_RTC_DRV_PCF85063 is not set
 # CONFIG_RTC_DRV_PCF85363 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
+CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_BQ32K is not set

buildroot-external/board/hardkernel/odroid-c2/uboot-boot.ush

@@ -18,13 +18,6 @@ test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"
 test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3
 test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3
 
-if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
-  env import -t ${ramdisk_addr_r} ${filesize};
-fi
-
-# Board bootargs
-setenv bootargs_odroidc2 ""
-
 # HassOS bootargs
 setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor systemd.machine_id=${MACHINE_ID} cgroup_enable=memory"
 
@@ -32,8 +25,6 @@ setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=ap
 setenv bootargs_a "root=PARTUUID=48617373-06 rootfstype=squashfs ro rootwait"
 setenv bootargs_b "root=PARTUUID=48617373-08 rootfstype=squashfs ro rootwait"
 
-usb start
-
 # Load extraargs
 fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
 fatload mmc ${devnum}:1 ${fdt_addr_r} meson-gxbb-odroidc2.dtb
@@ -55,16 +46,18 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
   elif test "x${BOOT_SLOT}" = "xA"; then
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
-      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:5 ${kernel_addr_r} Image"
-      setenv bootargs "${bootargs_hassos} ${bootargs_odroidc2} ${bootargs_a} rauc.slot=A ${cmdline}"
+      echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:5 ${kernel_addr_r} Image; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
+      fi
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
-      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:7 ${kernel_addr_r} Image"
-      setenv bootargs "${bootargs_hassos} ${bootargs_odroidc2} ${bootargs_b} rauc.slot=B ${cmdline}"
+      echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:7 ${kernel_addr_r} Image; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
+      fi
     fi
   fi
 done
@@ -79,12 +72,9 @@ else
   reset
 fi
 
-echo "Loading kernel"
-run load_kernel
-echo " Starting kernel"
-printenv load_kernel
 printenv bootargs
+echo "Starting kernel"
 booti ${kernel_addr_r} - ${fdt_addr_r}
 
-echo "Fails on boot"
+echo "Boot failed, resetting..."
 reset

buildroot-external/board/hardkernel/odroid-c2/uboot.config

@@ -1,3 +1,4 @@
 CONFIG_DOS_PARTITION=y
 # CONFIG_EFI_PARTITION is not set
 # CONFIG_USB_STORAGE is not set
+CONFIG_DISPLAY_BOARDINFO=y

buildroot-external/board/hardkernel/odroid-n2/hassos-hook.sh

@@ -7,7 +7,7 @@ function hassos_pre_image() {
     local SPL_IMG="$(path_spl_img)"
 
     cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
-    cp "${BINARIES_DIR}/meson-g12b-odroid-n2.dtb" "${BOOT_DATA}/meson-g12b-odroid-n2.dtb"
+    cp "${BINARIES_DIR}"/*.dtb "${BOOT_DATA}/"
 
     echo "console=tty0 console=ttyAML0,115200n8" > "${BOOT_DATA}/cmdline.txt"
 

buildroot-external/board/hardkernel/odroid-n2/kernel.config

@@ -0,0 +1 @@
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y

buildroot-external/board/hardkernel/odroid-n2/uboot-boot.ush

@@ -18,13 +18,6 @@ test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"
 test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3
 test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3
 
-if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
-  env import -t ${ramdisk_addr_r} ${filesize};
-fi
-
-# Board bootargs
-setenv bootargs_odroidn2 ""
-
 # HassOS bootargs
 setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor systemd.machine_id=${MACHINE_ID} cgroup_enable=memory"
 
@@ -32,11 +25,13 @@ setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=ap
 setenv bootargs_a "root=PARTUUID=48617373-06 rootfstype=squashfs ro rootwait"
 setenv bootargs_b "root=PARTUUID=48617373-08 rootfstype=squashfs ro rootwait"
 
-usb start
-
 # Load extraargs
 fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
-fatload mmc ${devnum}:1 ${fdt_addr_r} meson-g12b-odroid-n2.dtb
+if test "${board_rev}" = "c"; then
+  fatload mmc ${devnum}:1 ${fdt_addr_r} meson-g12b-odroid-n2-plus.dtb
+else
+  fatload mmc ${devnum}:1 ${fdt_addr_r} meson-g12b-odroid-n2.dtb
+fi
 
 # logical volumes get numbered after physical ones.
 # 1. boot
@@ -55,16 +50,18 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
   elif test "x${BOOT_SLOT}" = "xA"; then
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
-      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:5 ${kernel_addr_r} Image"
-      setenv bootargs "${bootargs_hassos} ${bootargs_odroidn2} ${bootargs_a} rauc.slot=A ${cmdline}"
+      echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:5 ${kernel_addr_r} Image; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
+      fi
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
-      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:7 ${kernel_addr_r} Image"
-      setenv bootargs "${bootargs_hassos} ${bootargs_odroidn2} ${bootargs_b} rauc.slot=B ${cmdline}"
+      echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:7 ${kernel_addr_r} Image; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
+      fi
     fi
   fi
 done
@@ -79,12 +76,9 @@ else
   reset
 fi
 
-echo "Loading kernel"
-run load_kernel
-echo " Starting kernel"
-printenv load_kernel
 printenv bootargs
+echo "Starting kernel"
 booti ${kernel_addr_r} - ${fdt_addr_r}
 
-echo "Fails on boot"
+echo "Boot failed, resetting..."
 reset

buildroot-external/board/hardkernel/odroid-n2/uboot.config

@@ -1,3 +1,4 @@
 CONFIG_DOS_PARTITION=y
 # CONFIG_EFI_PARTITION is not set
 # CONFIG_USB_STORAGE is not set
+CONFIG_DISPLAY_BOARDINFO=y

buildroot-external/board/hardkernel/odroid-xu4/uboot-boot.ush

@@ -20,13 +20,6 @@ test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"
 test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3
 test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3
 
-if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
-  env import -t ${ramdisk_addr_r} ${filesize};
-fi
-
-# Board bootargs
-setenv bootargs_odroidxu4 ""
-
 # HassOS bootargs
 setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor systemd.machine_id=${MACHINE_ID} cgroup_enable=memory"
 
@@ -34,8 +27,6 @@ setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=ap
 setenv bootargs_a "root=PARTUUID=48617373-06 rootfstype=squashfs ro rootwait"
 setenv bootargs_b "root=PARTUUID=48617373-08 rootfstype=squashfs ro rootwait"
 
-#usb start
-
 # Load extraargs
 fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
 fatload mmc ${devnum}:1 ${fdt_addr_r} exynos5422-odroidxu4.dtb
@@ -59,16 +50,18 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
   elif test "x${BOOT_SLOT}" = "xA"; then
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
-      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:5 ${kernel_addr_r} zImage"
-      setenv bootargs "${bootargs_hassos} ${bootargs_odroidxu4} ${bootargs_a} rauc.slot=A ${cmdline}"
+      echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:5 ${kernel_addr_r} zImage; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
+      fi
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
-      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc ${devnum}:7 ${kernel_addr_r} zImage"
-      setenv bootargs "${bootargs_hassos} ${bootargs_odroidxu4} ${bootargs_b} rauc.slot=B ${cmdline}"
+      echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load mmc ${devnum}:7 ${kernel_addr_r} zImage; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
+      fi
     fi
   fi
 done
@@ -83,13 +76,9 @@ else
   reset
 fi
 
-echo "Loading kernel"
-run load_kernel
-echo " Starting kernel"
-printenv load_kernel
 printenv bootargs
-dmc ${ddr_freq}
-bootz ${kernel_addr_r} - ${fdt_addr_r}
+echo "Starting kernel"
+booti ${kernel_addr_r} - ${fdt_addr_r}
 
-echo "Fails on boot"
+echo "Boot failed, resetting..."
 reset

buildroot-external/board/hardkernel/patches/linux/0001-arm64-defconfig-enable-meson-gx-audio-as-module.patch

@@ -1,7 +1,8 @@
-From e2b93751cfd0722801b65b4603b588ab9df4c12b Mon Sep 17 00:00:00 2001
+From 59bbf3567b02c36edfa4ee013d7e7e8c492756f2 Mon Sep 17 00:00:00 2001
+Message-Id: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Tue, 21 Apr 2020 18:39:30 +0200
-Subject: [PATCH 2/8] arm64: defconfig: enable meson gx audio as module
+Subject: [PATCH 01/14] arm64: defconfig: enable meson gx audio as module
 
 Enable the module config for the Amlogic GX audio card.
 This module will imply the internal components usually associated
@@ -39,5 +40,5 @@ index 03d0189f7d68..ceb60ee9c340 100644
  CONFIG_SND_SOC_WCD934X=m
  CONFIG_SND_SOC_WSA881X=m
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0002-ASoC-meson-imply-acodec-glue-on-axg-sound-card.patch

@@ -1,7 +1,10 @@
-From 821b8ac21b1675910423ee69d37cb1977b8f271e Mon Sep 17 00:00:00 2001
+From 4684d42cbbbb2d0331eb273229c9856a09b8d687 Mon Sep 17 00:00:00 2001
+Message-Id: <4684d42cbbbb2d0331eb273229c9856a09b8d687.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Mon, 30 Mar 2020 17:39:04 +0200
-Subject: [PATCH 3/8] ASoC: meson: imply acodec glue on axg sound card
+Subject: [PATCH 02/14] ASoC: meson: imply acodec glue on axg sound card
 
 When axg card driver support is enabled, lets enable the related
 internal DAC glue by default.
@@ -24,5 +27,5 @@ index 8b6295283989..363dc3b1bbe4 100644
  	help
  	  Select Y or M to add support for the AXG SoC sound card
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0003-ASoC-meson-gx-card-fix-sound-dai-dt-schema.patch

@@ -1,7 +1,10 @@
-From 60164df03c6314d8f5f3afef56b0bf97962ec9ee Mon Sep 17 00:00:00 2001
+From 07eb6dcfc912281b3c4ad598d8cfd3b7548fc965 Mon Sep 17 00:00:00 2001
+Message-Id: <07eb6dcfc912281b3c4ad598d8cfd3b7548fc965.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Mon, 24 Feb 2020 14:35:17 +0100
-Subject: [PATCH 4/8] ASoC: meson: gx-card: fix sound-dai dt schema
+Subject: [PATCH 03/14] ASoC: meson: gx-card: fix sound-dai dt schema
 
 There is a fair amount of warnings when running 'make dtbs_check' with
 amlogic,gx-sound-card.yaml.
@@ -43,5 +46,5 @@ index fb374c659be1..a48222e8cd08 100644
  
          required:
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0004-arm64-dts-meson-g12-add-internal-DAC.patch

@@ -1,7 +1,10 @@
-From e128dd1ca079c5ee558ab100387d9f81bd4f3980 Mon Sep 17 00:00:00 2001
+From 5f7bab7b52bc68738dd23af62a085dcc45c22f79 Mon Sep 17 00:00:00 2001
+Message-Id: <5f7bab7b52bc68738dd23af62a085dcc45c22f79.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Thu, 7 May 2020 00:16:55 +0200
-Subject: [PATCH 5/8] arm64: dts: meson: g12: add internal DAC
+Subject: [PATCH 04/14] arm64: dts: meson: g12: add internal DAC
 
 add internal audio DAC support on the g12 and sm1 SoC family
 
@@ -16,7 +19,7 @@ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot
 index c0aef7d69117..593a006f4b7b 100644
 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
 +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
-@@ -250,6 +250,17 @@
+@@ -250,6 +250,17 @@ hwrng: rng@218 {
  				};
  			};
  
@@ -35,5 +38,5 @@ index c0aef7d69117..593a006f4b7b 100644
  				compatible = "simple-bus";
  				reg = <0x0 0x34400 0x0 0x400>;
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0005-arm64-dts-meson-g12-add-internal-DAC-glue.patch

@@ -1,7 +1,10 @@
-From 5ea4085da165fd3f3aa211cb3664dd166d0d5fd7 Mon Sep 17 00:00:00 2001
+From e7d1f61513cfe9d2557fbd0ac981a3ecaab9bc70 Mon Sep 17 00:00:00 2001
+Message-Id: <e7d1f61513cfe9d2557fbd0ac981a3ecaab9bc70.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Thu, 7 May 2020 00:16:56 +0200
-Subject: [PATCH 6/8] arm64: dts: meson: g12: add internal DAC glue
+Subject: [PATCH 05/14] arm64: dts: meson: g12: add internal DAC glue
 
 add the internal DAC glue support on the g12 and sm1 family
 This glue connects the different TDM interfaces of the SoC to
@@ -18,7 +21,7 @@ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi b/arch/arm64/boot/dts/am
 index 55d39020ec72..0d14409f509c 100644
 --- a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
 +++ b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi
-@@ -343,6 +343,15 @@
+@@ -343,6 +343,15 @@ spdifout_b: audio-controller@680 {
  			status = "disabled";
  		};
  
@@ -35,5 +38,5 @@ index 55d39020ec72..0d14409f509c 100644
  			compatible = "amlogic,g12a-tohdmitx";
  			reg = <0x0 0x744 0x0 0x4>;
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0006-arm64-dts-meson-g12b-odroid-n2-enable-audio-loopback.patch

@@ -1,7 +1,11 @@
-From 15b3cef2ea75c4d81cb067264be1cf49c49f81b1 Mon Sep 17 00:00:00 2001
+From a778ae244b9e6035ef4c0e4fb36d81f140ed5019 Mon Sep 17 00:00:00 2001
+Message-Id: <a778ae244b9e6035ef4c0e4fb36d81f140ed5019.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Mon, 15 Jun 2020 15:38:44 +0200
-Subject: [PATCH 7/8] arm64: dts: meson-g12b: odroid-n2: enable audio loopback
+Subject: [PATCH 06/14] arm64: dts: meson-g12b: odroid-n2: enable audio
+ loopback
 
 Add capture pcm interfaces and loopback routes to the odroid-n2
 
@@ -14,7 +18,7 @@ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/b
 index 169ea283d4ee..d4421ad164bd 100644
 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
 +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
-@@ -209,11 +209,28 @@
+@@ -209,11 +209,28 @@ hdmi_connector_in: endpoint {
  	sound {
  		compatible = "amlogic,axg-sound-card";
  		model = "G12B-ODROID-N2";
@@ -45,7 +49,7 @@ index 169ea283d4ee..d4421ad164bd 100644
  
  		assigned-clocks = <&clkc CLKID_MPLL2>,
  				  <&clkc CLKID_MPLL0>,
-@@ -236,8 +253,20 @@
+@@ -236,8 +253,20 @@ dai-link-2 {
  			sound-dai = <&frddr_c>;
  		};
  
@@ -67,7 +71,7 @@ index 169ea283d4ee..d4421ad164bd 100644
  			sound-dai = <&tdmif_b>;
  			dai-format = "i2s";
  			dai-tdm-slot-tx-mask-0 = <1 1>;
-@@ -252,7 +281,7 @@
+@@ -252,7 +281,7 @@ codec {
  		};
  
  		/* hdmi glue */
@@ -76,7 +80,7 @@ index 169ea283d4ee..d4421ad164bd 100644
  			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
  
  			codec {
-@@ -476,6 +505,22 @@
+@@ -476,6 +505,22 @@ &tdmif_b {
  	status = "okay";
  };
  
@@ -99,7 +103,7 @@ index 169ea283d4ee..d4421ad164bd 100644
  &tdmout_b {
  	status = "okay";
  };
-@@ -484,6 +529,18 @@
+@@ -484,6 +529,18 @@ &tohdmitx {
  	status = "okay";
  };
  
@@ -119,5 +123,5 @@ index 169ea283d4ee..d4421ad164bd 100644
  	status = "okay";
  	pinctrl-0 = <&uart_ao_a_pins>;
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0007-arm64-dts-meson-odroid-n2-add-jack-audio-output-supp.patch

@@ -1,7 +1,10 @@
-From 978cc250574b7f1ab45f494cc2a094e3c9fd1fa4 Mon Sep 17 00:00:00 2001
+From 26603168f26468ac1872fcbcd703d2cd5a626310 Mon Sep 17 00:00:00 2001
+Message-Id: <26603168f26468ac1872fcbcd703d2cd5a626310.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
 From: Jerome Brunet <jbrunet@baylibre.com>
 Date: Mon, 15 Jun 2020 16:34:37 +0200
-Subject: [PATCH 8/8] arm64: dts: meson: odroid-n2: add jack audio output
+Subject: [PATCH 07/14] arm64: dts: meson: odroid-n2: add jack audio output
  support
 
 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
@@ -21,7 +24,7 @@ index d4421ad164bd..34fffa6d859d 100644
  #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
  
  / {
-@@ -20,6 +21,14 @@
+@@ -20,6 +21,14 @@ aliases {
  		ethernet0 = &ethmac;
  	};
  
@@ -36,7 +39,7 @@ index d4421ad164bd..34fffa6d859d 100644
  	chosen {
  		stdout-path = "serial0:115200n8";
  	};
-@@ -209,16 +218,26 @@
+@@ -209,16 +218,26 @@ hdmi_connector_in: endpoint {
  	sound {
  		compatible = "amlogic,axg-sound-card";
  		model = "G12B-ODROID-N2";
@@ -65,7 +68,7 @@ index d4421ad164bd..34fffa6d859d 100644
  				"TODDR_A IN 0", "TDMIN_A OUT",
  				"TODDR_B IN 0", "TDMIN_A OUT",
  				"TODDR_C IN 0", "TDMIN_A OUT",
-@@ -230,7 +249,11 @@
+@@ -230,7 +249,11 @@ sound {
  				"TODDR_C IN 2", "TDMIN_C OUT",
  				"TODDR_A IN 6", "TDMIN_LB OUT",
  				"TODDR_B IN 6", "TDMIN_LB OUT",
@@ -78,7 +81,7 @@ index d4421ad164bd..34fffa6d859d 100644
  
  		assigned-clocks = <&clkc CLKID_MPLL2>,
  				  <&clkc CLKID_MPLL0>,
-@@ -275,22 +298,56 @@
+@@ -275,22 +298,56 @@ dai-link-6 {
  			dai-tdm-slot-tx-mask-3 = <1 1>;
  			mclk-fs = <256>;
  
@@ -137,7 +140,7 @@ index d4421ad164bd..34fffa6d859d 100644
  &arb {
  	status = "okay";
  };
-@@ -505,6 +562,10 @@
+@@ -505,6 +562,10 @@ &tdmif_b {
  	status = "okay";
  };
  
@@ -148,7 +151,7 @@ index d4421ad164bd..34fffa6d859d 100644
  &tdmin_a {
  	status = "okay";
  };
-@@ -525,6 +586,14 @@
+@@ -525,6 +586,14 @@ &tdmout_b {
  	status = "okay";
  };
  
@@ -164,5 +167,5 @@ index d4421ad164bd..34fffa6d859d 100644
  	status = "okay";
  };
 -- 
-2.17.1
+2.29.1
 

buildroot-external/board/hardkernel/patches/linux/0008-dt-bindings-arm-amlogic-add-support-for-the-ODROID-N.patch

@@ -0,0 +1,37 @@
+From 40c86a409f3fa18c3f30bad3abeccff04379eaa9 Mon Sep 17 00:00:00 2001
+Message-Id: <40c86a409f3fa18c3f30bad3abeccff04379eaa9.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 15 Sep 2020 17:24:31 +0200
+Subject: [PATCH 08/14] dt-bindings: arm: amlogic: add support for the
+ ODROID-N2+
+
+HardKernel ODROID-N2+ uses a revised Amlogic S922X v2 chip that supports
+higher cpu clock speeds than the original ODROID-N2.
+
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Kevin Hilman <khilman@baylibre.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Link: https://lore.kernel.org/r/20200915152432.30616-3-narmstrong@baylibre.com
+---
+ Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
+index f74aba48cec1..915ef4f355ad 100644
+--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
++++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
+@@ -149,6 +149,7 @@ properties:
+         items:
+           - enum:
+               - hardkernel,odroid-n2
++              - hardkernel,odroid-n2-plus
+               - khadas,vim3
+               - ugoos,am6
+           - const: amlogic,s922x
+-- 
+2.29.1
+

buildroot-external/board/hardkernel/patches/linux/0010-arm64-dts-meson-add-support-for-the-ODROID-N2.patch

@@ -0,0 +1,78 @@
+From 45ac6c04283dce57e0e911d5dc794eeb9446394c Mon Sep 17 00:00:00 2001
+Message-Id: <45ac6c04283dce57e0e911d5dc794eeb9446394c.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+From: Christian Hewitt <christianshewitt@gmail.com>
+Date: Tue, 15 Sep 2020 17:24:32 +0200
+Subject: [PATCH 10/14] arm64: dts: meson: add support for the ODROID-N2+
+
+HardKernel ODROID-N2+ uses an Amlogic S922X rev. C chip capable of higher
+clock speeds than the original ODROID-N2.
+
+The rev. C support a slighly higher VDDCPU_A & VDDCPU_B voltages and supports
+the same OPPs as the Amlogic A311D SoC from the same G12B family.
+
+Suggested-by: Dongjin Kim <tobetter@hardkernel.com>
+Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Kevin Hilman <khilman@baylibre.com>
+Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Link: https://lore.kernel.org/r/20200915152432.30616-4-narmstrong@baylibre.com
+---
+ arch/arm64/boot/dts/amlogic/Makefile          |  1 +
+ .../dts/amlogic/meson-g12b-odroid-n2-plus.dts | 31 +++++++++++++++++++
+ 2 files changed, 32 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
+
+diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
+index eef0045320f2..7524cf9680f5 100644
+--- a/arch/arm64/boot/dts/amlogic/Makefile
++++ b/arch/arm64/boot/dts/amlogic/Makefile
+@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
++dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
+new file mode 100644
+index 000000000000..5de2815ba99d
+--- /dev/null
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
+@@ -0,0 +1,31 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 BayLibre, SAS
++ * Author: Neil Armstrong <narmstrong@baylibre.com>
++ */
++
++/dts-v1/;
++
++/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */
++#include "meson-g12b-a311d.dtsi"
++#include "meson-g12b-odroid-n2.dtsi"
++
++/ {
++	compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b";
++	model = "Hardkernel ODROID-N2Plus";
++};
++
++&vddcpu_a {
++	regulator-min-microvolt = <680000>;
++	regulator-max-microvolt = <1040000>;
++
++	pwms = <&pwm_AO_cd 1 1500 0>;
++};
++
++&vddcpu_b {
++	regulator-min-microvolt = <680000>;
++	regulator-max-microvolt = <1040000>;
++
++	pwms = <&pwm_AO_cd 1 1500 0>;
++};
++
+-- 
+2.29.1
+

buildroot-external/board/hardkernel/patches/linux/0011-arm64-dts-meson-add-missing-g12-rng-clock.patch

@@ -0,0 +1,38 @@
+From ab2773aa8ea7ff7f30c104bd3a1f93b67c5eac32 Mon Sep 17 00:00:00 2001
+Message-Id: <ab2773aa8ea7ff7f30c104bd3a1f93b67c5eac32.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+From: Scott K Logan <logans@cottsay.net>
+Date: Fri, 25 Sep 2020 01:43:53 -0700
+Subject: [PATCH 11/14] arm64: dts: meson: add missing g12 rng clock
+
+This adds the missing perpheral clock for the RNG for Amlogic G12. As
+stated in amlogic,meson-rng.yaml, this isn't always necessary for the
+RNG to function, but is better to have in case the clock is disabled for
+some reason prior to loading.
+
+Signed-off-by: Scott K Logan <logans@cottsay.net>
+Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Kevin Hilman <khilman@baylibre.com>
+Link: https://lore.kernel.org/r/520a1a8ec7a958b3d918d89563ec7e93a4100a45.camel@cottsay.net
+---
+ arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+index 593a006f4b7b..6ec40af658ba 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+@@ -247,6 +247,8 @@ apb_efuse: bus@30000 {
+ 				hwrng: rng@218 {
+ 					compatible = "amlogic,meson-rng";
+ 					reg = <0x0 0x218 0x0 0x4>;
++					clocks = <&clkc CLKID_RNG0>;
++					clock-names = "core";
+ 				};
+ 			};
+ 
+-- 
+2.29.1
+

buildroot-external/board/hardkernel/patches/linux/0012-arm64-dts-meson-odroid-n2-plus-fix-vddcpu_a-pwm.patch

@@ -0,0 +1,42 @@
+From 28967338d3222c1ef2e1ee7372ec857aab43589b Mon Sep 17 00:00:00 2001
+Message-Id: <28967338d3222c1ef2e1ee7372ec857aab43589b.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Fri, 23 Oct 2020 11:41:39 +0200
+Subject: [PATCH 12/14] arm64: dts: meson: odroid-n2 plus: fix vddcpu_a pwm
+
+On the odroid N2 plus, cpufreq is not available due to an error on the cpu
+regulators. vddcpu a and b get the same PWM. The one provided to vddcpu A
+is incorrect. Because vddcpu B PWM is busy the regulator cannot register:
+
+> pwm-regulator regulator-vddcpu-b: Failed to get PWM: -16
+
+Like on the odroid n2, use PWM A out of GPIOE_2 for vddcpu A to fix the
+problem
+
+Fixes: 98d24896ee11 ("arm64: dts: meson: add support for the ODROID-N2+")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Acked-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Kevin Hilman <khilman@baylibre.com>
+Link: https://lore.kernel.org/r/20201023094139.809379-1-jbrunet@baylibre.com
+---
+ arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
+index 5de2815ba99d..ce1198ad34e4 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
+@@ -19,7 +19,7 @@ &vddcpu_a {
+ 	regulator-min-microvolt = <680000>;
+ 	regulator-max-microvolt = <1040000>;
+ 
+-	pwms = <&pwm_AO_cd 1 1500 0>;
++	pwms = <&pwm_ab 0 1500 0>;
+ };
+ 
+ &vddcpu_b {
+-- 
+2.29.1
+

buildroot-external/board/hardkernel/patches/linux/0013-clk-meson-g12a-mark-fclk_div2-as-critical.patch

@@ -0,0 +1,38 @@
+From b65f3fd306972087aa43e91ab0951b19883a21f7 Mon Sep 17 00:00:00 2001
+Message-Id: <b65f3fd306972087aa43e91ab0951b19883a21f7.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Thu, 27 Aug 2020 23:29:57 +0200
+Subject: [PATCH 13/14] clk: meson: g12a: mark fclk_div2 as critical
+
+On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2
+seems to be necessary for the system to operate correctly as well.
+
+Typically, the clock also gets chosen by the eMMC peripheral. This
+probably masked the problem so far. However, when booting from a SD
+card the clock seems to get disabled which leads to a system freeze.
+
+Let's mark this clock as critical, fixing boot from SD card on G12b
+platforms.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ drivers/clk/meson/g12a.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
+index fad616cac01e..2214b974f748 100644
+--- a/drivers/clk/meson/g12a.c
++++ b/drivers/clk/meson/g12a.c
+@@ -298,6 +298,7 @@ static struct clk_regmap g12a_fclk_div2 = {
+ 			&g12a_fclk_div2_div.hw
+ 		},
+ 		.num_parents = 1,
++		.flags = CLK_IS_CRITICAL,
+ 	},
+ };
+ 
+-- 
+2.29.1
+

buildroot-external/board/hardkernel/patches/linux/0014-usb-cdc-acm-fix-cooldown-mechanism.patch

@@ -0,0 +1,126 @@
+From 83fb88f53712d309ee106cdbd1dfe228d1649918 Mon Sep 17 00:00:00 2001
+Message-Id: <83fb88f53712d309ee106cdbd1dfe228d1649918.1603880585.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1603880585.git.stefan@agner.ch>
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 19 Oct 2020 19:07:02 +0200
+Subject: [PATCH 14/14] usb: cdc-acm: fix cooldown mechanism
+
+Commit a4e7279cd1d1 ("cdc-acm: introduce a cool down") is causing
+regression if there is some USB error, such as -EPROTO.
+
+This has been reported on some samples of the Odroid-N2 using the Combee II
+Zibgee USB dongle.
+
+> struct acm *acm = container_of(work, struct acm, work)
+
+is incorrect in case of a delayed work and causes warnings, usually from
+the workqueue:
+
+> WARNING: CPU: 0 PID: 0 at kernel/workqueue.c:1474 __queue_work+0x480/0x528.
+
+When this happens, USB eventually stops working completely after a while.
+Also the ACM_ERROR_DELAY bit is never set, so the cooldown mechanism
+previously introduced cannot be triggered and acm_submit_read_urb() is
+never called.
+
+This changes makes the cdc-acm driver use a single delayed work, fixing the
+pointer arithmetic in acm_softint() and set the ACM_ERROR_DELAY when the
+cooldown mechanism appear to be needed.
+
+Fixes: a4e7279cd1d1 ("cdc-acm: introduce a cool down")
+Reported-by: Pascal Vizeli <pascal.vizeli@nabucasa.com>
+Cc: Oliver Neukum <oneukum@suse.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ drivers/usb/class/cdc-acm.c | 12 +++++-------
+ drivers/usb/class/cdc-acm.h |  3 +--
+ 2 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
+index d5187b50fc82..76ae5a5d1ac2 100644
+--- a/drivers/usb/class/cdc-acm.c
++++ b/drivers/usb/class/cdc-acm.c
+@@ -509,6 +509,7 @@ static void acm_read_bulk_callback(struct urb *urb)
+ 			"%s - cooling babbling device\n", __func__);
+ 		usb_mark_last_busy(acm->dev);
+ 		set_bit(rb->index, &acm->urbs_in_error_delay);
++		set_bit(ACM_ERROR_DELAY, &acm->flags);
+ 		cooldown = true;
+ 		break;
+ 	default:
+@@ -534,7 +535,7 @@ static void acm_read_bulk_callback(struct urb *urb)
+ 
+ 	if (stopped || stalled || cooldown) {
+ 		if (stalled)
+-			schedule_work(&acm->work);
++			schedule_delayed_work(&acm->dwork, 0);
+ 		else if (cooldown)
+ 			schedule_delayed_work(&acm->dwork, HZ / 2);
+ 		return;
+@@ -564,13 +565,13 @@ static void acm_write_bulk(struct urb *urb)
+ 	acm_write_done(acm, wb);
+ 	spin_unlock_irqrestore(&acm->write_lock, flags);
+ 	set_bit(EVENT_TTY_WAKEUP, &acm->flags);
+-	schedule_work(&acm->work);
++	schedule_delayed_work(&acm->dwork, 0);
+ }
+ 
+ static void acm_softint(struct work_struct *work)
+ {
+ 	int i;
+-	struct acm *acm = container_of(work, struct acm, work);
++	struct acm *acm = container_of(work, struct acm, dwork.work);
+ 
+ 	if (test_bit(EVENT_RX_STALL, &acm->flags)) {
+ 		smp_mb(); /* against acm_suspend() */
+@@ -586,7 +587,7 @@ static void acm_softint(struct work_struct *work)
+ 	if (test_and_clear_bit(ACM_ERROR_DELAY, &acm->flags)) {
+ 		for (i = 0; i < acm->rx_buflimit; i++)
+ 			if (test_and_clear_bit(i, &acm->urbs_in_error_delay))
+-					acm_submit_read_urb(acm, i, GFP_NOIO);
++				acm_submit_read_urb(acm, i, GFP_KERNEL);
+ 	}
+ 
+ 	if (test_and_clear_bit(EVENT_TTY_WAKEUP, &acm->flags))
+@@ -1354,7 +1355,6 @@ static int acm_probe(struct usb_interface *intf,
+ 	acm->ctrlsize = ctrlsize;
+ 	acm->readsize = readsize;
+ 	acm->rx_buflimit = num_rx_buf;
+-	INIT_WORK(&acm->work, acm_softint);
+ 	INIT_DELAYED_WORK(&acm->dwork, acm_softint);
+ 	init_waitqueue_head(&acm->wioctl);
+ 	spin_lock_init(&acm->write_lock);
+@@ -1564,7 +1564,6 @@ static void acm_disconnect(struct usb_interface *intf)
+ 	}
+ 
+ 	acm_kill_urbs(acm);
+-	cancel_work_sync(&acm->work);
+ 	cancel_delayed_work_sync(&acm->dwork);
+ 
+ 	tty_unregister_device(acm_tty_driver, acm->minor);
+@@ -1607,7 +1606,6 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message)
+ 		return 0;
+ 
+ 	acm_kill_urbs(acm);
+-	cancel_work_sync(&acm->work);
+ 	cancel_delayed_work_sync(&acm->dwork);
+ 	acm->urbs_in_error_delay = 0;
+ 
+diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h
+index cd5e9d8ab237..b95ff769072e 100644
+--- a/drivers/usb/class/cdc-acm.h
++++ b/drivers/usb/class/cdc-acm.h
+@@ -112,8 +112,7 @@ struct acm {
+ #		define ACM_ERROR_DELAY	3
+ 	unsigned long urbs_in_error_delay;		/* these need to be restarted after a delay */
+ 	struct usb_cdc_line_coding line;		/* bits, stop, parity */
+-	struct work_struct work;			/* work queue entry for various purposes*/
+-	struct delayed_work dwork;			/* for cool downs needed in error recovery */
++	struct delayed_work dwork;		        /* work queue entry for various purposes */
+ 	unsigned int ctrlin;				/* input control lines (DCD, DSR, RI, break, overruns) */
+ 	unsigned int ctrlout;				/* output control lines (DTR, RTS) */
+ 	struct async_icount iocount;			/* counters for control line changes */
+-- 
+2.29.1
+

buildroot-external/board/hardkernel/patches/linux/0015-arm64-dts-meson-add-RTC-to-ODROID-N2-boards.patch

@@ -0,0 +1,52 @@
+From 9a736bfb2ee71ed09e5f37ec4a506e7bd2a80bf5 Mon Sep 17 00:00:00 2001
+Message-Id: <9a736bfb2ee71ed09e5f37ec4a506e7bd2a80bf5.1606127729.git.stefan@agner.ch>
+In-Reply-To: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1606127729.git.stefan@agner.ch>
+References: <59bbf3567b02c36edfa4ee013d7e7e8c492756f2.1606127729.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Mon, 16 Nov 2020 23:11:02 +0100
+Subject: [PATCH 15/15] arm64: dts: meson: add RTC to ODROID-N2 boards
+
+All ODROID-N2 boards come with a NXP PCF8563TS RTC connected to I2C bus
+3. This is the RTC which is connected to the on-board RTC backup battery.
+Use it as primary RTC.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ .../boot/dts/amlogic/meson-g12b-odroid-n2.dtsi     | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
+index 6982632ae646..40390feba053 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
+@@ -13,6 +13,8 @@ / {
+ 	aliases {
+ 		serial0 = &uart_AO;
+ 		ethernet0 = &ethmac;
++		rtc0 = &board_rtc;
++		rtc1 = &vrtc;
+ 	};
+ 
+ 	dioo2133: audio-amplifier-0 {
+@@ -471,6 +473,18 @@ hdmi_tx_tmds_out: endpoint {
+ 	};
+ };
+ 
++&i2c3 {
++	status = "okay";
++	pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
++	pinctrl-names = "default";
++	clock-frequency = <400000>;
++
++	board_rtc: rtc@51 {
++		compatible = "nxp,pcf8563";
++		reg = <0x51>;
++	};
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+-- 
+2.29.2
+

buildroot-external/board/hardkernel/patches/uboot/0001-Amlogic-w400-read-ethaddr-from-efuse.patch

@@ -37,7 +37,7 @@ index e60dc3a622..d4028c6a39 100644
 +		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
 +					  efuse_mac_addr, EFUSE_MAC_SIZE);
 +		if (len != EFUSE_MAC_SIZE)
-+			return 0; 
++			return 0;
 +
 +		for (int i = 0; i < 6; i++){
 +			buff[0] = efuse_mac_addr[i * 2];

buildroot-external/board/hardkernel/patches/uboot/0002-ARM-meson-isolate-loading-of-socinfo.patch

@@ -0,0 +1,63 @@
+From fb41bcaf0e61e78bc40addb1312040a2bc6a69b7 Mon Sep 17 00:00:00 2001
+Message-Id: <fb41bcaf0e61e78bc40addb1312040a2bc6a69b7.1598875349.git.stefan@agner.ch>
+In-Reply-To: <c12338d22649e46aed12ebe60d897112f045fda9.1598875349.git.stefan@agner.ch>
+References: <c12338d22649e46aed12ebe60d897112f045fda9.1598875349.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Mon, 31 Aug 2020 13:40:18 +0200
+Subject: [PATCH 2/4] ARM: meson: isolate loading of socinfo
+
+Move loading of socinfo into a separate function so the value can be
+reused later.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/mach-meson/board-info.c | 20 ++++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
+index 0d3b40a249..e305d60dca 100644
+--- a/arch/arm/mach-meson/board-info.c
++++ b/arch/arm/mach-meson/board-info.c
+@@ -123,12 +123,16 @@ static void print_board_model(void)
+ 	printf("Model: %s\n", model ? model : "Unknown");
+ }
+ 
+-int show_board_info(void)
++static unsigned int get_socinfo(void)
+ {
+ 	struct regmap *regmap;
+ 	int nodeoffset, ret;
+ 	ofnode node;
+-	unsigned int socinfo;
++	static unsigned int socinfo = 0;
++
++	/* Empty socinfo is invalid, so !socinfo is successfully initialized */
++	if (socinfo)
++		return socinfo;
+ 
+ 	/* find the offset of compatible node */
+ 	nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+@@ -155,8 +159,20 @@ int show_board_info(void)
+ 		return 0;
+ 	}
+ 
++	return socinfo;
++}
++
++int show_board_info(void)
++{
++	unsigned int socinfo;
++
+ 	/* print board information */
+ 	print_board_model();
++
++	socinfo = get_socinfo();
++	if (!socinfo)
++		return 0;
++
+ 	printf("SoC:   Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n",
+ 	       socinfo_to_soc_id(socinfo),
+ 	       socinfo_to_package_id(socinfo),
+-- 
+2.28.0
+

buildroot-external/board/hardkernel/patches/uboot/0003-meson-Add-board_rev-to-env.patch

@@ -0,0 +1,82 @@
+From 15ce807d420324bc209772b843d4004619e0cdaf Mon Sep 17 00:00:00 2001
+Message-Id: <15ce807d420324bc209772b843d4004619e0cdaf.1598875349.git.stefan@agner.ch>
+In-Reply-To: <c12338d22649e46aed12ebe60d897112f045fda9.1598875349.git.stefan@agner.ch>
+References: <c12338d22649e46aed12ebe60d897112f045fda9.1598875349.git.stefan@agner.ch>
+From: Pascal Vizeli <pvizeli@syshack.ch>
+Date: Tue, 4 Aug 2020 13:50:57 +0000
+Subject: [PATCH 3/4] meson: Add board_rev to env
+
+Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/include/asm/arch-meson/boot.h |  4 ++++
+ arch/arm/mach-meson/board-info.c       | 12 ++++++++++++
+ board/amlogic/w400/w400.c              |  5 +++++
+ 3 files changed, 21 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
+index a90fe55081..c67d12d06c 100644
+--- a/arch/arm/include/asm/arch-meson/boot.h
++++ b/arch/arm/include/asm/arch-meson/boot.h
+@@ -7,6 +7,8 @@
+ #ifndef __MESON_BOOT_H__
+ #define __MESON_BOOT_H__
+ 
++#include <linux/types.h>
++
+ /* Boot device */
+ #define BOOT_DEVICE_RESERVED    0
+ #define BOOT_DEVICE_EMMC        1
+@@ -17,4 +19,6 @@
+ 
+ int meson_get_boot_device(void);
+ 
++int meson_get_soc_rev(char *buff, size_t buff_len);
++
+ #endif /* __MESON_BOOT_H__ */
+diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
+index e305d60dca..3c40d6cd27 100644
+--- a/arch/arm/mach-meson/board-info.c
++++ b/arch/arm/mach-meson/board-info.c
+@@ -183,3 +183,15 @@ int show_board_info(void)
+ 
+ 	return 0;
+ }
++
++int meson_get_soc_rev(char *buff, size_t buff_len)
++{
++	unsigned int socinfo;
++
++	socinfo = get_socinfo();
++	if (!socinfo)
++		return -1;
++
++	/* Write SoC info */
++	return snprintf(buff, buff_len, "%x", socinfo_to_minor(socinfo));
++}
+diff --git a/board/amlogic/w400/w400.c b/board/amlogic/w400/w400.c
+index d74aab899a..cb2e5edf5e 100644
+--- a/board/amlogic/w400/w400.c
++++ b/board/amlogic/w400/w400.c
+@@ -10,6 +10,7 @@
+ #include <asm/io.h>
+ #include <asm/arch/sm.h>
+ #include <asm/arch/eth.h>
++#include <asm/arch/boot.h>
+ 
+ #define EFUSE_MAC_OFFSET	20
+ #define EFUSE_MAC_SIZE		12
+@@ -20,6 +21,10 @@ int misc_init_r(void)
+ 	char efuse_mac_addr[EFUSE_MAC_SIZE], buff[3];
+ 	ssize_t len;
+ 
++	if (meson_get_soc_rev(buff, sizeof(buff))) {
++		env_set("board_rev", buff);
++	}
++
+ 	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+ 
+ 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+-- 
+2.28.0
+

buildroot-external/board/intel/nuc/kernel.config

@@ -15,3 +15,13 @@ CONFIG_DRM_I915=m
 CONFIG_DRM_I915_CAPTURE_ERROR=y
 CONFIG_DRM_I915_COMPRESS_ERROR=y
 CONFIG_DRM_I915_USERPTR=y
+
+CONFIG_SND_HDA=y
+CONFIG_SND_HDA_CORE=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_I915=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_CODEC_HDMI=m

buildroot-external/board/intel/ova/home-assistant.ovf

@@ -13,8 +13,9 @@
       <Description>Logical network used by this appliance.</Description>
     </Network>
   </NetworkSection>
-  <VirtualSystem ovf:id="Home Assistant">
+  <VirtualSystem ovf:id="HomeAssistant">
     <Info>A virtual machine</Info>
+    <Name>Home Assistant</Name>
     <ProductSection>
       <Info>Meta-information about the installed software</Info>
       <Product>Operating-System</Product>

buildroot-external/board/raspberrypi/hassos-hook.sh

@@ -13,14 +13,13 @@ function hassos_pre_image() {
 
     # Firmware
     if [[ "${BOARD_ID}" =~ "rpi4" ]]; then
-        cp -t "${BOOT_DATA}" \
-        "${BINARIES_DIR}/rpi-firmware/fixup4.dat" \
-        "${BINARIES_DIR}/rpi-firmware/start4.elf"
+        cp "${BINARIES_DIR}/rpi-firmware/fixup.dat" "${BOOT_DATA}/fixup4.dat" 
+        cp "${BINARIES_DIR}/rpi-firmware/start.elf" "${BOOT_DATA}/start4.elf" 
     else
         cp -t "${BOOT_DATA}" \
-        "${BINARIES_DIR}/rpi-firmware/fixup.dat" \
-        "${BINARIES_DIR}/rpi-firmware/start.elf" \
-        "${BINARIES_DIR}/rpi-firmware/bootcode.bin"
+            "${BINARIES_DIR}/rpi-firmware/fixup.dat" \
+            "${BINARIES_DIR}/rpi-firmware/start.elf" \
+            "${BINARIES_DIR}/rpi-firmware/bootcode.bin"
     fi
 
     # Set cmd options

buildroot-external/board/raspberrypi/patches/linux/0001-brcmfmac-add-FT-based-AKMs-in-brcmf_set_key_mgmt-for.patch

@@ -0,0 +1,50 @@
+From d6fc5f89ac905cb3efc9c61ce79dbfad5d91883b Mon Sep 17 00:00:00 2001
+Message-Id: <d6fc5f89ac905cb3efc9c61ce79dbfad5d91883b.1604607313.git.stefan@agner.ch>
+From: Chung-Hsien Hsu <stanley.hsu@cypress.com>
+Date: Wed, 15 Aug 2018 05:32:39 -0500
+Subject: [PATCH 1/3] brcmfmac: add FT-based AKMs in brcmf_set_key_mgmt() for
+ FT support
+
+Add WLAN_AKM_SUITE_FT_8021X and WLAN_AKM_SUITE_FT_PSK in
+brcmf_set_key_mgmt() for FT support.
+
+Signed-off-by: Chung-Hsien Hsu <stanley.hsu@cypress.com>
+Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
+Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
+---
+ drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c | 6 ++++++
+ .../net/wireless/broadcom/brcm80211/include/brcmu_wifi.h    | 1 +
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
+index 71b7e5c19434..c312626c0a27 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
+@@ -1649,6 +1649,12 @@ brcmf_set_key_mgmt(struct net_device *ndev, struct cfg80211_connect_params *sme)
+ 		case WLAN_AKM_SUITE_PSK:
+ 			val = WPA2_AUTH_PSK;
+ 			break;
++		case WLAN_AKM_SUITE_FT_8021X:
++			val = WPA2_AUTH_UNSPECIFIED | WPA2_AUTH_FT;
++			break;
++		case WLAN_AKM_SUITE_FT_PSK:
++			val = WPA2_AUTH_PSK | WPA2_AUTH_FT;
++			break;
+ 		default:
+ 			brcmf_err("invalid cipher group (%d)\n",
+ 				  sme->crypto.cipher_group);
+diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h b/drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h
+index 75b2a0438cfa..dddebaa60352 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h
++++ b/drivers/net/wireless/broadcom/brcm80211/include/brcmu_wifi.h
+@@ -239,6 +239,7 @@ static inline bool ac_bitmap_tst(u8 bitmap, int prec)
+ #define WPA2_AUTH_RESERVED4	0x0400
+ #define WPA2_AUTH_RESERVED5	0x0800
+ #define WPA2_AUTH_1X_SHA256	0x1000  /* 1X with SHA256 key derivation */
++#define WPA2_AUTH_FT		0x4000	/* Fast BSS Transition */
+ #define WPA2_AUTH_PSK_SHA256	0x8000	/* PSK with SHA256 key derivation */
+ 
+ #define DOT11_DEFAULT_RTS_LEN		2347
+-- 
+2.29.1
+

buildroot-external/board/raspberrypi/patches/linux/0001-dt-bindings-reset-Add-a-binding-for-the-RPi-Firmware.patch

@@ -1,41 +0,0 @@
-From a9f92163e6c07e5c6f57f00f4931098e0e1ee826 Mon Sep 17 00:00:00 2001
-Message-Id: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:18:37 +0200
-Subject: [PATCH 1/4] dt-bindings: reset: Add a binding for the RPi Firmware
- reset controller
-
-The firmware running on the RPi VideoCore can be used to reset and
-initialize HW controlled by the firmware.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-[backport for RPi 4.19 kernel]
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- .../dt-bindings/reset/raspberrypi,firmware-reset.h  | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
- create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
-
-diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-new file mode 100644
-index 000000000000..1a4f4c792723
---- /dev/null
-+++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (c) 2020 Nicolas Saenz Julienne
-+ * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+
-+#define RASPBERRYPI_FIRMWARE_RESET_ID_USB	0
-+#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS	1
-+
-+#endif
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/linux/0002-ARM-dts-bcm2711-Add-firmware-usb-reset-node.patch

@@ -1,38 +0,0 @@
-From b15414057bc9a023fc865242f499807d82933e58 Mon Sep 17 00:00:00 2001
-Message-Id: <b15414057bc9a023fc865242f499807d82933e58.1595152741.git.stefan@agner.ch>
-In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:18:39 +0200
-Subject: [PATCH 2/4] ARM: dts: bcm2711: Add firmware usb reset node
-
-Now that the reset driver exposing Raspberry Pi 4's firmware based USB
-reset routine is available, let's add the device tree node exposing it.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-[backport for RPi 4.19 kernel]
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-index 42259dbf3919..ec0b3bb64de8 100644
---- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-@@ -80,6 +80,11 @@
- 				  "";
- 		status = "okay";
- 	};
-+
-+	reset: reset {
-+		compatible = "raspberrypi,firmware-reset";
-+		#reset-cells = <1>;
-+	};
- };
- 
- &uart0 {
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/linux/0002-CDC-ACM-heed-quirk-also-in-error-handling.patch

@@ -0,0 +1,39 @@
+From 1eaf50e14dfdda654e6acb2a1ee4c18cff346064 Mon Sep 17 00:00:00 2001
+Message-Id: <1eaf50e14dfdda654e6acb2a1ee4c18cff346064.1604607313.git.stefan@agner.ch>
+In-Reply-To: <d6fc5f89ac905cb3efc9c61ce79dbfad5d91883b.1604607313.git.stefan@agner.ch>
+References: <d6fc5f89ac905cb3efc9c61ce79dbfad5d91883b.1604607313.git.stefan@agner.ch>
+From: Oliver Neukum <oneukum@suse.com>
+Date: Tue, 26 May 2020 14:44:20 +0200
+Subject: [PATCH 2/3] CDC-ACM: heed quirk also in error handling
+
+commit 97fe809934dd2b0b37dfef3a2fc70417f485d7af upstream.
+
+If buffers are iterated over in the error case, the lower limits
+for quirky devices must be heeded.
+
+Signed-off-by: Oliver Neukum <oneukum@suse.com>
+Reported-by: Jean Rene Dawin <jdawin@math.uni-bielefeld.de>
+Fixes: a4e7279cd1d19 ("cdc-acm: introduce a cool down")
+Cc: stable <stable@vger.kernel.org>
+Link: https://lore.kernel.org/r/20200526124420.22160-1-oneukum@suse.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/class/cdc-acm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
+index 10ba1b4f0dbf..e8b9b27937ed 100644
+--- a/drivers/usb/class/cdc-acm.c
++++ b/drivers/usb/class/cdc-acm.c
+@@ -590,7 +590,7 @@ static void acm_softint(struct work_struct *work)
+ 	}
+ 
+ 	if (test_and_clear_bit(ACM_ERROR_DELAY, &acm->flags)) {
+-		for (i = 0; i < ACM_NR; i++)
++		for (i = 0; i < acm->rx_buflimit; i++)
+ 			if (test_and_clear_bit(i, &acm->urbs_in_error_delay))
+ 					acm_submit_read_urb(acm, i, GFP_NOIO);
+ 	}
+-- 
+2.29.1
+

buildroot-external/board/raspberrypi/patches/linux/0003-ARM-dts-bcm2711-Add-reset-controller-to-xHCI-node.patch

@@ -1,58 +0,0 @@
-From 08558575c0f3d1437994590ad418d6c2cf18d96b Mon Sep 17 00:00:00 2001
-Message-Id: <08558575c0f3d1437994590ad418d6c2cf18d96b.1595152741.git.stefan@agner.ch>
-In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:18:40 +0200
-Subject: [PATCH 3/4] ARM: dts: bcm2711: Add reset controller to xHCI node
-
-The chip is hardwired to the board's PCIe bus and needs to be properly
-setup trough a firmware routine after a PCI fundamental reset. Pass the
-reset controller phandle that takes care of triggering the
-initialization to the relevant PCI device.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-[backport for RPi 4.19 kernel]
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-index ec0b3bb64de8..2c6aa1933600 100644
---- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-@@ -4,6 +4,8 @@
- #include "bcm2711-rpi.dtsi"
- #include "bcm283x-rpi-csi1-2lane.dtsi"
- 
-+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-+
- / {
- 	compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
- 	model = "Raspberry Pi 4 Model B";
-@@ -87,6 +89,21 @@
- 	};
- };
- 
-+&pcie_0 {
-+	pci@1,0 {
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		reg = <0 0 0 0 0>;
-+
-+		usb@1,0 {
-+			reg = <0x10000 0 0 0 0>;
-+			resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
-+		};
-+	};
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_pins &bt_pins>;
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/linux/0003-usb-cdc-acm-fix-cooldown-mechanism.patch

@@ -0,0 +1,130 @@
+From 930c59eeae2bdd02fa1327a69e4df70105f672e4 Mon Sep 17 00:00:00 2001
+Message-Id: <930c59eeae2bdd02fa1327a69e4df70105f672e4.1604607313.git.stefan@agner.ch>
+In-Reply-To: <d6fc5f89ac905cb3efc9c61ce79dbfad5d91883b.1604607313.git.stefan@agner.ch>
+References: <d6fc5f89ac905cb3efc9c61ce79dbfad5d91883b.1604607313.git.stefan@agner.ch>
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 19 Oct 2020 19:07:02 +0200
+Subject: [PATCH 3/3] usb: cdc-acm: fix cooldown mechanism
+
+Commit a4e7279cd1d1 ("cdc-acm: introduce a cool down") is causing
+regression if there is some USB error, such as -EPROTO.
+
+This has been reported on some samples of the Odroid-N2 using the Combee II
+Zibgee USB dongle.
+
+> struct acm *acm = container_of(work, struct acm, work)
+
+is incorrect in case of a delayed work and causes warnings, usually from
+the workqueue:
+
+> WARNING: CPU: 0 PID: 0 at kernel/workqueue.c:1474 __queue_work+0x480/0x528.
+
+When this happens, USB eventually stops working completely after a while.
+Also the ACM_ERROR_DELAY bit is never set, so the cooldown mechanism
+previously introduced cannot be triggered and acm_submit_read_urb() is
+never called.
+
+This changes makes the cdc-acm driver use a single delayed work, fixing the
+pointer arithmetic in acm_softint() and set the ACM_ERROR_DELAY when the
+cooldown mechanism appear to be needed.
+
+Fixes: a4e7279cd1d1 ("cdc-acm: introduce a cool down")
+Cc: Oliver Neukum <oneukum@suse.com>
+Reported-by: Pascal Vizeli <pascal.vizeli@nabucasa.com>
+Acked-by: Oliver Neukum <oneukum@suse.com>
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Link: https://lore.kernel.org/r/20201019170702.150534-1-jbrunet@baylibre.com
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/class/cdc-acm.c | 12 +++++-------
+ drivers/usb/class/cdc-acm.h |  3 +--
+ 2 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
+index e8b9b27937ed..4b543aa0030d 100644
+--- a/drivers/usb/class/cdc-acm.c
++++ b/drivers/usb/class/cdc-acm.c
+@@ -510,6 +510,7 @@ static void acm_read_bulk_callback(struct urb *urb)
+ 			"%s - cooling babbling device\n", __func__);
+ 		usb_mark_last_busy(acm->dev);
+ 		set_bit(rb->index, &acm->urbs_in_error_delay);
++		set_bit(ACM_ERROR_DELAY, &acm->flags);
+ 		cooldown = true;
+ 		break;
+ 	default:
+@@ -535,7 +536,7 @@ static void acm_read_bulk_callback(struct urb *urb)
+ 
+ 	if (stopped || stalled || cooldown) {
+ 		if (stalled)
+-			schedule_work(&acm->work);
++			schedule_delayed_work(&acm->dwork, 0);
+ 		else if (cooldown)
+ 			schedule_delayed_work(&acm->dwork, HZ / 2);
+ 		return;
+@@ -570,13 +571,13 @@ static void acm_write_bulk(struct urb *urb)
+ 	acm_write_done(acm, wb);
+ 	spin_unlock_irqrestore(&acm->write_lock, flags);
+ 	set_bit(EVENT_TTY_WAKEUP, &acm->flags);
+-	schedule_work(&acm->work);
++	schedule_delayed_work(&acm->dwork, 0);
+ }
+ 
+ static void acm_softint(struct work_struct *work)
+ {
+ 	int i;
+-	struct acm *acm = container_of(work, struct acm, work);
++	struct acm *acm = container_of(work, struct acm, dwork.work);
+ 
+ 	if (test_bit(EVENT_RX_STALL, &acm->flags)) {
+ 		smp_mb(); /* against acm_suspend() */
+@@ -592,7 +593,7 @@ static void acm_softint(struct work_struct *work)
+ 	if (test_and_clear_bit(ACM_ERROR_DELAY, &acm->flags)) {
+ 		for (i = 0; i < acm->rx_buflimit; i++)
+ 			if (test_and_clear_bit(i, &acm->urbs_in_error_delay))
+-					acm_submit_read_urb(acm, i, GFP_NOIO);
++				acm_submit_read_urb(acm, i, GFP_KERNEL);
+ 	}
+ 
+ 	if (test_and_clear_bit(EVENT_TTY_WAKEUP, &acm->flags))
+@@ -1386,7 +1387,6 @@ static int acm_probe(struct usb_interface *intf,
+ 	acm->ctrlsize = ctrlsize;
+ 	acm->readsize = readsize;
+ 	acm->rx_buflimit = num_rx_buf;
+-	INIT_WORK(&acm->work, acm_softint);
+ 	INIT_DELAYED_WORK(&acm->dwork, acm_softint);
+ 	init_waitqueue_head(&acm->wioctl);
+ 	spin_lock_init(&acm->write_lock);
+@@ -1596,7 +1596,6 @@ static void acm_disconnect(struct usb_interface *intf)
+ 	}
+ 
+ 	acm_kill_urbs(acm);
+-	cancel_work_sync(&acm->work);
+ 	cancel_delayed_work_sync(&acm->dwork);
+ 
+ 	tty_unregister_device(acm_tty_driver, acm->minor);
+@@ -1639,7 +1638,6 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message)
+ 		return 0;
+ 
+ 	acm_kill_urbs(acm);
+-	cancel_work_sync(&acm->work);
+ 	cancel_delayed_work_sync(&acm->dwork);
+ 	acm->urbs_in_error_delay = 0;
+ 
+diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h
+index 30380d28a504..d8f8651425c4 100644
+--- a/drivers/usb/class/cdc-acm.h
++++ b/drivers/usb/class/cdc-acm.h
+@@ -111,8 +111,7 @@ struct acm {
+ #		define ACM_ERROR_DELAY	3
+ 	unsigned long urbs_in_error_delay;		/* these need to be restarted after a delay */
+ 	struct usb_cdc_line_coding line;		/* bits, stop, parity */
+-	struct work_struct work;			/* work queue entry for various purposes*/
+-	struct delayed_work dwork;			/* for cool downs needed in error recovery */
++	struct delayed_work dwork;		        /* work queue entry for various purposes */
+ 	unsigned int ctrlin;				/* input control lines (DCD, DSR, RI, break, overruns) */
+ 	unsigned int ctrlout;				/* output control lines (DTR, RTS) */
+ 	struct async_icount iocount;			/* counters for control line changes */
+-- 
+2.29.1
+

buildroot-external/board/raspberrypi/patches/linux/0004-ARM-dts-bcm2838-add-upstream-property-to-enable-PCIe.patch

@@ -1,44 +0,0 @@
-From dcfb930f9c271ad303a888ce94227d2d78974e39 Mon Sep 17 00:00:00 2001
-Message-Id: <dcfb930f9c271ad303a888ce94227d2d78974e39.1595152741.git.stefan@agner.ch>
-In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Stefan Agner <stefan@agner.ch>
-Date: Sun, 19 Jul 2020 11:49:45 +0200
-Subject: [PATCH 4/4] ARM: dts: bcm2838: add upstream property to enable PCIe
- spread-spectrum
-
-Add the upstream device tree property brcm,enable-ssc to enable
-spread-spectrum for PCIe. This is used by the upstream U-Boot.
-
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- arch/arm/boot/dts/bcm2838.dtsi | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi
-index 36d250d7053b..d6cc876bc720 100644
---- a/arch/arm/boot/dts/bcm2838.dtsi
-+++ b/arch/arm/boot/dts/bcm2838.dtsi
-@@ -353,11 +353,14 @@
- 			 */
- 			ranges = <0x02000000 0x0 0xf8000000  0x6 0x00000000
- 				  0x0 0x04000000>;
--			/* Map inbound accesses from pci:0x0_00000000..ffffffff
--			 * to scb:0x0_00000000-ffffffff
--			 */
--			dma-ranges = <0x02000000 0x0 0x00000000  0x0 0x00000000
--				      0x1 0x00000000>;
-+                        /*
-+                         * The wrapper around the PCIe block has a bug
-+                         * preventing it from accessing beyond the first 3GB of
-+                         * memory.
-+                         */
-+                        dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
-+                                      0x0 0xc0000000>;
-+			brcm,enable-ssc;
- 			status = "okay";
- 		};
- 
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/uboot/0002-avoid-block-uart-write.patch

@@ -1,49 +0,0 @@
-From 5e960cc9b208c53d5385d5a2f6c7f380e9499d4c Mon Sep 17 00:00:00 2001
-From: Alexandru Costache <alexandru@balena.io>
-Date: Wed, 18 Mar 2020 16:54:28 +0100
-Subject: [PATCH] Add a retry limit when writing to uart console
-
-Seems that if the serial console is incorrectly
-configured in the dtb, writing to it may block indefinitely,
-thus preventing the board from booting.
-
-Let's add a retry count to unblock in such cases.
-
-Upstream-status: Inappropriate [configuration]
-Signed-off-by: Alexandru Costache <alexandru@balena.io>
----
- drivers/serial/serial_bcm283x_mu.c | 12 +++++++++---
- 1 file changed, 9 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
-index bd1d89ec83..bd033d14c4 100644
---- a/drivers/serial/serial_bcm283x_mu.c
-+++ b/drivers/serial/serial_bcm283x_mu.c
-@@ -49,7 +49,7 @@ struct bcm283x_mu_regs {
- struct bcm283x_mu_priv {
- 	struct bcm283x_mu_regs *regs;
- };
--
-+static uint16_t putc_retry = 0;
- static int bcm283x_mu_serial_getc(struct udevice *dev);
- 
- static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
-@@ -105,8 +105,14 @@ static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
- 	struct bcm283x_mu_regs *regs = priv->regs;
- 
- 	/* Wait until there is space in the FIFO */
--	if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY))
--		return -EAGAIN;
-+	if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY)) {
-+		if (++putc_retry) {
-+			return -EAGAIN;
-+		} else {
-+			/* Couldn't write for too long, drop char */
-+			return 0;
-+		}
-+	}
- 
- 	/* Send the character */
- 	writel(data, &regs->io);
--- 
-2.17.1

buildroot-external/board/raspberrypi/rootfs-overlay/usr/lib/udev/rules.d/99-com.rules

@@ -1,4 +1,5 @@
-KERNEL=="ttyAMA[01]", PROGRAM="/bin/sh -c '\
+
+KERNEL=="ttyAMA0", PROGRAM="/bin/sh -c '\
 	ALIASES=/proc/device-tree/aliases; \
 	if cmp -s $ALIASES/uart0 $ALIASES/serial0; then \
 		echo 0;\
@@ -9,6 +10,19 @@ KERNEL=="ttyAMA[01]", PROGRAM="/bin/sh -c '\
 	fi\
 '", SYMLINK+="serial%c"
 
+KERNEL=="ttyAMA1", PROGRAM="/bin/sh -c '\
+	ALIASES=/proc/device-tree/aliases; \
+	if [ -e /dev/ttyAMA0 ]; then \
+		exit 1; \
+	elif cmp -s $ALIASES/uart0 $ALIASES/serial0; then \
+		echo 0;\
+	elif cmp -s $ALIASES/uart0 $ALIASES/serial1; then \
+		echo 1; \
+	else \
+		exit 1; \
+	fi\
+'", SYMLINK+="serial%c"
+
 KERNEL=="ttyS0", PROGRAM="/bin/sh -c '\
 	ALIASES=/proc/device-tree/aliases; \
 	if cmp -s $ALIASES/uart1 $ALIASES/serial0; then \

buildroot-external/board/raspberrypi/uboot-boot.ush

@@ -37,16 +37,18 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
   elif test "x${BOOT_SLOT}" = "xA"; then
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
-      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load ${devtype} ${devnum}:2 ${kernel_addr_r} zImage"
-      setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_a} rauc.slot=A"
+      echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load ${devtype} ${devnum}:2 ${kernel_addr_r} zImage; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_a} rauc.slot=A"
+      fi
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
-      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load ${devtype} ${devnum}:4 ${kernel_addr_r} zImage"
-      setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_b} rauc.slot=B"
+      echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load ${devtype} ${devnum}:4 ${kernel_addr_r} zImage"; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_b} rauc.slot=B"
+      fi
     fi
   fi
 done
@@ -62,10 +64,8 @@ else
   reset
 fi
 
-echo "Loading kernel"
-run load_kernel
-echo " Starting kernel"
+echo "Starting kernel"
 bootz ${kernel_addr_r} - ${fdt_org}
 
-echo "Fails on boot"
+echo "Boot failed, resetting..."
 reset

buildroot-external/board/raspberrypi/uboot-boot64.ush

@@ -37,16 +37,18 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
   elif test "x${BOOT_SLOT}" = "xA"; then
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
-      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load ${devtype} ${devnum}:2 ${kernel_addr_r} Image"
-      setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_a} rauc.slot=A"
+      echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load ${devtype} ${devnum}:2 ${kernel_addr_r} Image; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_a} rauc.slot=A"
+      fi
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
-      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load ${devtype} ${devnum}:4 ${kernel_addr_r} Image"
-      setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_b} rauc.slot=B"
+      echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..."
+      if ext4load ${devtype} ${devnum}:4 ${kernel_addr_r} Image"; then
+          setenv bootargs "${bootargs_hassos} ${bootargs_rpi} ${bootargs_b} rauc.slot=B"
+      fi
     fi
   fi
 done
@@ -62,10 +64,8 @@ else
   reset
 fi
 
-echo "Loading kernel"
-run load_kernel
-echo " Starting kernel"
+echo "Starting kernel"
 booti ${kernel_addr_r} - ${fdt_org}
 
-echo "Fails on boot"
+echo "Boot failed, resetting..."
 reset

buildroot-external/configs/intel_nuc_defconfig

@@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.53"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.80"
 BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -103,5 +103,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="amd64"
+BR2_PACKAGE_HASSIO_MACHINE="intel-nuc"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_INTEL_E1000E=y

buildroot-external/configs/odroid_c2_defconfig

@@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.10"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.19"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
@@ -96,6 +96,7 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="aarch64"
+BR2_PACKAGE_HASSIO_MACHINE="odroid-c2"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_HARDKERNEL_BOOT=y
 BR2_PACKAGE_HARDKERNEL_BOOT_ODROID_C2=y

buildroot-external/configs/odroid_n2_defconfig

@@ -22,13 +22,13 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.10"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.19"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
-BR2_LINUX_KERNEL_INTREE_DTS_NAME="amlogic/meson-g12b-odroid-n2"
+BR2_LINUX_KERNEL_INTREE_DTS_NAME="amlogic/meson-g12b-odroid-n2 amlogic/meson-g12b-odroid-n2-plus"
 BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
 BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y
 BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_HASSOS_PATH)/busybox.config"
@@ -96,6 +96,7 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="aarch64"
+BR2_PACKAGE_HASSIO_MACHINE="odroid-n2"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_HARDKERNEL_BOOT=y
 BR2_PACKAGE_HARDKERNEL_BOOT_ODROID_N2=y

buildroot-external/configs/odroid_xu4_defconfig

@@ -23,7 +23,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.10"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.19"
 BR2_LINUX_KERNEL_DEFCONFIG="exynos"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -100,6 +100,7 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armv7"
+BR2_PACKAGE_HASSIO_MACHINE="odroid-xu"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_HARDKERNEL_BOOT=y
 BR2_PACKAGE_HARDKERNEL_BOOT_ODROID_XU4=y

buildroot-external/configs/ova_defconfig

@@ -23,7 +23,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.53"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.80"
 BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -94,4 +94,5 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="amd64"
+BR2_PACKAGE_HASSIO_MACHINE="qemux86-64"
 BR2_PACKAGE_APPARMOR=y

buildroot-external/configs/rpi0_w_defconfig

@@ -99,5 +99,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armhf"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_BLUETOOTH_BCM43XX=y

buildroot-external/configs/rpi2_defconfig

@@ -98,4 +98,5 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armv7"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi2"
 BR2_PACKAGE_APPARMOR=y

buildroot-external/configs/rpi3_64_defconfig

@@ -99,5 +99,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="aarch64"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi3-64"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_BLUETOOTH_BCM43XX=y

buildroot-external/configs/rpi3_defconfig

@@ -99,5 +99,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armv7"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi3"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_BLUETOOTH_BCM43XX=y

buildroot-external/configs/rpi4_64_defconfig

@@ -87,7 +87,7 @@ BR2_TARGET_ROOTFS_SQUASHFS4_LZ4=y
 BR2_TARGET_UBOOT=y
 BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
 BR2_TARGET_UBOOT_CUSTOM_VERSION=y
-BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.07"
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.01"
 BR2_TARGET_UBOOT_BOARD_DEFCONFIG="rpi_4"
 BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/bootloader/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/uboot.config"
 BR2_TARGET_UBOOT_BOOT_SCRIPT=y
@@ -100,5 +100,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="aarch64"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi4-64"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_BLUETOOTH_BCM43XX=y

buildroot-external/configs/rpi4_defconfig

@@ -100,5 +100,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armv7"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi4"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_BLUETOOTH_BCM43XX=y

buildroot-external/configs/rpi_defconfig

@@ -98,4 +98,5 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armhf"
+BR2_PACKAGE_HASSIO_MACHINE="raspberrypi"
 BR2_PACKAGE_APPARMOR=y

buildroot-external/configs/tinker_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker $(BR2_EXTERNAL_HASSOS_PATH)/board/asus/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.53"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.80"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/kernel.config"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
@@ -105,5 +105,6 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="armv7"
+BR2_PACKAGE_HASSIO_MACHINE="tinker"
 BR2_PACKAGE_APPARMOR=y
 BR2_PACKAGE_BLUETOOTH_RTL8723=y

buildroot-external/kernel/device-support.config

@@ -13,6 +13,7 @@ CONFIG_USB_ACM=m
 CONFIG_USB_USBNET=m
 
 CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_SND_USB_AUDIO=m
 
 CONFIG_BT=y
 CONFIG_BT_BREDR=y
@@ -24,6 +25,9 @@ CONFIG_BT_HCIBTUSB=y
 CONFIG_BT_HCIBTUSB_BCM=m
 CONFIG_BT_HCIBTUSB_RTL=m
 
+CONFIG_RTL_CARDS=y
+CONFIG_RTL8192CU=m
+
 # Multimedia core support
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CONTROLLER=y
@@ -140,15 +144,3 @@ CONFIG_VIDEO_EM28XX_V4L2=m
 CONFIG_VIDEO_EM28XX_ALSA=m
 CONFIG_VIDEO_EM28XX_DVB=m
 CONFIG_VIDEO_EM28XX_RC=m
-
-# Audio devices (USB/PCI)
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_HDA=y
-CONFIG_SND_HDA_CORE=y
-CONFIG_SND_HDA_GENERIC=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_I915=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m

buildroot-external/meta

@@ -1,7 +1,7 @@
-VERSION_MAJOR=5
-VERSION_BUILD=0
+VERSION_MAJOR=4
+VERSION_BUILD=18
 
 HASSOS_NAME="HassOS"
 HASSOS_ID="hassos"
 
-DEPLOYMENT="development"
+DEPLOYMENT="production"

buildroot-external/ota/rauc-hook

@@ -2,29 +2,46 @@
 
 ##
 # Hooks
+env
 
 # Handle boot hocks
 if [ "${RAUC_SLOT_CLASS}" = "boot" ]; then
-    BOOT_DATA=/tmp/boot-data
+    BOOT_TMP=/tmp/boot-tmp
+    BOOT_NEW=/tmp/boot-new
+    BOOT_MNT=/mnt/boot
 
-    mkdir -p ${BOOT_DATA}
-    if [ "${1}" = "slot-pre-install" ]; then
-        cp -f ${RAUC_SLOT_MOUNT_POINT}/*.txt ${BOOT_DATA}/
-    elif [ "${1}" = "slot-post-install" ]; then
-        cp -f ${BOOT_DATA}/*.txt ${RAUC_SLOT_MOUNT_POINT}/
+    mkdir -p "${BOOT_TMP}"
+    mkdir -p "${BOOT_NEW}"
+
+    # Mount boot
+    if ! systemctl -q is-active mnt-boot.mount; then
+        systemctl start mnt-boot.mount
     fi
+    mount "${RAUC_IMAGE_NAME}" "${BOOT_NEW}"
+
+    # Backup boot config
+    cp -f "${BOOT_MNT}"/*.txt "${BOOT_TMP}/"
+
+    # Update
+    cp -rf "${BOOT_NEW}"/* "${BOOT_MNT}/"
+
+    # Restore boot config
+    cp -f "${BOOT_TMP}"/*.txt "${BOOT_MNT}/"
+
+    umount "${BOOT_NEW}"
+    rm -rf "${BOOT_TMP}" "${BOOT_NEW}"
 fi
 
 # Handle spl install
 if [ "${RAUC_SLOT_CLASS}" = "spl" ]; then
     DEVICE_CHILD="$(findfs LABEL="hassos-boot")"
-    DEVICE_ROOT="/dev/$(lsblk -no pkname ${DEVICE_CHILD})"
+    DEVICE_ROOT="/dev/$(lsblk -no pkname "${DEVICE_CHILD}")"
 
-    if sfdisk -dq ${DEVICE_ROOT} | grep -q 'label: gpt'; then
-        dd if=${RAUC_IMAGE_NAME} of=${DEVICE_ROOT} conv=notrunc bs=512 seek=2 skip=2
+    if sfdisk -dq "${DEVICE_ROOT}" | grep -q 'label: gpt'; then
+        dd if="${RAUC_IMAGE_NAME}" of="${DEVICE_ROOT}" conv=notrunc bs=512 seek=2 skip=2
     else
-        dd if=${RAUC_IMAGE_NAME} of=${DEVICE_ROOT} conv=notrunc bs=1 count=440
-        dd if=${RAUC_IMAGE_NAME} of=${DEVICE_ROOT} conv=notrunc bs=512 seek=1 skip=1
+        dd if="${RAUC_IMAGE_NAME}" of="${DEVICE_ROOT}" conv=notrunc bs=1 count=440
+        dd if="${RAUC_IMAGE_NAME}" of="${DEVICE_ROOT}" conv=notrunc bs=512 seek=1 skip=1
     fi
 fi
 

buildroot-external/package/bluetooth-bcm43xx/bluetooth-bcm43xx.mk

@@ -11,8 +11,8 @@ BLUETOOTH_BCM43XX_SITE = $(BR2_EXTERNAL_HASSOS_PATH)/package/bluetooth-bcm43xx
 BLUETOOTH_BCM43XX_SITE_METHOD = local
 
 define BLUETOOTH_BCM43XX_BUILD_CMDS
-	curl -L -o $(@D)/BCM43430A1.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/fff76cb15527c435ce99a9787848eacd6288282c/broadcom/BCM43430A1.hcd
-	curl -L -o $(@D)/BCM4345C0.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/fff76cb15527c435ce99a9787848eacd6288282c/broadcom/BCM4345C0.hcd
+	curl -L -o $(@D)/BCM43430A1.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/a4e08822e3f24a6211f6ac94bc98b7ef87700c70/broadcom/BCM43430A1.hcd
+	curl -L -o $(@D)/BCM4345C0.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/a4e08822e3f24a6211f6ac94bc98b7ef87700c70/broadcom/BCM4345C0.hcd
 	curl -L -o $(@D)/btuart https://raw.githubusercontent.com/RPi-Distro/pi-bluetooth/cbdbcb66bcc5b9af05f1a9fffe2254c872bb0ace/usr/bin/btuart
 	curl -L -o $(@D)/bthelper https://raw.githubusercontent.com/RPi-Distro/pi-bluetooth/cbdbcb66bcc5b9af05f1a9fffe2254c872bb0ace/usr/bin/bthelper
 	curl -L -o $(@D)/90-pi-bluetooth.rules https://raw.githubusercontent.com/RPi-Distro/pi-bluetooth/cbdbcb66bcc5b9af05f1a9fffe2254c872bb0ace/lib/udev/rules.d/90-pi-bluetooth.rules

buildroot-external/package/hardkernel-boot/hardkernel-boot.mk

@@ -42,13 +42,13 @@ define HARDKERNEL_BOOT_BUILD_CMDS
 endef
 
 else ifeq ($(BR2_PACKAGE_HARDKERNEL_BOOT_ODROID_N2),y)
-HARDKERNEL_BOOT_VERSION = c989da31a5c1da3ab57d7c6dc5a3fdbcc1c3eed7
+HARDKERNEL_BOOT_VERSION = ca5bdd0f1c291d1ec135cd134e01aa2619203d4c
 
 HARDKERNEL_BOOT_BINS += u-boot.g12b
 define HARDKERNEL_BOOT_BUILD_CMDS
-	curl -L -o $(@D)/fip/blx_fix.sh https://raw.githubusercontent.com/home-assistant/hassos-blobs/d88ec078470f236d694ba1f9e69a44759ddf41ea/odroid-n2/blx_fix_g12a.sh
-	curl -L -o $(@D)/fip/acs.bin https://raw.githubusercontent.com/home-assistant/hassos-blobs/d88ec078470f236d694ba1f9e69a44759ddf41ea/odroid-n2/acs.bin
-	curl -L -o $(@D)/fip/bl301.bin https://raw.githubusercontent.com/home-assistant/hassos-blobs/d88ec078470f236d694ba1f9e69a44759ddf41ea/odroid-n2/bl301.bin
+	curl -L -o $(@D)/fip/blx_fix.sh https://raw.githubusercontent.com/home-assistant/operating-system-blobs/f17a8e81e0b7e1bd2475441465cc737c0891edfa/hardkernel/blx_fix_g12a.sh
+	curl -L -o $(@D)/fip/acs.bin https://raw.githubusercontent.com/home-assistant/operating-system-blobs/f17a8e81e0b7e1bd2475441465cc737c0891edfa/hardkernel/odroid-n2/acs.bin
+	curl -L -o $(@D)/fip/bl301.bin https://raw.githubusercontent.com/home-assistant/operating-system-blobs/f17a8e81e0b7e1bd2475441465cc737c0891edfa/hardkernel/odroid-n2/bl301.bin
 
 	bash $(@D)/fip/blx_fix.sh \
 		$(@D)/fip/g12b/bl30.bin $(@D)/fip/zero_tmp $(@D)/fip/bl30_zero.bin \

buildroot-external/package/hassio/Config.in

@@ -13,4 +13,9 @@ config BR2_PACKAGE_HASSIO_ARCH
 	help
 	  Supervisor architecture which should be pull.
 
+config BR2_PACKAGE_HASSIO_MACHINE
+	string "Supervisor Machine"
+	help
+	  Machine to pull containers for (used for landing page).
+
 endif

buildroot-external/package/hassio/builder/hostapp.sh

@@ -2,6 +2,7 @@
 set -e
 
 ARCH=
+MACHINE=
 DATA_IMG="/export/data.ext4"
 VERSION_URL="https://version.home-assistant.io/stable.json"
 APPARMOR_URL="https://version.home-assistant.io/apparmor.txt"
@@ -14,6 +15,10 @@ while [[ $# -gt 0 ]]; do
             ARCH=$2
             shift
             ;;
+        --machine)
+            MACHINE=$2
+            shift
+            ;;
         *)
             exit 1
             ;;
@@ -26,12 +31,15 @@ DNS="homeassistant/${ARCH}-hassio-dns"
 AUDIO="homeassistant/${ARCH}-hassio-audio"
 CLI="homeassistant/${ARCH}-hassio-cli"
 MULTICAST="homeassistant/${ARCH}-hassio-multicast"
+OBSERVER="homeassistant/${ARCH}-hassio-observer"
+LANDINGPAGE="homeassistant/${MACHINE}-homeassistant:landingpage"
 
 SUPERVISOR_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.supervisor')
 DNS_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.dns')
 CLI_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.cli')
 AUDIO_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.audio')
 MULTICAST_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.multicast')
+OBSERVER_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.observer')
 
 # Make image
 dd if=/dev/zero of=${DATA_IMG} bs=1G count=1
@@ -72,6 +80,10 @@ docker pull "${CLI}:${CLI_VERSION}"
 docker pull "${DNS}:${DNS_VERSION}"
 docker pull "${AUDIO}:${AUDIO_VERSION}"
 docker pull "${MULTICAST}:${MULTICAST_VERSION}"
+docker pull "${OBSERVER}:${OBSERVER_VERSION}"
+
+# Install landing page
+docker pull "${LANDINGPAGE}"
 
 # Setup AppArmor
 mkdir -p "/mnt/data/supervisor/apparmor"

buildroot-external/package/hassio/hassio.mk

@@ -19,7 +19,8 @@ define HASSIO_INSTALL_TARGET_CMDS
 		-e BUILDER_UID="$(shell id -u)" -e BUILDER_GID="$(shell id -g)" \
 		-v $(BINARIES_DIR):/export \
 		hassos-hostapps \
-		--arch $(BR2_PACKAGE_HASSIO_ARCH)
+		--arch $(BR2_PACKAGE_HASSIO_ARCH) \
+		--machine $(BR2_PACKAGE_HASSIO_MACHINE)
 endef
 
 $(eval $(generic-package))

buildroot-external/patches/systemd/0002-time-wait-sync-log-inotify-errors.patch

@@ -0,0 +1,23 @@
+From 4a4298ef78e943d36f3b8d8e78bfa21b1506961e Mon Sep 17 00:00:00 2001
+From: Aman Gupta Karmani <aman@tmm1.net>
+Date: Mon, 12 Oct 2020 13:39:26 -0700
+Subject: [PATCH] time-wait-sync: log errors trying to watch
+ /run/systemd/timesync
+
+---
+ src/time-wait-sync/time-wait-sync.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/time-wait-sync/time-wait-sync.c b/src/time-wait-sync/time-wait-sync.c
+index 96072445f6e..c8ec4850426 100644
+--- a/src/time-wait-sync/time-wait-sync.c
++++ b/src/time-wait-sync/time-wait-sync.c
+@@ -50,7 +50,7 @@ static void clock_state_release(ClockState *sp) {
+ static int clock_state_update(ClockState *sp, sd_event *event);
+ 
+ static int update_notify_run_systemd_timesync(ClockState *sp) {
+-        sp->run_systemd_timesync_wd = inotify_add_watch(sp->inotify_fd, "/run/systemd/timesync", IN_CREATE|IN_DELETE_SELF);
++        sp->run_systemd_timesync_wd = inotify_add_watch_and_warn(sp->inotify_fd, "/run/systemd/timesync", IN_CREATE|IN_DELETE_SELF);
+         return sp->run_systemd_timesync_wd;
+ }
+ 

buildroot-external/patches/systemd/0003-fix-inotify-watches.patch

@@ -0,0 +1,54 @@
+From f6f4f5fe5395a57f10dd446c7266c53f0673eaac Mon Sep 17 00:00:00 2001
+From: Balaji Punnuru <balaji_punnuru@cable.comcast.com>
+Date: Thu, 9 Apr 2020 12:21:49 -0400
+Subject: [PATCH] util: return the correct correct wd from inotify helpers
+
+We need to propagate the acquired watch descriptors because our callers
+are counting on them.
+
+[Lennart: this is split out of #15381 and simplified]
+---
+ src/basic/fs-util.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/src/basic/fs-util.c b/src/basic/fs-util.c
+index 558cafbcaf5..ef3b5a51842 100644
+--- a/src/basic/fs-util.c
++++ b/src/basic/fs-util.c
+@@ -692,28 +692,30 @@ int unlink_or_warn(const char *filename) {
+ 
+ int inotify_add_watch_fd(int fd, int what, uint32_t mask) {
+         char path[STRLEN("/proc/self/fd/") + DECIMAL_STR_MAX(int) + 1];
+-        int r;
++        int wd;
+ 
+         /* This is like inotify_add_watch(), except that the file to watch is not referenced by a path, but by an fd */
+         xsprintf(path, "/proc/self/fd/%i", what);
+ 
+-        r = inotify_add_watch(fd, path, mask);
+-        if (r < 0)
++        wd = inotify_add_watch(fd, path, mask);
++        if (wd < 0)
+                 return -errno;
+ 
+-        return r;
++        return wd;
+ }
+ 
+ int inotify_add_watch_and_warn(int fd, const char *pathname, uint32_t mask) {
++        int wd;
+ 
+-        if (inotify_add_watch(fd, pathname, mask) < 0) {
++        wd = inotify_add_watch(fd, pathname, mask);
++        if (wd < 0) {
+                 if (errno == ENOSPC)
+                         return log_error_errno(errno, "Failed to add a watch for %s: inotify watch limit reached", pathname);
+ 
+                 return log_error_errno(errno, "Failed to add a watch for %s: %m", pathname);
+         }
+ 
+-        return 0;
++        return wd;
+ }
+ 
+ static bool unsafe_transition(const struct stat *a, const struct stat *b) {

buildroot-external/patches/uboot/2020.07/0001-CMD-read-string-from-fileinto-env.patch

@@ -1,96 +0,0 @@
-From 040a141f84f2f84bf8be18f85b4cdb34bf066df0 Mon Sep 17 00:00:00 2001
-Message-Id: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595086593.git.stefan@agner.ch>
-From: Pascal Vizeli <pvizeli@syshack.ch>
-Date: Sun, 5 Aug 2018 20:43:03 +0000
-Subject: [PATCH 1/1] CMD: read string from fileinto env
-
-Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
----
- cmd/Kconfig   |  5 +++++
- cmd/Makefile  |  1 +
- cmd/fileenv.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 51 insertions(+)
- create mode 100644 cmd/fileenv.c
-
-diff --git a/cmd/Kconfig b/cmd/Kconfig
-index 192b3b262f..b44cd64215 100644
---- a/cmd/Kconfig
-+++ b/cmd/Kconfig
-@@ -1388,6 +1388,11 @@ config CMD_SETEXPR
- 	  Also supports loading the value at a memory location into a variable.
- 	  If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
- 
-+config CMD_FILEENV
-+	bool "fileenv"
-+	help
-+	   Read a file into memory and store it to env.
-+
- endmenu
- 
- menu "Android support commands"
-diff --git a/cmd/Makefile b/cmd/Makefile
-index 974ad48b0a..287887e97f 100644
---- a/cmd/Makefile
-+++ b/cmd/Makefile
-@@ -128,6 +128,7 @@ obj-$(CONFIG_CMD_SF) += sf.o
- obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o
- obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
- obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
-+obj-$(CONFIG_CMD_FILEENV) += fileenv.o
- obj-$(CONFIG_CMD_SPI) += spi.o
- obj-$(CONFIG_CMD_STRINGS) += strings.o
- obj-$(CONFIG_CMD_SMC) += smccc.o
-diff --git a/cmd/fileenv.c b/cmd/fileenv.c
-new file mode 100644
-index 0000000000..af24d22d0e
---- /dev/null
-+++ b/cmd/fileenv.c
-@@ -0,0 +1,45 @@
-+#include <config.h>
-+#include <common.h>
-+#include <command.h>
-+#include <linux/ctype.h>
-+
-+static char *fs_argv[5];
-+
-+int do_fileenv(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
-+{
-+	if (argc < 6)
-+		return CMD_RET_USAGE;
-+
-+	fs_argv[0] = "fatload";
-+	fs_argv[1] = argv[1];
-+	fs_argv[2] = argv[2];
-+	fs_argv[3] = argv[3];
-+	fs_argv[4] = argv[4];
-+
-+	if (do_fat_fsload(cmdtp, 0, 5, fs_argv) != 0)
-+		return 1;
-+
-+	char *addr = (char *)simple_strtoul(argv[3], NULL, 16);
-+	size_t size = env_get_hex("filesize", 0);
-+
-+	// Prepare string
-+	addr[size] = 0x00;
-+	char *s = addr;
-+	while(*s != 0x00) {
-+		if (isprint(*s)) {
-+			s++;
-+		}
-+		else {
-+			*s = 0x00;
-+		}
-+	}
-+
-+	return env_set(argv[5], addr);
-+}
-+
-+U_BOOT_CMD(
-+	fileenv, 6, 0, do_fileenv,
-+	"Read file and store it into env.",
-+	"<interface> <dev:part> <addr> <filename> <envname>\n"
-+	"    - Read file from fat32 and store it as env."
-+);
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0002-usb-xhci-Add-missing-cache-flush-in-the-scratchpad-a.patch

@@ -1,41 +0,0 @@
-From b39cd5ba642ddba46268e8d873b952604844c047 Mon Sep 17 00:00:00 2001
-Message-Id: <b39cd5ba642ddba46268e8d873b952604844c047.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:51 +0200
-Subject: [PATCH 02/20] usb: xhci: Add missing cache flush in the scratchpad
- array initialization
-
-In current code there is no cache flush after initializing the scratchpad
-buffer array with the scratchpad buffer pointers. This leads to a failure
-of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
-controller + VL805 USB hub) - the very first TRB transfer on the command
-ring fails and there is a timeout while waiting for the command completion
-event. After adding the missing cache flush everything seems to be working
-as expected.
-
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/usb/host/xhci-mem.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
-index 2d968aafb0..f446520528 100644
---- a/drivers/usb/host/xhci-mem.c
-+++ b/drivers/usb/host/xhci-mem.c
-@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
- 		scratchpad->sp_array[i] = cpu_to_le64(ptr);
- 	}
- 
-+	xhci_flush_cache((uintptr_t)scratchpad->sp_array,
-+			 sizeof(u64) * num_sp);
-+
- 	return 0;
- 
- fail_sp3:
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0003-usb-xhci-Use-only-32-bit-accesses-in-xhci_writeq-xhc.patch

@@ -1,69 +0,0 @@
-From 71343be3dd8d7f04cea781c8369aa77a36ae7123 Mon Sep 17 00:00:00 2001
-Message-Id: <71343be3dd8d7f04cea781c8369aa77a36ae7123.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:52 +0200
-Subject: [PATCH 03/20] usb: xhci: Use only 32-bit accesses in
- xhci_writeq/xhci_readq
-
-There might be hardware configurations where 64-bit data accesses
-to XHCI registers are not supported properly.  This patch removes
-the readq/writeq so always two 32-bit accesses are used to read/write
-64-bit XHCI registers, similarly as it is done in Linux kernel.
-
-This patch fixes operation of the XHCI controller on RPI4 Broadcom
-BCM2711 SoC based board, where the VL805 USB XHCI controller is
-connected to the PCIe Root Complex, which is attached to the system
-through the SCB bridge.
-
-Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
-the 64-bit wide register accesses initiated by the CPU are not properly
-translated to a sequence of 32-bit PCIe accesses.
-xhci_readq(), for example, always returns same value in upper and lower
-32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
-
-Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- include/usb/xhci.h | 8 --------
- 1 file changed, 8 deletions(-)
-
-diff --git a/include/usb/xhci.h b/include/usb/xhci.h
-index 20e4a21066..1170c0ac69 100644
---- a/include/usb/xhci.h
-+++ b/include/usb/xhci.h
-@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
-  */
- static inline u64 xhci_readq(__le64 volatile *regs)
- {
--#if BITS_PER_LONG == 64
--	return readq(regs);
--#else
- 	__u32 *ptr = (__u32 *)regs;
- 	u64 val_lo = readl(ptr);
- 	u64 val_hi = readl(ptr + 1);
- 	return val_lo + (val_hi << 32);
--#endif
- }
- 
- static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
- {
--#if BITS_PER_LONG == 64
--	writeq(val, regs);
--#else
- 	__u32 *ptr = (__u32 *)regs;
- 	u32 val_lo = lower_32_bits(val);
- 	/* FIXME */
- 	u32 val_hi = upper_32_bits(val);
- 	writel(val_lo, ptr);
- 	writel(val_hi, ptr + 1);
--#endif
- }
- 
- int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0004-pci-Move-some-PCIe-register-offset-definitions-to-a-.patch

@@ -1,85 +0,0 @@
-From 82024c95e4d00b555f93d93b9f706c4d995ab302 Mon Sep 17 00:00:00 2001
-Message-Id: <82024c95e4d00b555f93d93b9f706c4d995ab302.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:53 +0200
-Subject: [PATCH 04/20] pci: Move some PCIe register offset definitions to a
- common header
-
-Some PCI Express register offsets are currently defined in multiple
-drivers, move them to a common header to avoid re-definitions and
-as a pre-requisite for adding new PCIe driver.
-While at it replace some spaces with tabs.
-
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/pci/pci-rcar-gen3.c   |  8 --------
- drivers/pci/pcie_intel_fpga.c |  3 ---
- include/pci.h                 | 13 +++++++++++--
- 3 files changed, 11 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
-index df7b37a592..1f51854ccc 100644
---- a/drivers/pci/pci-rcar-gen3.c
-+++ b/drivers/pci/pci-rcar-gen3.c
-@@ -118,14 +118,6 @@
- #define RCAR_PCI_MAX_RESOURCES	4
- #define MAX_NR_INBOUND_MAPS	6
- 
--#define PCI_EXP_FLAGS		2		/* Capabilities register */
--#define PCI_EXP_FLAGS_TYPE	0x00f0		/* Device/Port type */
--#define PCI_EXP_TYPE_ROOT_PORT	0x4		/* Root Port */
--#define PCI_EXP_LNKCAP		12		/* Link Capabilities */
--#define PCI_EXP_LNKCAP_DLLLARC	0x00100000	/* Data Link Layer Link Active Reporting Capable */
--#define PCI_EXP_SLTCAP		20		/* Slot Capabilities */
--#define PCI_EXP_SLTCAP_PSN	0xfff80000	/* Physical Slot Number */
--
- enum {
- 	RCAR_PCI_ACCESS_READ,
- 	RCAR_PCI_ACCESS_WRITE,
-diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
-index aa1903e547..9f102c64c6 100644
---- a/drivers/pci/pcie_intel_fpga.c
-+++ b/drivers/pci/pcie_intel_fpga.c
-@@ -67,9 +67,6 @@
- #define IS_ROOT_PORT(pcie, bdf)				\
- 		((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
- 
--#define PCI_EXP_LNKSTA		18	/* Link Status */
--#define PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
--
- /**
-  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
-  * @bus: Pointer to the PCI bus
-diff --git a/include/pci.h b/include/pci.h
-index 19c9244b94..9cd8564436 100644
---- a/include/pci.h
-+++ b/include/pci.h
-@@ -471,10 +471,19 @@
- #define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
- 
- /* PCI Express capabilities */
-+#define PCI_EXP_FLAGS		2	/* Capabilities register */
-+#define  PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
-+#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
- #define PCI_EXP_DEVCAP		4	/* Device capabilities */
--#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
-+#define  PCI_EXP_DEVCAP_FLR	0x10000000 /* Function Level Reset */
- #define PCI_EXP_DEVCTL		8	/* Device Control */
--#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
-+#define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
-+#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
-+#define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
-+#define PCI_EXP_LNKSTA		18	/* Link Status */
-+#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
-+#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
-+#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
- 
- /* Include the ID list */
- 
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0005-rpi4-shorten-a-mapping-for-the-DRAM.patch

@@ -1,33 +0,0 @@
-From 5dddca0c2ca5de72b74a5fca0d3ea67251add760 Mon Sep 17 00:00:00 2001
-Message-Id: <5dddca0c2ca5de72b74a5fca0d3ea67251add760.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Mon, 25 May 2020 13:39:54 +0200
-Subject: [PATCH 05/20] rpi4: shorten a mapping for the DRAM
-
-Remove the overlap between DRAM and device's IO area.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- arch/arm/mach-bcm283x/init.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
-index f4d00d892d..f9a5209480 100644
---- a/arch/arm/mach-bcm283x/init.c
-+++ b/arch/arm/mach-bcm283x/init.c
-@@ -39,7 +39,7 @@ static struct mm_region bcm2711_mem_map[] = {
- 	{
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
--		.size = 0xfe000000UL,
-+		.size = 0xfc000000UL,
- 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- 			 PTE_BLOCK_INNER_SHARE
- 	}, {
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0006-rpi4-add-a-mapping-for-the-PCIe-XHCI-controller-MMIO.patch

@@ -1,76 +0,0 @@
-From a326f58940f16b2dc3740fd9e87eb485da939ae5 Mon Sep 17 00:00:00 2001
-Message-Id: <a326f58940f16b2dc3740fd9e87eb485da939ae5.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Mon, 25 May 2020 13:39:55 +0200
-Subject: [PATCH 06/20] rpi4: add a mapping for the PCIe XHCI controller MMIO
- registers (ARM 64bit)
-
-Create a non-cacheable mapping for the 0x600000000 physical memory region,
-where MMIO registers for the PCIe XHCI controller are instantiated by the
-PCIe bridge.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++---
- 1 file changed, 15 insertions(+), 3 deletions(-)
-
-diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
-index f9a5209480..cf4c5b245d 100644
---- a/arch/arm/mach-bcm283x/init.c
-+++ b/arch/arm/mach-bcm283x/init.c
-@@ -12,10 +12,15 @@
- #include <dm/device.h>
- #include <fdt_support.h>
- 
-+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS	0x600000000UL
-+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE	0x800000UL
-+
- #ifdef CONFIG_ARM64
- #include <asm/armv8/mmu.h>
- 
--static struct mm_region bcm283x_mem_map[] = {
-+#define MEM_MAP_MAX_ENTRIES (4)
-+
-+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
- 	{
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
-@@ -35,7 +40,7 @@ static struct mm_region bcm283x_mem_map[] = {
- 	}
- };
- 
--static struct mm_region bcm2711_mem_map[] = {
-+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
- 	{
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
-@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
- 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- 			 PTE_BLOCK_NON_SHARE |
- 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+	}, {
-+		.virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
-+		.phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
-+		.size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+			 PTE_BLOCK_NON_SHARE |
-+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
- 	}, {
- 		/* List terminator */
- 		0,
-@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
- {
- 	int i;
- 
--	for (i = 0; i < 2; i++) {
-+	for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
- 		mem_map[i].virt = pd[i].virt;
- 		mem_map[i].phys = pd[i].phys;
- 		mem_map[i].size = pd[i].size;
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0007-linux-bitfield.h-Add-primitives-for-manipulating-bit.patch

@@ -1,85 +0,0 @@
-From 9c761488487ce27517e2a9e425f4ed0777708c53 Mon Sep 17 00:00:00 2001
-Message-Id: <9c761488487ce27517e2a9e425f4ed0777708c53.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 25 May 2020 13:39:56 +0200
-Subject: [PATCH 07/20] linux/bitfield.h: Add primitives for manipulating
- bitfields both in host- and fixed-endian
-
-Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
-an in depth explanation and two fixes from Johannes Berg:
- e7d4a95da86e0 "bitfield: fix *_encode_bits()",
- 37a3862e12382 "bitfield: add u8 helpers".
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-[s.nawrocki: added empty lines between functions and macros]
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
----
- include/linux/bitfield.h | 52 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
-diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
-index 8b9d6fff00..7ad8b088ed 100644
---- a/include/linux/bitfield.h
-+++ b/include/linux/bitfield.h
-@@ -103,4 +103,56 @@
- 		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));	\
- 	})
- 
-+extern void __compiletime_error("value doesn't fit into mask")
-+__field_overflow(void);
-+extern void __compiletime_error("bad bitfield mask")
-+__bad_mask(void);
-+
-+static __always_inline u64 field_multiplier(u64 field)
-+{
-+	if ((field | (field - 1)) & ((field | (field - 1)) + 1))
-+		__bad_mask();
-+	return field & -field;
-+}
-+
-+static __always_inline u64 field_mask(u64 field)
-+{
-+	return field / field_multiplier(field);
-+}
-+
-+#define ____MAKE_OP(type, base, to, from)				\
-+static __always_inline __##type type##_encode_bits(base v, base field)	\
-+{									\
-+	if (__builtin_constant_p(v) && (v & ~field_mask(field)))	\
-+		__field_overflow();					\
-+	return to((v & field_mask(field)) * field_multiplier(field));	\
-+}									\
-+static __always_inline __##type type##_replace_bits(__##type old,	\
-+					base val, base field)		\
-+{									\
-+	return (old & ~to(field)) | type##_encode_bits(val, field);	\
-+}									\
-+static __always_inline void type##p_replace_bits(__##type * p,		\
-+					base val, base field)		\
-+{									\
-+	*p = (*p & ~to(field)) | type##_encode_bits(val, field);	\
-+}									\
-+static __always_inline base type##_get_bits(__##type v, base field)	\
-+{									\
-+	return (from(v) & field) / field_multiplier(field);		\
-+}
-+
-+#define __MAKE_OP(size)							\
-+	____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
-+	____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
-+	____MAKE_OP(u##size, u##size, ,)
-+
-+____MAKE_OP(u8, u8, ,)
-+__MAKE_OP(16)
-+__MAKE_OP(32)
-+__MAKE_OP(64)
-+
-+#undef __MAKE_OP
-+#undef ____MAKE_OP
-+
- #endif
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0008-pci-Add-some-PCI-Express-capability-register-offset-.patch

@@ -1,47 +0,0 @@
-From 376bd33efa69abfc6102eb5a56b700c0f1981cf4 Mon Sep 17 00:00:00 2001
-Message-Id: <376bd33efa69abfc6102eb5a56b700c0f1981cf4.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:57 +0200
-Subject: [PATCH 08/20] pci: Add some PCI Express capability register offset
- definitions
-
-Add PCI Express capability definitions required by the Broadcom
-STB PCIe controller driver.
-
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- include/pci.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/include/pci.h b/include/pci.h
-index 9cd8564436..281f353916 100644
---- a/include/pci.h
-+++ b/include/pci.h
-@@ -479,11 +479,20 @@
- #define PCI_EXP_DEVCTL		8	/* Device Control */
- #define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
- #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
-+#define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */
-+#define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
- #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
- #define PCI_EXP_LNKSTA		18	/* Link Status */
-+#define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */
-+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
-+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
-+#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
-+#define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Negotiated Link Width */
-+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4	/* start of NLW mask in link status */
- #define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
- #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
- #define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
-+#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
- 
- /* Include the ID list */
- 
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0009-pci-Add-driver-for-Broadcom-BCM2711-SoC-PCIe-control.patch

@@ -1,686 +0,0 @@
-From 21a9b72b4a28398c9511f3d9e3c1adc1439a8870 Mon Sep 17 00:00:00 2001
-Message-Id: <21a9b72b4a28398c9511f3d9e3c1adc1439a8870.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:58 +0200
-Subject: [PATCH 09/20] pci: Add driver for Broadcom BCM2711 SoC PCIe
- controller
-
-This patch adds basic driver PCI Express controller found on Broadcom
-set-top-box SoCs, e.g. BCM2711.
-The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
-handling removed. The inbound access memory region is not currently
-parsed from dma-ranges DT property and a fixed 3GB region is used.
-
-The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
-USB Host Controller.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
----
- drivers/pci/Kconfig        |   9 +
- drivers/pci/Makefile       |   1 +
- drivers/pci/pcie_brcmstb.c | 623 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 633 insertions(+)
- create mode 100644 drivers/pci/pcie_brcmstb.c
-
-diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
-index 6d8c22aacf..7e1e51d9ea 100644
---- a/drivers/pci/Kconfig
-+++ b/drivers/pci/Kconfig
-@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP
- 	  Say Y here if you want to enable PCIe controller support on
- 	  Rockchip SoCs.
- 
-+config PCI_BRCMSTB
-+	bool "Broadcom STB PCIe controller"
-+	depends on DM_PCI
-+	depends on ARCH_BCM283X
-+	help
-+	  Say Y here if you want to enable support for PCIe controller
-+	  on Broadcom set-top-box (STB) SoCs.
-+	  This driver currently supports only BCM2711 SoC and RC mode
-+	  of the controller.
- endif
-diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
-index 955351c5c2..29092916a6 100644
---- a/drivers/pci/Makefile
-+++ b/drivers/pci/Makefile
-@@ -44,3 +44,4 @@ obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
- obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
- obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
- obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
-+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
-diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
-new file mode 100644
-index 0000000000..dade79e9c8
---- /dev/null
-+++ b/drivers/pci/pcie_brcmstb.c
-@@ -0,0 +1,623 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Broadcom STB PCIe controller driver
-+ *
-+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
-+ *
-+ * Based on upstream Linux kernel driver:
-+ * drivers/pci/controller/pcie-brcmstb.c
-+ * Copyright (C) 2009 - 2017 Broadcom
-+ *
-+ * Based driver by Nicolas Saenz Julienne
-+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-+ */
-+
-+#include <common.h>
-+#include <errno.h>
-+#include <dm.h>
-+#include <dm/ofnode.h>
-+#include <pci.h>
-+#include <asm/io.h>
-+#include <linux/bitfield.h>
-+#include <linux/log2.h>
-+#include <linux/iopoll.h>
-+
-+/* Offset of the mandatory PCIe capability config registers */
-+#define BRCM_PCIE_CAP_REGS				0x00ac
-+
-+/* The PCIe controller register offsets */
-+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1		0x0188
-+#define  VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK	0xc
-+#define  VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN		0x0
-+
-+#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
-+#define  CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK		0xffffff
-+
-+#define PCIE_RC_DL_MDIO_ADDR				0x1100
-+#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
-+#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
-+
-+#define PCIE_MISC_MISC_CTRL				0x4008
-+#define  MISC_CTRL_SCB_ACCESS_EN_MASK			0x1000
-+#define  MISC_CTRL_CFG_READ_UR_MODE_MASK		0x2000
-+#define  MISC_CTRL_MAX_BURST_SIZE_MASK			0x300000
-+#define  MISC_CTRL_MAX_BURST_SIZE_128			0x0
-+#define  MISC_CTRL_SCB0_SIZE_MASK			0xf8000000
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
-+#define PCIE_MEM_WIN0_LO(win)	\
-+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
-+#define PCIE_MEM_WIN0_HI(win)	\
-+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
-+
-+#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
-+#define  RC_BAR1_CONFIG_LO_SIZE_MASK			0x1f
-+
-+#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
-+#define  RC_BAR2_CONFIG_LO_SIZE_MASK			0x1f
-+#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
-+
-+#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
-+#define  RC_BAR3_CONFIG_LO_SIZE_MASK			0x1f
-+
-+#define PCIE_MISC_PCIE_STATUS				0x4068
-+#define  STATUS_PCIE_PORT_MASK				0x80
-+#define  STATUS_PCIE_PORT_SHIFT				7
-+#define  STATUS_PCIE_DL_ACTIVE_MASK			0x20
-+#define  STATUS_PCIE_DL_ACTIVE_SHIFT			5
-+#define  STATUS_PCIE_PHYLINKUP_MASK			0x10
-+#define  STATUS_PCIE_PHYLINKUP_SHIFT			4
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
-+#define  MEM_WIN0_BASE_LIMIT_LIMIT_MASK			0xfff00000
-+#define  MEM_WIN0_BASE_LIMIT_BASE_MASK			0xfff0
-+#define  MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT		12
-+#define PCIE_MEM_WIN0_BASE_LIMIT(win)	\
-+	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI		0x4080
-+#define  MEM_WIN0_BASE_HI_BASE_MASK			0xff
-+#define PCIE_MEM_WIN0_BASE_HI(win)	\
-+	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI		0x4084
-+#define  PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK		0xff
-+#define PCIE_MEM_WIN0_LIMIT_HI(win)	\
-+	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
-+
-+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
-+#define  PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
-+#define  PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
-+
-+#define PCIE_MSI_INTR2_CLR				0x4508
-+#define PCIE_MSI_INTR2_MASK_SET				0x4510
-+
-+#define PCIE_EXT_CFG_DATA				0x8000
-+
-+#define PCIE_EXT_CFG_INDEX				0x9000
-+#define  PCIE_EXT_BUSNUM_SHIFT				20
-+#define  PCIE_EXT_SLOT_SHIFT				15
-+#define  PCIE_EXT_FUNC_SHIFT				12
-+
-+#define PCIE_RGR1_SW_INIT_1				0x9210
-+#define  RGR1_SW_INIT_1_PERST_MASK			0x1
-+#define  RGR1_SW_INIT_1_INIT_MASK			0x2
-+
-+/* PCIe parameters */
-+#define BRCM_NUM_PCIE_OUT_WINS				4
-+
-+/* MDIO registers */
-+#define MDIO_PORT0					0x0
-+#define MDIO_DATA_MASK					0x7fffffff
-+#define MDIO_DATA_SHIFT					0
-+#define MDIO_PORT_MASK					0xf0000
-+#define MDIO_PORT_SHIFT					16
-+#define MDIO_REGAD_MASK					0xffff
-+#define MDIO_REGAD_SHIFT				0
-+#define MDIO_CMD_MASK					0xfff00000
-+#define MDIO_CMD_SHIFT					20
-+#define MDIO_CMD_READ					0x1
-+#define MDIO_CMD_WRITE					0x0
-+#define MDIO_DATA_DONE_MASK				0x80000000
-+#define SSC_REGS_ADDR					0x1100
-+#define SET_ADDR_OFFSET					0x1f
-+#define SSC_CNTL_OFFSET					0x2
-+#define SSC_CNTL_OVRD_EN_MASK				0x8000
-+#define SSC_CNTL_OVRD_VAL_MASK				0x4000
-+#define SSC_STATUS_OFFSET				0x1
-+#define SSC_STATUS_SSC_MASK				0x400
-+#define SSC_STATUS_SSC_SHIFT				10
-+#define SSC_STATUS_PLL_LOCK_MASK			0x800
-+#define SSC_STATUS_PLL_LOCK_SHIFT			11
-+
-+/**
-+ * struct brcm_pcie - the PCIe controller state
-+ * @base: Base address of memory mapped IO registers of the controller
-+ * @gen: Non-zero value indicates limitation of the PCIe controller operation
-+ *       to a specific generation (1, 2 or 3)
-+ * @ssc: true indicates active Spread Spectrum Clocking operation
-+ */
-+struct brcm_pcie {
-+	void __iomem		*base;
-+
-+	int			gen;
-+	bool			ssc;
-+};
-+
-+/**
-+ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
-+ * @size: The inbound region size
-+ *
-+ * This function converts size of the inbound "BAR" region to the non-linear
-+ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
-+ *
-+ * Return: The encoded inbound region size
-+ */
-+static int brcm_pcie_encode_ibar_size(u64 size)
-+{
-+	int log2_in = ilog2(size);
-+
-+	if (log2_in >= 12 && log2_in <= 15)
-+		/* Covers 4KB to 32KB (inclusive) */
-+		return (log2_in - 12) + 0x1c;
-+	else if (log2_in >= 16 && log2_in <= 37)
-+		/* Covers 64KB to 32GB, (inclusive) */
-+		return log2_in - 15;
-+
-+	/* Something is awry so disable */
-+	return 0;
-+}
-+
-+/**
-+ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
-+ * @pcie: Pointer to the PCIe controller state
-+ *
-+ * The controller is capable of serving in both RC and EP roles.
-+ *
-+ * Return: true for RC mode, false for EP mode.
-+ */
-+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
-+{
-+	u32 val;
-+
-+	val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
-+
-+	return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
-+}
-+
-+/**
-+ * brcm_pcie_link_up() - Check whether the PCIe link is up
-+ * @pcie: Pointer to the PCIe controller state
-+ *
-+ * Return: true if the link is up, false otherwise.
-+ */
-+static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
-+{
-+	u32 val, dla, plu;
-+
-+	val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
-+	dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
-+	plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
-+
-+	return dla && plu;
-+}
-+
-+static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
-+				    uint offset, void **paddress)
-+{
-+	struct brcm_pcie *pcie = dev_get_priv(dev);
-+	unsigned int pci_bus = PCI_BUS(bdf);
-+	unsigned int pci_dev = PCI_DEV(bdf);
-+	unsigned int pci_func = PCI_FUNC(bdf);
-+	int idx;
-+
-+	/*
-+	 * Busses 0 (host PCIe bridge) and 1 (its immediate child)
-+	 * are limited to a single device each
-+	 */
-+	if (pci_bus < 2 && pci_dev > 0)
-+		return -EINVAL;
-+
-+	/* Accesses to the RC go right to the RC registers */
-+	if (pci_bus == 0) {
-+		*paddress = pcie->base + offset;
-+		return 0;
-+	}
-+
-+	/* For devices, write to the config space index register */
-+	idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
-+		| (pci_dev << PCIE_EXT_SLOT_SHIFT)
-+		| (pci_func << PCIE_EXT_FUNC_SHIFT);
-+
-+	writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
-+	*paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
-+
-+	return 0;
-+}
-+
-+static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
-+				 uint offset, ulong *valuep,
-+				 enum pci_size_t size)
-+{
-+	return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
-+					    bdf, offset, valuep, size);
-+}
-+
-+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
-+				  uint offset, ulong value,
-+				  enum pci_size_t size)
-+{
-+	return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
-+					     bdf, offset, value, size);
-+}
-+
-+static const char *link_speed_to_str(unsigned int cls)
-+{
-+	switch (cls) {
-+	case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
-+	case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
-+	case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
-+	default:
-+		break;
-+	}
-+
-+	return "??";
-+}
-+
-+static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
-+				   unsigned int cmd)
-+{
-+	u32 pkt;
-+
-+	pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
-+	pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
-+	pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
-+
-+	return pkt;
-+}
-+
-+/**
-+ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
-+ * @base: Pointer to the PCIe controller IO registers
-+ * @port: The MDIO port number
-+ * @regad: The register address
-+ * @val: A pointer at which to store the read value
-+ *
-+ * Return: 0 on success and register value in @val, negative error value
-+ *         on failure.
-+ */
-+static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
-+			       unsigned int regad, u32 *val)
-+{
-+	u32 data, addr;
-+	int ret;
-+
-+	addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
-+	writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
-+	readl(base + PCIE_RC_DL_MDIO_ADDR);
-+
-+	ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
-+				 (data & MDIO_DATA_DONE_MASK), 100);
-+
-+	*val = data & MDIO_DATA_MASK;
-+
-+	return ret;
-+}
-+
-+/**
-+ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
-+ * @base: Pointer to the PCIe controller IO registers
-+ * @port: The MDIO port number
-+ * @regad: Address of the register
-+ * @wrdata: The value to write
-+ *
-+ * Return: 0 on success, negative error value on failure.
-+ */
-+static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
-+				unsigned int regad, u16 wrdata)
-+{
-+	u32 data, addr;
-+
-+	addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
-+	writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
-+	readl(base + PCIE_RC_DL_MDIO_ADDR);
-+	writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
-+
-+	return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
-+				  !(data & MDIO_DATA_DONE_MASK), 100);
-+}
-+
-+/**
-+ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
-+ * @base: pointer to the PCIe controller IO registers
-+ *
-+ * Return: 0 on success, negative error value on failure.
-+ */
-+static int brcm_pcie_set_ssc(void __iomem *base)
-+{
-+	int pll, ssc;
-+	int ret;
-+	u32 tmp;
-+
-+	ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
-+				   SSC_REGS_ADDR);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
-+	if (ret < 0)
-+		return ret;
-+
-+	tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
-+
-+	ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
-+	if (ret < 0)
-+		return ret;
-+
-+	udelay(1000);
-+	ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
-+	if (ret < 0)
-+		return ret;
-+
-+	ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
-+	pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
-+
-+	return ssc && pll ? 0 : -EIO;
-+}
-+
-+/**
-+ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
-+ * @pcie: pointer to the PCIe controller state
-+ * @gen: PCIe generation to limit the controller's operation to
-+ */
-+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
-+{
-+	void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
-+
-+	u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
-+	u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
-+
-+	lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
-+	writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
-+
-+	lnkctl2 = (lnkctl2 & ~0xf) | gen;
-+	writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
-+}
-+
-+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
-+				       unsigned int win, u64 phys_addr,
-+				       u64 pcie_addr, u64 size)
-+{
-+	void __iomem *base = pcie->base;
-+	u32 phys_addr_mb_high, limit_addr_mb_high;
-+	phys_addr_t phys_addr_mb, limit_addr_mb;
-+	int high_addr_shift;
-+	u32 tmp;
-+
-+	/* Set the base of the pcie_addr window */
-+	writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
-+	writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
-+
-+	/* Write the addr base & limit lower bits (in MBs) */
-+	phys_addr_mb = phys_addr / SZ_1M;
-+	limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
-+
-+	tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
-+	u32p_replace_bits(&tmp, phys_addr_mb,
-+			  MEM_WIN0_BASE_LIMIT_BASE_MASK);
-+	u32p_replace_bits(&tmp, limit_addr_mb,
-+			  MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
-+	writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
-+
-+	/* Write the cpu & limit addr upper bits */
-+	high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
-+	phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
-+	tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
-+	u32p_replace_bits(&tmp, phys_addr_mb_high,
-+			  MEM_WIN0_BASE_HI_BASE_MASK);
-+	writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
-+
-+	limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
-+	tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
-+	u32p_replace_bits(&tmp, limit_addr_mb_high,
-+			  PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
-+	writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
-+}
-+
-+static int brcm_pcie_probe(struct udevice *dev)
-+{
-+	struct udevice *ctlr = pci_get_controller(dev);
-+	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
-+	struct brcm_pcie *pcie = dev_get_priv(dev);
-+	void __iomem *base = pcie->base;
-+	bool ssc_good = false;
-+	int num_out_wins = 0;
-+	u64 rc_bar2_offset, rc_bar2_size;
-+	unsigned int scb_size_val;
-+	int i, ret;
-+	u16 nlw, cls, lnksta;
-+	u32 tmp;
-+
-+	/*
-+	 * Reset the bridge, assert the fundamental reset. Note for some SoCs,
-+	 * e.g. BCM7278, the fundamental reset should not be asserted here.
-+	 * This will need to be changed when support for other SoCs is added.
-+	 */
-+	setbits_le32(base + PCIE_RGR1_SW_INIT_1,
-+		     RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
-+	/*
-+	 * The delay is a safety precaution to preclude the reset signal
-+	 * from looking like a glitch.
-+	 */
-+	udelay(100);
-+
-+	/* Take the bridge out of reset */
-+	clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
-+
-+	clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
-+		     PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
-+
-+	/* Wait for SerDes to be stable */
-+	udelay(100);
-+
-+	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
-+	clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
-+			MISC_CTRL_MAX_BURST_SIZE_MASK,
-+			MISC_CTRL_SCB_ACCESS_EN_MASK |
-+			MISC_CTRL_CFG_READ_UR_MODE_MASK |
-+			MISC_CTRL_MAX_BURST_SIZE_128);
-+	/*
-+	 * TODO: When support for other SoCs than BCM2711 is added we may
-+	 * need to use the base address and size(s) provided in the dma-ranges
-+	 * property.
-+	 */
-+	rc_bar2_offset = 0;
-+	rc_bar2_size = 0xc0000000;
-+
-+	tmp = lower_32_bits(rc_bar2_offset);
-+	u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
-+			  RC_BAR2_CONFIG_LO_SIZE_MASK);
-+	writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
-+	writel(upper_32_bits(rc_bar2_offset),
-+	       base + PCIE_MISC_RC_BAR2_CONFIG_HI);
-+
-+	scb_size_val = rc_bar2_size ?
-+		       ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
-+
-+	tmp = readl(base + PCIE_MISC_MISC_CTRL);
-+	u32p_replace_bits(&tmp, scb_size_val,
-+			  MISC_CTRL_SCB0_SIZE_MASK);
-+	writel(tmp, base + PCIE_MISC_MISC_CTRL);
-+
-+	/* Disable the PCIe->GISB memory window (RC_BAR1) */
-+	clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
-+		     RC_BAR1_CONFIG_LO_SIZE_MASK);
-+
-+	/* Disable the PCIe->SCB memory window (RC_BAR3) */
-+	clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
-+		     RC_BAR3_CONFIG_LO_SIZE_MASK);
-+
-+	/* Mask all interrupts since we are not handling any yet */
-+	writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
-+
-+	/* Clear any interrupts we find on boot */
-+	writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
-+
-+	if (pcie->gen)
-+		brcm_pcie_set_gen(pcie, pcie->gen);
-+
-+	/* Unassert the fundamental reset */
-+	clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
-+		     RGR1_SW_INIT_1_PERST_MASK);
-+
-+	/* Give the RC/EP time to wake up, before trying to configure RC.
-+	 * Intermittently check status for link-up, up to a total of 100ms.
-+	 */
-+	for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
-+		mdelay(5);
-+
-+	if (!brcm_pcie_link_up(pcie)) {
-+		printf("PCIe BRCM: link down\n");
-+		return -EINVAL;
-+	}
-+
-+	if (!brcm_pcie_rc_mode(pcie)) {
-+		printf("PCIe misconfigured; is in EP mode\n");
-+		return -EINVAL;
-+	}
-+
-+	for (i = 0; i < hose->region_count; i++) {
-+		struct pci_region *reg = &hose->regions[i];
-+
-+		if (reg->flags != PCI_REGION_MEM)
-+			continue;
-+
-+		if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
-+			return -EINVAL;
-+
-+		brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
-+					   reg->bus_start, reg->size);
-+
-+		num_out_wins++;
-+	}
-+
-+	/*
-+	 * For config space accesses on the RC, show the right class for
-+	 * a PCIe-PCIe bridge (the default setting is to be EP mode).
-+	 */
-+	clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
-+			CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
-+
-+	if (pcie->ssc) {
-+		ret = brcm_pcie_set_ssc(pcie->base);
-+		if (!ret)
-+			ssc_good = true;
-+		else
-+			printf("PCIe BRCM: failed attempt to enter SSC mode\n");
-+	}
-+
-+	lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
-+	cls = lnksta & PCI_EXP_LNKSTA_CLS;
-+	nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
-+
-+	printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
-+	       nlw, ssc_good ? "(SSC)" : "(!SSC)");
-+
-+	/* PCIe->SCB endian mode for BAR */
-+	clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
-+			VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
-+			VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
-+	/*
-+	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
-+	 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
-+	 */
-+	setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
-+		     PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
-+
-+	return 0;
-+}
-+
-+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
-+{
-+	struct brcm_pcie *pcie = dev_get_priv(dev);
-+	ofnode dn = dev_ofnode(dev);
-+	u32 max_link_speed;
-+	int ret;
-+
-+	/* Get the controller base address */
-+	pcie->base = dev_read_addr_ptr(dev);
-+	if (!pcie->base)
-+		return -EINVAL;
-+
-+	pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
-+
-+	ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
-+	if (ret < 0 || max_link_speed > 4)
-+		pcie->gen = 0;
-+	else
-+		pcie->gen = max_link_speed;
-+
-+	return 0;
-+}
-+
-+static const struct dm_pci_ops brcm_pcie_ops = {
-+	.read_config	= brcm_pcie_read_config,
-+	.write_config	= brcm_pcie_write_config,
-+};
-+
-+static const struct udevice_id brcm_pcie_ids[] = {
-+	{ .compatible = "brcm,bcm2711-pcie" },
-+	{ }
-+};
-+
-+U_BOOT_DRIVER(pcie_brcm_base) = {
-+	.name			= "pcie_brcm",
-+	.id			= UCLASS_PCI,
-+	.ops			= &brcm_pcie_ops,
-+	.of_match		= brcm_pcie_ids,
-+	.probe			= brcm_pcie_probe,
-+	.ofdata_to_platdata	= brcm_pcie_ofdata_to_platdata,
-+	.priv_auto_alloc_size	= sizeof(struct brcm_pcie),
-+};
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0010-configs-Enable-support-for-the-XHCI-controller-on-RP.patch

@@ -1,102 +0,0 @@
-From 66537b5984af81b5add420df9eb64c508268f581 Mon Sep 17 00:00:00 2001
-Message-Id: <66537b5984af81b5add420df9eb64c508268f581.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Mon, 25 May 2020 13:39:59 +0200
-Subject: [PATCH 10/20] configs: Enable support for the XHCI controller on RPI4
- board (ARM 64-bit)
-
-This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
-and USB commands. To get it working one has to call the following commands:
-"pci enum; usb start;", thus such commands have been added to the default
-"preboot" environment variable. One has to update their environment if it
-is already configured to get this feature working out of the box.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
----
- configs/rpi_4_defconfig     | 9 +++++++++
- configs/rpi_arm64_defconfig | 8 +++++++-
- 2 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
-index f0301dc8bc..b42efe6072 100644
---- a/configs/rpi_4_defconfig
-+++ b/configs/rpi_4_defconfig
-@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
- CONFIG_ENV_SIZE=0x4000
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_OF_BOARD_SETUP=y
-+CONFIG_USE_PREBOOT=y
-+CONFIG_PREBOOT="pci enum; usb start;"
- CONFIG_MISC_INIT_R=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
-@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
- CONFIG_CMD_DFU=y
- CONFIG_CMD_GPIO=y
- CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
- CONFIG_CMD_FS_UUID=y
- CONFIG_OF_BOARD=y
- CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
-@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y
- CONFIG_MMC_SDHCI_BCM2835=y
- CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
-+CONFIG_PCI=y
-+CONFIG_DM_PCI=y
-+CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
- CONFIG_DM_USB_GADGET=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PCI=y
- CONFIG_USB_GADGET=y
- CONFIG_USB_GADGET_MANUFACTURER="FSL"
- CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
-index d16c2388af..0feea7f0be 100644
---- a/configs/rpi_arm64_defconfig
-+++ b/configs/rpi_arm64_defconfig
-@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_OF_BOARD_SETUP=y
- CONFIG_USE_PREBOOT=y
--CONFIG_PREBOOT="usb start"
-+CONFIG_PREBOOT="pci enum; usb start;"
- CONFIG_MISC_INIT_R=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
- CONFIG_SYS_PROMPT="U-Boot> "
- CONFIG_CMD_GPIO=y
- CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
- CONFIG_CMD_USB=y
- CONFIG_CMD_FS_UUID=y
- CONFIG_OF_BOARD=y
-@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y
- CONFIG_MMC_SDHCI_BCM2835=y
- CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
-+CONFIG_PCI=y
-+CONFIG_DM_PCI=y
-+CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PCI=y
- CONFIG_USB_DWC2=y
- CONFIG_USB_KEYBOARD=y
- CONFIG_USB_HOST_ETHER=y
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0011-arm-rpi-Add-function-to-trigger-VL805-s-firmware-loa.patch

@@ -1,131 +0,0 @@
-From 2899e2cbe5412ee6f6a01855467fa37534ffc2be Mon Sep 17 00:00:00 2001
-Message-Id: <2899e2cbe5412ee6f6a01855467fa37534ffc2be.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:22 +0200
-Subject: [PATCH 11/20] arm: rpi: Add function to trigger VL805's firmware load
-
-On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
-may either be loaded directly from an EEPROM or, if not present, by the
-SoC's VideCore (the SoC's co-processor). Introduce the function that
-informs VideCore that VL805 may need its firmware loaded.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++
- arch/arm/mach-bcm283x/include/mach/msg.h  |  7 ++++
- arch/arm/mach-bcm283x/msg.c               | 46 +++++++++++++++++++++++
- 3 files changed, 66 insertions(+)
-
-diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
-index 60e226ce1d..2ae2d3d97c 100644
---- a/arch/arm/mach-bcm283x/include/mach/mbox.h
-+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
-@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette {
- 	} body;
- };
- 
-+#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET          0x00030058
-+
-+struct bcm2835_mbox_tag_pci_dev_addr {
-+	struct bcm2835_mbox_tag_hdr tag_hdr;
-+	union {
-+		struct {
-+			u32 dev_addr;
-+		} req;
-+		struct {
-+		} resp;
-+	} body;
-+};
-+
- /*
-  * Pass a raw u32 message to the VC, and receive a raw u32 back.
-  *
-diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h
-index 4afb08631b..e45c1bf010 100644
---- a/arch/arm/mach-bcm283x/include/mach/msg.h
-+++ b/arch/arm/mach-bcm283x/include/mach/msg.h
-@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
- 			     int pixel_order, int alpha_mode, ulong *fb_basep,
- 			     ulong *fb_sizep, int *pitchp);
- 
-+/**
-+ * bcm2711_load_vl805_firmware() - get vl805's firmware loaded
-+ *
-+ * @return 0 if OK, -EIO on error
-+ */
-+int bcm2711_notify_vl805_reset(void);
-+
- #endif
-diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
-index 94b75283f8..347aece3cd 100644
---- a/arch/arm/mach-bcm283x/msg.c
-+++ b/arch/arm/mach-bcm283x/msg.c
-@@ -7,6 +7,7 @@
- #include <memalign.h>
- #include <phys2bus.h>
- #include <asm/arch/mbox.h>
-+#include <linux/delay.h>
- 
- struct msg_set_power_state {
- 	struct bcm2835_mbox_hdr hdr;
-@@ -40,6 +41,12 @@ struct msg_setup {
- 	u32 end_tag;
- };
- 
-+struct msg_notify_vl805_reset {
-+	struct bcm2835_mbox_hdr hdr;
-+	struct bcm2835_mbox_tag_pci_dev_addr dev_addr;
-+	u32 end_tag;
-+};
-+
- int bcm2835_power_on_module(u32 module)
- {
- 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
-@@ -151,3 +158,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
- 
- 	return 0;
- }
-+
-+/*
-+ * On the Raspberry Pi 4, after a PCI reset, VL805's (the xHCI chip) firmware
-+ * may either be loaded directly from an EEPROM or, if not present, by the
-+ * SoC's VideoCore. This informs VideoCore that VL805 needs its firmware
-+ * loaded.
-+ */
-+int bcm2711_notify_vl805_reset(void)
-+{
-+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
-+				 msg_notify_vl805_reset, 1);
-+	int ret;
-+
-+	BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
-+	BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,
-+			      NOTIFY_XHCI_RESET);
-+
-+	/*
-+	 * The pci device address is expected like this:
-+	 *
-+	 *   PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12
-+	 *
-+	 * But since RPi4's PCIe setup is hardwired, we know the address in
-+	 * advance.
-+	 */
-+	msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000;
-+
-+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
-+				     &msg_notify_vl805_reset->hdr);
-+	if (ret) {
-+		printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
-+		return -EIO;
-+	}
-+
-+	udelay(200);
-+
-+	return 0;
-+}
-+
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0012-reset-Add-Raspberry-Pi-4-firmware-reset-controller.patch

@@ -1,140 +0,0 @@
-From e9925f97c2c31253e1ff62de4049d90e19884f55 Mon Sep 17 00:00:00 2001
-Message-Id: <e9925f97c2c31253e1ff62de4049d90e19884f55.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:23 +0200
-Subject: [PATCH 12/20] reset: Add Raspberry Pi 4 firmware reset controller
-
-Raspberry Pi 4's co-processor controls some of the board's HW
-initialization process, but it's up to Linux to trigger it when
-relevant. Introduce a reset controller capable of interfacing with
-RPi4's co-processor that models these firmware initialization routines as
-reset lines.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/reset/Kconfig                         | 10 ++++
- drivers/reset/Makefile                        |  1 +
- drivers/reset/reset-raspberrypi.c             | 60 +++++++++++++++++++
- .../reset/raspberrypi,firmware-reset.h        | 13 ++++
- 4 files changed, 84 insertions(+)
- create mode 100644 drivers/reset/reset-raspberrypi.c
- create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
-
-diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
-index 88d3be1593..d02c1522e5 100644
---- a/drivers/reset/Kconfig
-+++ b/drivers/reset/Kconfig
-@@ -148,4 +148,14 @@ config RESET_IMX7
- 	help
- 	  Support for reset controller on i.MX7/8 SoCs.
- 
-+config RESET_RASPBERRYPI
-+	bool "Raspberry Pi 4 Firmware Reset Controller Driver"
-+	depends on DM_RESET && ARCH_BCM283X
-+	default USB_XHCI_PCI
-+	help
-+	  Raspberry Pi 4's co-processor controls some of the board's HW
-+	  initialization process, but it's up to Linux to trigger it when
-+	  relevant. This driver provides a reset controller capable of
-+	  interfacing with RPi4's co-processor and model these firmware
-+	  initialization routines as reset lines.
- endmenu
-diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
-index 0a044d5d8c..be54dae725 100644
---- a/drivers/reset/Makefile
-+++ b/drivers/reset/Makefile
-@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
- obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
- obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
- obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
-+obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
-diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c
-new file mode 100644
-index 0000000000..e2d284e5ac
---- /dev/null
-+++ b/drivers/reset/reset-raspberrypi.c
-@@ -0,0 +1,60 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Raspberry Pi 4 firmware reset driver
-+ *
-+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-+ */
-+#include <common.h>
-+#include <dm.h>
-+#include <reset-uclass.h>
-+#include <asm/arch/msg.h>
-+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-+
-+static int raspberrypi_reset_request(struct reset_ctl *reset_ctl)
-+{
-+	if (reset_ctl->id >= RASPBERRYPI_FIRMWARE_RESET_NUM_IDS)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int raspberrypi_reset_free(struct reset_ctl *reset_ctl)
-+{
-+	return 0;
-+}
-+
-+static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl)
-+{
-+	switch (reset_ctl->id) {
-+	case RASPBERRYPI_FIRMWARE_RESET_ID_USB:
-+		bcm2711_notify_vl805_reset();
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int raspberrypi_reset_deassert(struct reset_ctl *reset_ctl)
-+{
-+	return 0;
-+}
-+
-+struct reset_ops raspberrypi_reset_ops = {
-+	.request = raspberrypi_reset_request,
-+	.rfree = raspberrypi_reset_free,
-+	.rst_assert = raspberrypi_reset_assert,
-+	.rst_deassert = raspberrypi_reset_deassert,
-+};
-+
-+static const struct udevice_id raspberrypi_reset_ids[] = {
-+	{ .compatible = "raspberrypi,firmware-reset" },
-+	{ }
-+};
-+
-+U_BOOT_DRIVER(raspberrypi_reset) = {
-+	.name = "raspberrypi-reset",
-+	.id = UCLASS_RESET,
-+	.of_match = raspberrypi_reset_ids,
-+	.ops = &raspberrypi_reset_ops,
-+};
-+
-diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-new file mode 100644
-index 0000000000..1a4f4c7927
---- /dev/null
-+++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (c) 2020 Nicolas Saenz Julienne
-+ * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+
-+#define RASPBERRYPI_FIRMWARE_RESET_ID_USB	0
-+#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS	1
-+
-+#endif
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0013-configs-Enable-support-for-reset-controllers-on-RPi4.patch

@@ -1,57 +0,0 @@
-From d32b13ba58aa59a5ec0b71cfc2005bf1efd84ddf Mon Sep 17 00:00:00 2001
-Message-Id: <d32b13ba58aa59a5ec0b71cfc2005bf1efd84ddf.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:24 +0200
-Subject: [PATCH 13/20] configs: Enable support for reset controllers on RPi4
-
-This is required in order to access the reset controller used to
-initialize the board's xHCI chip.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- configs/rpi_4_32b_defconfig | 1 +
- configs/rpi_4_defconfig     | 1 +
- configs/rpi_arm64_defconfig | 1 +
- 3 files changed, 3 insertions(+)
-
-diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
-index a36a249540..0df5c17d6e 100644
---- a/configs/rpi_4_32b_defconfig
-+++ b/configs/rpi_4_32b_defconfig
-@@ -28,6 +28,7 @@ CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
-+CONFIG_DM_RESET=y
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
-diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
-index b42efe6072..f641ad3dfa 100644
---- a/configs/rpi_4_defconfig
-+++ b/configs/rpi_4_defconfig
-@@ -35,6 +35,7 @@ CONFIG_DM_PCI=y
- CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
-+CONFIG_DM_RESET=y
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
-diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
-index 0feea7f0be..4ce8469f43 100644
---- a/configs/rpi_arm64_defconfig
-+++ b/configs/rpi_arm64_defconfig
-@@ -32,6 +32,7 @@ CONFIG_DM_PCI=y
- CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
-+CONFIG_DM_RESET=y
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0014-usb-xhci-Add-reset-controller-support.patch

@@ -1,106 +0,0 @@
-From a39dcf665d8867875b104661bd6a6325f502c5f2 Mon Sep 17 00:00:00 2001
-Message-Id: <a39dcf665d8867875b104661bd6a6325f502c5f2.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:25 +0200
-Subject: [PATCH 14/20] usb: xhci: Add reset controller support
-
-Some atypical users of xhci might need to manually reset their xHCI
-controller before starting the HCD setup. Check if a reset controller
-device is available to the PCI bus and trigger a reset.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/usb/host/xhci-mem.c |  2 ++
- drivers/usb/host/xhci.c     | 33 +++++++++++++++++++++++++++++++++
- include/usb/xhci.h          |  2 ++
- 3 files changed, 37 insertions(+)
-
-diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
-index f446520528..108f4bd8cf 100644
---- a/drivers/usb/host/xhci-mem.c
-+++ b/drivers/usb/host/xhci-mem.c
-@@ -180,6 +180,8 @@ void xhci_cleanup(struct xhci_ctrl *ctrl)
- 	xhci_free_virt_devices(ctrl);
- 	free(ctrl->erst.entries);
- 	free(ctrl->dcbaa);
-+	if (reset_valid(&ctrl->reset))
-+		reset_free(&ctrl->reset);
- 	memset(ctrl, '\0', sizeof(struct xhci_ctrl));
- }
- 
-diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
-index ebd2954571..e252964d0d 100644
---- a/drivers/usb/host/xhci.c
-+++ b/drivers/usb/host/xhci.c
-@@ -190,6 +190,35 @@ static int xhci_start(struct xhci_hcor *hcor)
- 	return ret;
- }
- 
-+/**
-+ * Resets XHCI Hardware
-+ *
-+ * @param ctrl	pointer to host controller
-+ * @return 0 if OK, or a negative error code.
-+ */
-+static int xhci_reset_hw(struct xhci_ctrl *ctrl)
-+{
-+	int ret;
-+
-+	ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
-+	if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
-+		dev_err(ctrl->dev, "failed to get reset\n");
-+		return ret;
-+	}
-+
-+	if (reset_valid(&ctrl->reset)) {
-+		ret = reset_assert(&ctrl->reset);
-+		if (ret)
-+			return ret;
-+
-+		ret = reset_deassert(&ctrl->reset);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
- /**
-  * Resets the XHCI Controller
-  *
-@@ -1508,6 +1537,10 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
- 
- 	ctrl->dev = dev;
- 
-+	ret = xhci_reset_hw(ctrl);
-+	if (ret)
-+		goto err;
-+
- 	/*
- 	 * XHCI needs to issue a Address device command to setup
- 	 * proper device context structures, before it can interact
-diff --git a/include/usb/xhci.h b/include/usb/xhci.h
-index 1170c0ac69..7d34103fd5 100644
---- a/include/usb/xhci.h
-+++ b/include/usb/xhci.h
-@@ -16,6 +16,7 @@
- #ifndef HOST_XHCI_H_
- #define HOST_XHCI_H_
- 
-+#include <reset.h>
- #include <asm/types.h>
- #include <asm/cache.h>
- #include <asm/io.h>
-@@ -1209,6 +1210,7 @@ struct xhci_ctrl {
- #if CONFIG_IS_ENABLED(DM_USB)
- 	struct udevice *dev;
- #endif
-+	struct reset_ctl reset;
- 	struct xhci_hccr *hccr;	/* R/O registers, not need for volatile */
- 	struct xhci_hcor *hcor;
- 	struct xhci_doorbell_array *dba;
--- 
-2.27.0
-