78152db78f
* Backport USB PCIe/XHCI patches to U-Boot 2020.07 Backport relevant patches required to make PCIe/USB XHCI work. * Backport/integrate PCIe device tree changes from upstream Linux U-Boot uses the device tree provided by upstream Linux. Make sure the device tree has the relevant chanages to make VL805 USB controller reset work. * Document RPi 4 USB mass storage support (#746)
42 lines
1.6 KiB
Diff
42 lines
1.6 KiB
Diff
From b39cd5ba642ddba46268e8d873b952604844c047 Mon Sep 17 00:00:00 2001
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Message-Id: <b39cd5ba642ddba46268e8d873b952604844c047.1595101389.git.stefan@agner.ch>
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In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
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References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
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From: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Date: Mon, 25 May 2020 13:39:51 +0200
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Subject: [PATCH 02/20] usb: xhci: Add missing cache flush in the scratchpad
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array initialization
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In current code there is no cache flush after initializing the scratchpad
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buffer array with the scratchpad buffer pointers. This leads to a failure
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of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
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controller + VL805 USB hub) - the very first TRB transfer on the command
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ring fails and there is a timeout while waiting for the command completion
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event. After adding the missing cache flush everything seems to be working
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as expected.
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Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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---
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drivers/usb/host/xhci-mem.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
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index 2d968aafb0..f446520528 100644
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--- a/drivers/usb/host/xhci-mem.c
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+++ b/drivers/usb/host/xhci-mem.c
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@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
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scratchpad->sp_array[i] = cpu_to_le64(ptr);
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}
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+ xhci_flush_cache((uintptr_t)scratchpad->sp_array,
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+ sizeof(u64) * num_sp);
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+
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return 0;
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fail_sp3:
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--
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2.27.0
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