Revert DTS rpi4

* Odroid: Update kernel 5.7.7

* Linux: Update kernel 5.4.50

* RaspberryPi: Update kernel 4.19.127 - a03605b08ae73107100c72dc92c92adf0dde3e42

* Fix script

* Add bcm2711-rpi-cm4

.github/ISSUE_TEMPLATE.md

@@ -1,23 +1,21 @@
 <!-- READ THIS FIRST:
 - If you need additional help with this template please refer to https://www.home-assistant.io/help/reporting_issues/
-- Make sure you are running the latest version before reporting an issue: https://github.com/home-assistant/core/releases
-- Do not report issues for integrations here, please refer to https://github.com/home-assistant/core/issues
+- Make sure you are running the latest version before reporting an issue: https://github.com/home-assistant/home-assistant/releases
+- Do not report issues for components here, plaese refer to https://github.com/home-assistant/home-assistant/issues
 - This is for bugs only. Feature and enhancement requests should go in our community forum: https://community.home-assistant.io/c/feature-requests
 - Provide as many details as possible. Paste logs, configuration sample and code into the backticks. Do not delete any text from this template!
-- If you have a problem with an add-on, make an issue in its repository.
-- If you are using Raspberry Pi overlays in config.txt and your system doesn't work anymore please report this to the Raspberry Pi kernel project.
-
+- If you have a problem with a Add-on, make a issue on there repository.
 -->
 
 **HassOS release with the issue:**
 <!--
-- Frontend -> Configuration -> Info
+- Frontend -> Developer tools -> Info
 - Or use this command: hass --version
 -->
 
 **Supervisor logs:**
 <!--
-- Frontend -> Supervisor -> System
+- Frontend -> Hass.io -> System
 - Or use this command: ha su logs
 -->
 

Documentation/boards/nuc.md

@@ -8,8 +8,7 @@ Requirements:
 - UEFI boot
 - SATA/AHCI storage
 - Supported NIC:
-  - Intel Gigabit NIC (e1000, igb - via Linux mainline)
-  - Intel PCIe Gigabit NIC (e1000e - via out-of-tree module in *buildroot-external/package/intel-e1000e*)
+  - Intel Gigabit NIC (e1000, e1000e, igb)
   - Realtek Gigabit NIC (r8169)
   - Intel Wireless Wifi 802.11ac (iwlwifi, see below)
 
@@ -19,7 +18,6 @@ Requirements:
 |--------|-----------|
 | Intel NUC5CPYH |  |
 | Intel NUC6CAYH |  |
-| Intel NUC10I3FNK2 |  |
 | Gigabyte GB-BPCE-3455 | needs 'nomodeset' in cmdline.txt if you want a console |
 
 

Documentation/boards/raspberrypi.md

@@ -31,13 +31,8 @@ i2c-bcm2708
 
 ## USB Boot
 
-USB mass storage boot is available on Raspberry Pi 4 (64-bit only), 3B, 3B+, 3A+, and 2B v1.2.
-
-For Raspberry 3B, 3A+ and 2B v1.2, to enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
-
-For Raspberry 4, make sure to update the bootloader to a stable release
-supporting USB mass storage boot (see
-[bcm2711_bootloader_config.md](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711_bootloader_config.md#usbmassstorageboot). If no SD card is used add `sd_poll_once=on` to `dtparam` in `config.txt` (comma separated). This gets rid of `mmc0: timeout waiting for hardware interrupt` kernel errors.
+USB mass storage boot is available on Raspberry Pi 3B, 3B+, 3A+, and 2B v1.2.
+To enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
 
 For more information see [RaspberryPi](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/msd.md).
 

Documentation/configuration.md

@@ -59,4 +59,4 @@ FallbackNTP=0.pool.ntp.org 1.pool.ntp.org 2.pool.ntp.org 3.pool.ntp.org
 [systemd-modules]: https://www.freedesktop.org/software/systemd/man/modules-load.d.html
 [network.md]: network.md
 [hassos-release]: https://github.com/home-assistant/hassos/releases/
-[debug-homeassistant]: https://developers.home-assistant.io/docs/operating-system/debugging
+[debug-homeassistant]: https://developers.home-assistant.io/docs/en/hassio_debugging.html

Documentation/deployment.md

@@ -2,8 +2,8 @@
 
 We provide 3 different types of release builds:
 
-- development (dev)
-- staging (beta)
+- development (beta/dev)
+- staging (rc)
 - production (stable)
 
 ## Versioning
@@ -15,7 +15,7 @@ The development number they will be bump for the stable release version and the
 
 The branch `dev` ist the actual development branch and from there we never make a release. The `master` branch contains the development version and from there we build a beta release.
 
-If we create a new productive/staging release, we create a new branch `rel-{MAJOR}`. They will be used for the whole cycle of this release.
+If we create a new productive release, we create a new branch `rel-{MAJOR}`. They will be used for the whole cycle of this release.
 
 ## Upload release files
 

Documentation/kernel.md

@@ -5,14 +5,14 @@ Default Kernel tree: 5.4
 
 | Board | Version |
 |-------|---------|
-| Open Virtual Applicance | 5.4.53 |
+| Open Virtual Applicance | 5.4.50 |
 | Raspberry Pi | 4.19.127 |
 | Raspberry Pi 0-W | 4.19.127 |
 | Raspberry Pi 2 | 4.19.127 |
 | Raspberry Pi 3 | 4.19.127 |
 | Raspberry Pi 4 | 4.19.127 |
-| Tinker Board | 5.4.53 |
-| Odroid-C2 | 5.7.10 |
-| Odroid-N2 | 5.7.10 |
-| Odroid-XU4 | 5.7.10 |
-| Intel NUC | 5.4.53 |
+| Tinker Board | 5.4.50 |
+| Odroid-C2 | 5.7.7 |
+| Odroid-N2 | 5.7.7 |
+| Odroid-XU4 | 5.7.7 |
+| Intel NUC | 5.4.50 |

Documentation/network.md

@@ -148,6 +148,6 @@ If you now view the default connection `cat /etc/NetworkManager/system-connectio
 
 Doing a `nmcli con reload` does not always work, so restart the virtual machine or the physical system.
 
-[nm-manual]: https://developer.gnome.org/NetworkManager/stable/NetworkManager.conf.html
+[nm-manual]: https://developer.gnome.org/NetworkManager/stable/nm-settings.html
 [configuration-usb]: configuration.md
 [uuid]: https://www.uuidgenerator.net/

Documentation/partition.md

@@ -1,6 +1,6 @@
 # Partition
 
-The partition layout is a bit different than for regular setups. We prefer GPT, if possible. With SoCs which don't support GPT, we use the hybrid GPT. For more details about this topic, please refer to the [development](development.md) documentation.
+The partition layout is a bit different than for regular setups. We prefer GPT, if possible. With SoCs which don't support GPT, we use the hybrid GPT. For more details about this topic, please refer to the [development](development.mnd) documentation.
 
 The system is designed to have as less as possible write operations on the storage media. Which means that we have basically only write during the OTA update and 5-6 times per week on the overlay part. The data partition is having I/O. This is the reason which is should be run on a different drive.
 
@@ -36,33 +36,12 @@ Sometime the bootloader part can look different because there can be firmware or
 
 ## Data
 
-The data partition is the only partition with real I/O. It will be expanded automatically at boot to the full size of the disk.
+The data partition is the only partition with real I/O. It will be expanded automatic on boot time to the full size of the disk.
 
-
-## Using datactl to move the data partition.
-
-In a Home Assistant OS installation, the data is stored on the `/mnt/data` partition of the SD card. This is the only read+write partition on the SD drive. Using the `datactl` move command, this partition can be moved off of the SD card onto an externally connected drive, leaving the rest of the read-only system on the SD.
-
-The storage capacity of the external drive must be larger than the storage capacity of the existing SD card.
-
-The command needs to be run from the host console by either connecting a keyboard and monitor or making use of the [debug ssh access](https://developers.home-assistant.io/docs/operating-system/debugging/) over port 22222. The command will not work from within an SSH add-on container.
-
-Log in as `root` to get to the Home Assistant CLI and then enter `login` to continue to the host.
-
-Confirm your USB SSD/HD is connected and recognized using `fdisk -l`.
-
-It is recommended to use fdisk to remove the existing partition(s) before proceeding.
-
-- Type `fdisk /dev/XXX` (replacing XXX with your drive)
-- Type `d` to delete a partition.
-- Continue if needed, then write the changes.
-
-Creating a new partition is not necessary.
-
-With the drive now prepared, use the below command (again, replacing XXX with your drive)
+This partition can be offloaded to a different drive with the utility:
 
 ```sh
 $ datactl move /dev/xxx
 ```
 
-Hit any key to continue, and then the move will happen after the next reboot. Once complete, the external drive will be owned and used by the system.
+On next boot, the partition will be moved to the new drive. The drive needs to be bigger as the old one and we own the full new drive.

buildroot-external/Config.in

@@ -5,4 +5,3 @@ source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-bcm43xx/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-rtl8723/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/hardkernel-boot/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/qemu-guest-agent/Config.in"
-source "$BR2_EXTERNAL_HASSOS_PATH/package/intel-e1000e/Config.in"

buildroot-external/board/asus/tinker/patches/linux/2007-drivers-wifi-ath9k-reverse-do-not-use-bulk-on-EP3-and-EP4.patch

@@ -43,8 +43,8 @@ diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath
  
  resubmit:
 @@ -909,11 +909,11 @@
- 		rx_buf->hif_dev = hif_dev;
- 		rx_buf->skb = skb;
+ 			goto err_skb;
+ 		}
  
 +		usb_fill_bulk_urb(urb, hif_dev->udev,
 +				  usb_rcvbulkpipe(hif_dev->udev,
@@ -53,7 +53,7 @@ diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath
  						  USB_REG_IN_PIPE),
  				  skb->data, MAX_REG_IN_BUF_SIZE,
 +				  ath9k_hif_usb_reg_in_cb, skb);
--				  ath9k_hif_usb_reg_in_cb, rx_buf, 1);
+-				  ath9k_hif_usb_reg_in_cb, skb, 1);
  
  		/* Anchor URB */
  		usb_anchor_urb(urb, &hif_dev->reg_in_submitted);

buildroot-external/board/hardkernel/odroid-c2/boot-env.txt

@@ -0,0 +1,131 @@
+
+
+# Custom modeline!
+# To use custom modeline you need to disable all the below resolutions
+# and setup your own!
+# For more information check our wiki:
+# http://odroid.com/dokuwiki/doku.php?id=en:c2_hdmi_autosetting
+# Example below:
+#m=custombuilt
+#modeline=1920,1200,154000,74040,60,1920,1968,2000,2080,1200,1202,1208,1235,1,0,1
+
+# 480 Lines (720x480)
+#m=480i60hz
+#m=480i_rpt
+#m=480p60hz
+#m=480p_rpt
+
+# 576 Lines (720x576)
+#m=576i50hz
+#m=576i_rpt
+#m=576p50hz
+#m=576p_rpt
+
+# 720 Lines (1280x720)
+#m=720p50hz
+#m=720p60hz
+
+# 1080 Lines (1920x1080)
+#m=1080i60hz
+m=1080p60hz
+#m=1080i50hz
+#m=1080p50hz
+#m=1080p24hz
+
+# 4K (3840x2160)
+#m=2160p30hz
+#m=2160p25hz
+#m=2160p24hz
+#m=smpte24hz
+#m=2160p50hz
+#m=2160p60hz
+#m=2160p50hz420
+#m=2160p60hz420
+
+### VESA modes ###
+#m=640x480p60hz
+#m=800x480p60hz
+#m=480x800p60hz
+#m=800x600p60hz
+#m=1024x600p60hz
+#m=1024x768p60hz
+#m=1280x800p60hz
+#m=1280x1024p60hz
+#m=1360x768p60hz
+#m=1440x900p60hz
+#m=1600x900p60hz
+#m=1680x1050p60hz
+#m=1600x1200p60hz
+#m=1920x1200p60hz
+#m=2560x1080p60hz
+#m=2560x1440p60hz
+#m=2560x1600p60hz
+#m=3440x1440p60hz
+
+# HDMI BPP Mode
+m_bpp=32
+#m_bpp=24
+#m_bpp=16
+
+# HDMI DVI/VGA modes
+# By default its set to HDMI, if needed change below.
+# Uncomment only a single Line.
+#vout=dvi
+#vout=vga
+
+# HDMI HotPlug Detection control
+# Allows you to force HDMI thinking that the cable is connected.
+# true = HDMI will believe that cable is always connected
+# false = will let board/monitor negotiate the connection status
+#hpd=false
+hpd=true
+
+# Monitor output
+# Controls if HDMI PHY should output anything to the monitor
+monitor_onoff=false
+
+# Server Mode (aka. No Graphics)
+# Setting nographics to 1 will disable all video subsystem
+# This mode is ideal of server type usage. (Saves ~300Mb of RAM)
+nographics=0
+
+# Meson Timer
+# 1 - Meson Timer
+# 0 - Arch Timer
+# Using meson_timer improves the video playback however it breaks KVM (virtualization).
+# Using arch timer allows KVM/Virtualization to work however you'll experience poor video
+mesontimer=1
+
+# UHS (Ultra High Speed) MicroSD mode enable/disable
+disableuhs=false
+
+# MicroSD Card Detection enable/disable
+# Force the MMC controlled to believe that a card is connected.
+mmc_removable=true
+
+# USB Multi WebCam tweak
+# Only enable this if you use it.
+usbmulticam=false
+
+# CPU Frequency / Cores control
+###########################################
+### WARNING!!! WARNING!!! WARNING!!!
+# Before changing anything here please read the wiki entry:
+# http://odroid.com/dokuwiki/doku.php?id=en:c2_set_cpu_freq
+#
+# MAX CPU's
+#maxcpus=1
+#maxcpus=2
+#maxcpus=3
+maxcpus=4
+
+# MAX Frequency
+#max_freq=2016
+#max_freq=1944
+#max_freq=1944
+#max_freq=1920
+#max_freq=1896
+#max_freq=1752
+#max_freq=1680
+#max_freq=1656
+max_freq=1536

buildroot-external/board/hardkernel/odroid-c2/hassos-hook.sh

@@ -8,6 +8,7 @@ function hassos_pre_image() {
     local SPL_IMG="$(path_spl_img)"
 
     cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
+    cp "${BOARD_DIR}/boot-env.txt" "${BOOT_DATA}/config.txt"
     cp "${BINARIES_DIR}/meson-gxbb-odroidc2.dtb" "${BOOT_DATA}/meson-gxbb-odroidc2.dtb"
 
     echo "console=tty0 console=ttyAML0,115200n8" > "${BOOT_DATA}/cmdline.txt"

buildroot-external/board/hardkernel/odroid-c2/uboot-boot.ush

@@ -23,7 +23,8 @@ if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
 fi
 
 # Board bootargs
-setenv bootargs_odroidc2 ""
+if test "${m}" = "custombuilt"; then setenv cmode "modeline=${modeline}"; fi
+setenv bootargs_odroidc2 "no_console_suspend hdmimode=${m} ${cmode} m_bpp=${m_bpp} vout=${vout} net.ifnames=0 elevator=noop disablehpd=${hpd} max_freq=${max_freq} maxcpus=${maxcpus} monitor_onoff=${monitor_onoff} disableuhs=${disableuhs} mmc_removable=${mmc_removable} usbmulticam=${usbmulticam}"
 
 # HassOS bootargs
 setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor systemd.machine_id=${MACHINE_ID} cgroup_enable=memory"

buildroot-external/board/hardkernel/odroid-n2/boot-env.txt

@@ -0,0 +1,84 @@
+
+
+# Custom modeline!
+# To use custom modeline you need to disable all the below resolutions
+# and setup your own!
+# For more information check our wiki:
+# https://wiki.odroid.com/odroid-n2/application_note/software/set_display_mode
+
+# HDMI Mode
+# Resolution Configuration
+#    Symbol             | Resolution
+# ----------------------+-------------
+#    "480x320p60hz"     | 480x320 Progressive 60Hz
+#    "480p60hz"         | 720x480 Progressive 60Hz
+#    "576p50hz"         | 720x576 Progressive 50Hz
+#    "720p60hz"         | 1280x720 Progressive 60Hz
+#    "720p50hz"         | 1280x720 Progressive 50Hz
+#    "1080p60hz"        | 1920x1080 Progressive 60Hz
+#    "1080p50hz"        | 1920x1080 Progressive 50Hz
+#    "1080p30hz"        | 1920x1080 Progressive 30Hz
+#    "1080p24hz"        | 1920x1080 Progressive 24Hz
+#    "1080i60hz"        | 1920x1080 Interlaced 60Hz
+#    "1080i50hz"        | 1920x1080 Interlaced 50Hz
+#    "2160p60hz"        | 3840x2160 Progressive 60Hz
+#    "2160p50hz"        | 3840x2160 Progressive 50Hz
+#    "2160p30hz"        | 3840x2160 Progressive 30Hz
+#    "2160p25hz"        | 3840x2160 Progressive 25Hz
+#    "2160p24hz"        | 3840x2160 Progressive 24Hz
+#    "smpte24hz"        | 3840x2160 Progressive 24Hz SMPTE
+#    "2160p60hz420"     | 3840x2160 Progressive 60Hz YCbCr 4:2:0
+#    "2160p50hz420"     | 3840x2160 Progressive 50Hz YCbCr 4:2:0
+#    "640x480p60hz"     | 640x480 Progressive 60Hz
+#    "800x480p60hz"     | 800x480 Progressive 60Hz
+#    "800x600p60hz"     | 800x600 Progressive 60Hz
+#    "1024x600p60hz"    | 1024x600 Progressive 60Hz
+#    "1024x768p60hz"    | 1024x768 Progressive 60Hz
+#    "1280x800p60hz"    | 1280x800 Progressive 60Hz
+#    "1280x1024p60hz"   | 1280x1024 Progressive 60Hz
+#    "1360x768p60hz"    | 1360x768 Progressive 60Hz
+#    "1440x900p60hz"    | 1440x900 Progressive 60Hz
+#    "1600x900p60hz"    | 1600x900 Progressive 60Hz
+#    "1600x1200p60hz"   | 1600x1200 Progressive 60Hz
+#    "1680x1050p60hz"   | 1680x1050 Progressive 60Hz
+#    "1920x1200p60hz"   | 1920x1200 Progressive 60Hz
+#    "2560x1080p60hz"   | 2560x1080 Progressive 60Hz
+#    "2560x1440p60hz"   | 2560x1440 Progressive 60Hz
+#    "2560x1600p60hz"   | 2560x1600 Progressive 60Hz
+#    "3440x1440p60hz"   | 3440x1440 Progressive 60Hz
+hdmimode=1080p60hz
+ 
+# Overscan percentage
+# This value scales down the actual screen size by the percentage below
+# valid range is 80 to 100
+overscan=100
+ 
+### voutmode : hdmi or dvi
+#voutmode=dvi
+voutmode=hdmi
+ 
+# HPD enable/disable option
+disablehpd="false"
+ 
+# max cpu frequency for big core, A73 in MHz unit
+# 1.8 GHz, default value
+#max_freq_a73=2004  # 2.004 GHz
+#max_freq_a73=1908  # 1.908 GHz
+#max_freq_a73=1704  # 1.704 GHz
+max_freq_a73=1800
+ 
+# max cpu frequency for little core, A53 in MHz unit
+# 1.896 GHz, default value
+#max_freq_a53=1992  # 1.992 GHz
+#max_freq_a53=1704  # 1.704 GHz
+max_freq_a53=1896
+ 
+ 
+# max cpu-cores
+# Note:
+# CPU's 0 and 1 are the A53 (small cores)
+# CPU's 2 to 5 are the A73 (big cores)
+# Lowering this value disables only the bigger cores (the last cores).
+#maxcpus=4
+#maxcpus=5
+maxcpus=6

buildroot-external/board/hardkernel/odroid-n2/hassos-hook.sh

@@ -7,6 +7,7 @@ function hassos_pre_image() {
     local SPL_IMG="$(path_spl_img)"
 
     cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
+    cp "${BOARD_DIR}/boot-env.txt" "${BOOT_DATA}/config.txt"
     cp "${BINARIES_DIR}/meson-g12b-odroid-n2.dtb" "${BOOT_DATA}/meson-g12b-odroid-n2.dtb"
 
     echo "console=tty0 console=ttyAML0,115200n8" > "${BOOT_DATA}/cmdline.txt"

buildroot-external/board/hardkernel/odroid-n2/uboot-boot.ush

@@ -23,7 +23,10 @@ if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
 fi
 
 # Board bootargs
-setenv bootargs_odroidn2 ""
+if test "${hdmimode}" = "custombuilt"; then setenv cmode "modeline=${modeline}"; fi
+ 
+# Boot Args
+setenv bootargs_odroidn2 "clk_ignore_unused hdmimode=${hdmimode} cvbsmode=576cvbs max_freq_a53=${max_freq_a53} max_freq_a73=${max_freq_a73} maxcpus=${maxcpus} ${cmode} voutmode=${voutmode} disablehpd=${disablehpd} overscan=${overscan}"
 
 # HassOS bootargs
 setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor systemd.machine_id=${MACHINE_ID} cgroup_enable=memory"

buildroot-external/board/hardkernel/odroid-xu4/boot-env.txt

@@ -0,0 +1,40 @@
+
+macaddr=00:1e:06:61:7a:39
+vout=hdmi
+# - DVI Mode (disables sound over HDMI as per DVI compat)
+# vout=dvi
+
+# --- HDMI CEC Configuration ---
+# ------------------------------------------
+cecenable=false
+# set to true to enable HDMI CEC
+
+# Enable/Disable ODROID-VU7 Touchsreen
+disable_vu7=false
+
+# DRAM Frequency
+# Sets the LPDDR3 memory frequency
+# Supported values: 933 825 728 633 (MHZ)
+ddr_freq=825
+
+# External watchdog board enable
+external_watchdog=false
+# debounce time set to 3 ~ 10 sec, default 3 sec
+external_watchdog_debounce=3
+
+
+#------------------------------------------------------------------------------
+#
+# HDMI Hot Plug detection
+#
+#------------------------------------------------------------------------------
+#
+# Forces the HDMI subsystem to ignore the check if the cable is connected or
+# not.
+# false : disable the detection and force it as connected.
+# true : let cable, board and monitor decide the connection status.
+#
+# default: true
+#
+#------------------------------------------------------------------------------
+HPD=true

buildroot-external/board/hardkernel/odroid-xu4/hassos-hook.sh

@@ -10,6 +10,7 @@ function hassos_pre_image() {
     local spl_img="$(path_spl_img)"
 
     cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
+    cp "${BOARD_DIR}/boot-env.txt" "${BOOT_DATA}/config.txt"
     cp "${BINARIES_DIR}/exynos5422-odroidxu4.dtb" "${BOOT_DATA}/exynos5422-odroidxu4.dtb"
 
     echo "console=tty1 console=ttySAC2,115200" > "${BOOT_DATA}/cmdline.txt"

buildroot-external/board/hardkernel/odroid-xu4/uboot-boot.ush

@@ -25,7 +25,12 @@ if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
 fi
 
 # Board bootargs
-setenv bootargs_odroidxu4 ""
+setenv hdmi_phy_control "HPD=${HPD} vout=${vout}"
+if test "${cecenable}" = "false"; then fdt rm /cec@101B0000; fi
+if test "${disable_vu7}" = "false"; then setenv hid_quirks "usbhid.quirks=0x0eef:0x0005:0x0004"; fi
+if test "${external_watchdog}" = "true"; then setenv external_watchdog "external_watchdog=${external_watchdog} external_watchdog_debounce=${external_watchdog_debounce}"; fi
+
+setenv bootargs_odroidxu4 "${videoconfig} ${hdmi_phy_control} ${hid_quirks} smsc95xx.macaddr=${macaddr} ${external_watchdog}"
 
 # HassOS bootargs
 setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor systemd.machine_id=${MACHINE_ID} cgroup_enable=memory"

buildroot-external/board/hardkernel/patches/linux/0001-mmc-meson-gx-limit-segments-to-1-when-dram-access-qu.patch

@@ -0,0 +1,46 @@
+From bbafdffacb88adb701ca2f37f3169df4c9ac3824 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Mon, 8 Jun 2020 10:44:58 +0200
+Subject: [PATCH 1/8] mmc: meson-gx: limit segments to 1 when dram-access-quirk
+ is needed
+
+The actual max_segs computation leads to failure while using the broadcom
+sdio brcmfmac/bcmsdh driver, since the driver tries to make usage of scatter
+gather.
+
+But with the dram-access-quirk we use a 1,5K SRAM bounce buffer, and the
+max_segs current value of 3 leads to max transfers to 4,5k, which doesn't work.
+
+This patch sets max_segs to 1 to better describe the hardware limitation,
+and fix the SDIO functionnality with the brcmfmac/bcmsdh driver on Amlogic
+G12A/G12B SoCs on boards like SEI510 or Khadas VIM3.
+
+Reported-by: Art Nikpal <art@khadas.com>
+Reported-by: Christian Hewitt <christianshewitt@gmail.com>
+Fixes: acdc8e71d9bb ("mmc: meson-gx: add dram-access-quirk")
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/mmc/host/meson-gx-mmc.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
+index 35400cf2a2e4..cfaf8e7e22ec 100644
+--- a/drivers/mmc/host/meson-gx-mmc.c
++++ b/drivers/mmc/host/meson-gx-mmc.c
+@@ -1143,9 +1143,11 @@ static int meson_mmc_probe(struct platform_device *pdev)
+ 
+ 	mmc->caps |= MMC_CAP_CMD23;
+ 	if (host->dram_access_quirk) {
++		/* Limit segments to 1 due to low available sram memory */
++		mmc->max_segs = 1;
+ 		/* Limit to the available sram memory */
+-		mmc->max_segs = SD_EMMC_SRAM_DATA_BUF_LEN / mmc->max_blk_size;
+-		mmc->max_blk_count = mmc->max_segs;
++		mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
++				     mmc->max_blk_size;
+ 	} else {
+ 		mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
+ 		mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
+-- 
+2.17.1
+

buildroot-external/board/intel/nuc/kernel.config

@@ -4,8 +4,6 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_BLK_DEV_NVME=y
 
-# CONFIG_E1000E is not set
-
 CONFIG_IGB=y
 
 CONFIG_IWLWIFI=m
@@ -15,3 +13,13 @@ CONFIG_DRM_I915=m
 CONFIG_DRM_I915_CAPTURE_ERROR=y
 CONFIG_DRM_I915_COMPRESS_ERROR=y
 CONFIG_DRM_I915_USERPTR=y
+
+CONFIG_SND_HDA=y
+CONFIG_SND_HDA_CORE=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_I915=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_CODEC_HDMI=m

buildroot-external/board/raspberrypi/patches/linux/0001-dt-bindings-reset-Add-a-binding-for-the-RPi-Firmware.patch

@@ -1,41 +0,0 @@
-From a9f92163e6c07e5c6f57f00f4931098e0e1ee826 Mon Sep 17 00:00:00 2001
-Message-Id: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:18:37 +0200
-Subject: [PATCH 1/4] dt-bindings: reset: Add a binding for the RPi Firmware
- reset controller
-
-The firmware running on the RPi VideoCore can be used to reset and
-initialize HW controlled by the firmware.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-[backport for RPi 4.19 kernel]
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- .../dt-bindings/reset/raspberrypi,firmware-reset.h  | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
- create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
-
-diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-new file mode 100644
-index 000000000000..1a4f4c792723
---- /dev/null
-+++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (c) 2020 Nicolas Saenz Julienne
-+ * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+
-+#define RASPBERRYPI_FIRMWARE_RESET_ID_USB	0
-+#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS	1
-+
-+#endif
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/linux/0002-ARM-dts-bcm2711-Add-firmware-usb-reset-node.patch

@@ -1,38 +0,0 @@
-From b15414057bc9a023fc865242f499807d82933e58 Mon Sep 17 00:00:00 2001
-Message-Id: <b15414057bc9a023fc865242f499807d82933e58.1595152741.git.stefan@agner.ch>
-In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:18:39 +0200
-Subject: [PATCH 2/4] ARM: dts: bcm2711: Add firmware usb reset node
-
-Now that the reset driver exposing Raspberry Pi 4's firmware based USB
-reset routine is available, let's add the device tree node exposing it.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-[backport for RPi 4.19 kernel]
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-index 42259dbf3919..ec0b3bb64de8 100644
---- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-@@ -80,6 +80,11 @@
- 				  "";
- 		status = "okay";
- 	};
-+
-+	reset: reset {
-+		compatible = "raspberrypi,firmware-reset";
-+		#reset-cells = <1>;
-+	};
- };
- 
- &uart0 {
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/linux/0003-ARM-dts-bcm2711-Add-reset-controller-to-xHCI-node.patch

@@ -1,58 +0,0 @@
-From 08558575c0f3d1437994590ad418d6c2cf18d96b Mon Sep 17 00:00:00 2001
-Message-Id: <08558575c0f3d1437994590ad418d6c2cf18d96b.1595152741.git.stefan@agner.ch>
-In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:18:40 +0200
-Subject: [PATCH 3/4] ARM: dts: bcm2711: Add reset controller to xHCI node
-
-The chip is hardwired to the board's PCIe bus and needs to be properly
-setup trough a firmware routine after a PCI fundamental reset. Pass the
-reset controller phandle that takes care of triggering the
-initialization to the relevant PCI device.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-[backport for RPi 4.19 kernel]
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-index ec0b3bb64de8..2c6aa1933600 100644
---- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
-@@ -4,6 +4,8 @@
- #include "bcm2711-rpi.dtsi"
- #include "bcm283x-rpi-csi1-2lane.dtsi"
- 
-+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-+
- / {
- 	compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
- 	model = "Raspberry Pi 4 Model B";
-@@ -87,6 +89,21 @@
- 	};
- };
- 
-+&pcie_0 {
-+	pci@1,0 {
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		reg = <0 0 0 0 0>;
-+
-+		usb@1,0 {
-+			reg = <0x10000 0 0 0 0>;
-+			resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
-+		};
-+	};
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_pins &bt_pins>;
--- 
-2.27.0
-

buildroot-external/board/raspberrypi/patches/linux/0004-ARM-dts-bcm2838-add-upstream-property-to-enable-PCIe.patch

@@ -1,44 +0,0 @@
-From dcfb930f9c271ad303a888ce94227d2d78974e39 Mon Sep 17 00:00:00 2001
-Message-Id: <dcfb930f9c271ad303a888ce94227d2d78974e39.1595152741.git.stefan@agner.ch>
-In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
-From: Stefan Agner <stefan@agner.ch>
-Date: Sun, 19 Jul 2020 11:49:45 +0200
-Subject: [PATCH 4/4] ARM: dts: bcm2838: add upstream property to enable PCIe
- spread-spectrum
-
-Add the upstream device tree property brcm,enable-ssc to enable
-spread-spectrum for PCIe. This is used by the upstream U-Boot.
-
-Signed-off-by: Stefan Agner <stefan@agner.ch>
----
- arch/arm/boot/dts/bcm2838.dtsi | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi
-index 36d250d7053b..d6cc876bc720 100644
---- a/arch/arm/boot/dts/bcm2838.dtsi
-+++ b/arch/arm/boot/dts/bcm2838.dtsi
-@@ -353,11 +353,14 @@
- 			 */
- 			ranges = <0x02000000 0x0 0xf8000000  0x6 0x00000000
- 				  0x0 0x04000000>;
--			/* Map inbound accesses from pci:0x0_00000000..ffffffff
--			 * to scb:0x0_00000000-ffffffff
--			 */
--			dma-ranges = <0x02000000 0x0 0x00000000  0x0 0x00000000
--				      0x1 0x00000000>;
-+                        /*
-+                         * The wrapper around the PCIe block has a bug
-+                         * preventing it from accessing beyond the first 3GB of
-+                         * memory.
-+                         */
-+                        dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
-+                                      0x0 0xc0000000>;
-+			brcm,enable-ssc;
- 			status = "okay";
- 		};
- 
--- 
-2.27.0
-

buildroot-external/configs/intel_nuc_defconfig

@@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.53"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.50"
 BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -104,4 +104,3 @@ BR2_PACKAGE_HOST_RAUC=y
 BR2_PACKAGE_HASSIO=y
 BR2_PACKAGE_HASSIO_ARCH="amd64"
 BR2_PACKAGE_APPARMOR=y
-BR2_PACKAGE_INTEL_E1000E=y

buildroot-external/configs/odroid_c2_defconfig

@@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.10"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.7"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"

buildroot-external/configs/odroid_n2_defconfig

@@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.10"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.7"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"

buildroot-external/configs/odroid_xu4_defconfig

@@ -23,7 +23,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.10"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.7.7"
 BR2_LINUX_KERNEL_DEFCONFIG="exynos"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/ova_defconfig

@@ -23,7 +23,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.53"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.50"
 BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/rpi0_w_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi0-w $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/rpi2_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi2 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2709"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/rpi3_64_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi3-64 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi3"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/rpi3_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi3 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2709"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/rpi4_64_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi4-64 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2711"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -87,7 +87,7 @@ BR2_TARGET_ROOTFS_SQUASHFS4_LZ4=y
 BR2_TARGET_UBOOT=y
 BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
 BR2_TARGET_UBOOT_CUSTOM_VERSION=y
-BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.07"
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.01"
 BR2_TARGET_UBOOT_BOARD_DEFCONFIG="rpi_4"
 BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/bootloader/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/uboot.config"
 BR2_TARGET_UBOOT_BOOT_SCRIPT=y

buildroot-external/configs/rpi4_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi4 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2711"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/rpi_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/a03605b08ae73107100c72dc92c92adf0dde3e42.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y

buildroot-external/configs/tinker_defconfig

@@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker $(BR2_EXTERNAL_HASSOS_PATH)/board/asus/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.53"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.50"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/kernel.config"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"

buildroot-external/kernel/device-support.config

@@ -13,6 +13,7 @@ CONFIG_USB_ACM=m
 CONFIG_USB_USBNET=m
 
 CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_SND_USB_AUDIO=m
 
 CONFIG_BT=y
 CONFIG_BT_BREDR=y
@@ -140,15 +141,3 @@ CONFIG_VIDEO_EM28XX_V4L2=m
 CONFIG_VIDEO_EM28XX_ALSA=m
 CONFIG_VIDEO_EM28XX_DVB=m
 CONFIG_VIDEO_EM28XX_RC=m
-
-# Audio devices (USB/PCI)
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_HDA=y
-CONFIG_SND_HDA_CORE=y
-CONFIG_SND_HDA_GENERIC=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_I915=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m

buildroot-external/meta

@@ -1,7 +1,7 @@
-VERSION_MAJOR=5
-VERSION_BUILD=0
+VERSION_MAJOR=4
+VERSION_BUILD=11
 
 HASSOS_NAME="HassOS"
 HASSOS_ID="hassos"
 
-DEPLOYMENT="development"
+DEPLOYMENT="production"

buildroot-external/package/intel-e1000e/Config.in

@@ -1,10 +0,0 @@
-comment "e1000e needs a Linux kernel to be built"
-	depends on !BR2_LINUX_KERNEL
-
-config BR2_PACKAGE_INTEL_E1000E
-	bool "Intel Network Adapter Driver for PCIe"
-	depends on BR2_LINUX_KERNEL
-	help
-	  Install Intel Network Adapter Driver for PCIe (external module)
-
-	  https://downloadcenter.intel.com/download/15817/Intel-Network-Adapter-Driver-for-PCIe-Intel-Gigabit-Ethernet-Network-Connections-Under-Linux-

buildroot-external/package/intel-e1000e/intel-e1000e.hash

@@ -1,5 +0,0 @@
-# from https://downloadcenter.intel.com/download/15817/Intel-Network-Adapter-Driver-for-PCIe-Intel-Gigabit-Ethernet-Network-Connections-Under-Linux-
-md5  711dc0ada83947b0e22e53699d4fa1ac  e1000e-3.8.4.tar.gz
-
-# Locally calculated
-sha256  4441515302f901e32f29b9b4702239f176d3c02c3b9a697009f93012205e0de1  e1000e-3.8.4.tar.gz

buildroot-external/package/intel-e1000e/intel-e1000e.mk

@@ -1,20 +0,0 @@
-################################################################################
-#
-# Intel Network Adapter Driver for PCIe
-#
-################################################################################
-
-INTEL_E1000E_VERSION = 3.8.4
-INTEL_E1000E_LICENSE = GPL-2.0
-INTEL_E1000E_LICENSE_FILES = COPYING
-INTEL_E1000E_SOURCE = e1000e-$(INTEL_E1000E_VERSION).tar.gz
-INTEL_E1000E_SITE = https://downloads.sourceforge.net/project/e1000/e1000e%20stable/$(INTEL_E1000E_VERSION)
-INTEL_E1000E_MODULE_SUBDIRS = src
-
-INTEL_E1000E_MODULE_MAKE_OPTS = \
-	CONFIG_E1000E=m \
-	KVER=$(LINUX_VERSION_PROBED) \
-	KSRC=$(LINUX_DIR)
-
-$(eval $(kernel-module))
-$(eval $(generic-package))

buildroot-external/patches/uboot/2020.07/0001-CMD-read-string-from-fileinto-env.patch

@@ -1,96 +0,0 @@
-From 040a141f84f2f84bf8be18f85b4cdb34bf066df0 Mon Sep 17 00:00:00 2001
-Message-Id: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595086593.git.stefan@agner.ch>
-From: Pascal Vizeli <pvizeli@syshack.ch>
-Date: Sun, 5 Aug 2018 20:43:03 +0000
-Subject: [PATCH 1/1] CMD: read string from fileinto env
-
-Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
----
- cmd/Kconfig   |  5 +++++
- cmd/Makefile  |  1 +
- cmd/fileenv.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 51 insertions(+)
- create mode 100644 cmd/fileenv.c
-
-diff --git a/cmd/Kconfig b/cmd/Kconfig
-index 192b3b262f..b44cd64215 100644
---- a/cmd/Kconfig
-+++ b/cmd/Kconfig
-@@ -1388,6 +1388,11 @@ config CMD_SETEXPR
- 	  Also supports loading the value at a memory location into a variable.
- 	  If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
- 
-+config CMD_FILEENV
-+	bool "fileenv"
-+	help
-+	   Read a file into memory and store it to env.
-+
- endmenu
- 
- menu "Android support commands"
-diff --git a/cmd/Makefile b/cmd/Makefile
-index 974ad48b0a..287887e97f 100644
---- a/cmd/Makefile
-+++ b/cmd/Makefile
-@@ -128,6 +128,7 @@ obj-$(CONFIG_CMD_SF) += sf.o
- obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o
- obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
- obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
-+obj-$(CONFIG_CMD_FILEENV) += fileenv.o
- obj-$(CONFIG_CMD_SPI) += spi.o
- obj-$(CONFIG_CMD_STRINGS) += strings.o
- obj-$(CONFIG_CMD_SMC) += smccc.o
-diff --git a/cmd/fileenv.c b/cmd/fileenv.c
-new file mode 100644
-index 0000000000..af24d22d0e
---- /dev/null
-+++ b/cmd/fileenv.c
-@@ -0,0 +1,45 @@
-+#include <config.h>
-+#include <common.h>
-+#include <command.h>
-+#include <linux/ctype.h>
-+
-+static char *fs_argv[5];
-+
-+int do_fileenv(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
-+{
-+	if (argc < 6)
-+		return CMD_RET_USAGE;
-+
-+	fs_argv[0] = "fatload";
-+	fs_argv[1] = argv[1];
-+	fs_argv[2] = argv[2];
-+	fs_argv[3] = argv[3];
-+	fs_argv[4] = argv[4];
-+
-+	if (do_fat_fsload(cmdtp, 0, 5, fs_argv) != 0)
-+		return 1;
-+
-+	char *addr = (char *)simple_strtoul(argv[3], NULL, 16);
-+	size_t size = env_get_hex("filesize", 0);
-+
-+	// Prepare string
-+	addr[size] = 0x00;
-+	char *s = addr;
-+	while(*s != 0x00) {
-+		if (isprint(*s)) {
-+			s++;
-+		}
-+		else {
-+			*s = 0x00;
-+		}
-+	}
-+
-+	return env_set(argv[5], addr);
-+}
-+
-+U_BOOT_CMD(
-+	fileenv, 6, 0, do_fileenv,
-+	"Read file and store it into env.",
-+	"<interface> <dev:part> <addr> <filename> <envname>\n"
-+	"    - Read file from fat32 and store it as env."
-+);
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0002-usb-xhci-Add-missing-cache-flush-in-the-scratchpad-a.patch

@@ -1,41 +0,0 @@
-From b39cd5ba642ddba46268e8d873b952604844c047 Mon Sep 17 00:00:00 2001
-Message-Id: <b39cd5ba642ddba46268e8d873b952604844c047.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:51 +0200
-Subject: [PATCH 02/20] usb: xhci: Add missing cache flush in the scratchpad
- array initialization
-
-In current code there is no cache flush after initializing the scratchpad
-buffer array with the scratchpad buffer pointers. This leads to a failure
-of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
-controller + VL805 USB hub) - the very first TRB transfer on the command
-ring fails and there is a timeout while waiting for the command completion
-event. After adding the missing cache flush everything seems to be working
-as expected.
-
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/usb/host/xhci-mem.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
-index 2d968aafb0..f446520528 100644
---- a/drivers/usb/host/xhci-mem.c
-+++ b/drivers/usb/host/xhci-mem.c
-@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
- 		scratchpad->sp_array[i] = cpu_to_le64(ptr);
- 	}
- 
-+	xhci_flush_cache((uintptr_t)scratchpad->sp_array,
-+			 sizeof(u64) * num_sp);
-+
- 	return 0;
- 
- fail_sp3:
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0003-usb-xhci-Use-only-32-bit-accesses-in-xhci_writeq-xhc.patch

@@ -1,69 +0,0 @@
-From 71343be3dd8d7f04cea781c8369aa77a36ae7123 Mon Sep 17 00:00:00 2001
-Message-Id: <71343be3dd8d7f04cea781c8369aa77a36ae7123.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:52 +0200
-Subject: [PATCH 03/20] usb: xhci: Use only 32-bit accesses in
- xhci_writeq/xhci_readq
-
-There might be hardware configurations where 64-bit data accesses
-to XHCI registers are not supported properly.  This patch removes
-the readq/writeq so always two 32-bit accesses are used to read/write
-64-bit XHCI registers, similarly as it is done in Linux kernel.
-
-This patch fixes operation of the XHCI controller on RPI4 Broadcom
-BCM2711 SoC based board, where the VL805 USB XHCI controller is
-connected to the PCIe Root Complex, which is attached to the system
-through the SCB bridge.
-
-Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
-the 64-bit wide register accesses initiated by the CPU are not properly
-translated to a sequence of 32-bit PCIe accesses.
-xhci_readq(), for example, always returns same value in upper and lower
-32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
-
-Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- include/usb/xhci.h | 8 --------
- 1 file changed, 8 deletions(-)
-
-diff --git a/include/usb/xhci.h b/include/usb/xhci.h
-index 20e4a21066..1170c0ac69 100644
---- a/include/usb/xhci.h
-+++ b/include/usb/xhci.h
-@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
-  */
- static inline u64 xhci_readq(__le64 volatile *regs)
- {
--#if BITS_PER_LONG == 64
--	return readq(regs);
--#else
- 	__u32 *ptr = (__u32 *)regs;
- 	u64 val_lo = readl(ptr);
- 	u64 val_hi = readl(ptr + 1);
- 	return val_lo + (val_hi << 32);
--#endif
- }
- 
- static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
- {
--#if BITS_PER_LONG == 64
--	writeq(val, regs);
--#else
- 	__u32 *ptr = (__u32 *)regs;
- 	u32 val_lo = lower_32_bits(val);
- 	/* FIXME */
- 	u32 val_hi = upper_32_bits(val);
- 	writel(val_lo, ptr);
- 	writel(val_hi, ptr + 1);
--#endif
- }
- 
- int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0004-pci-Move-some-PCIe-register-offset-definitions-to-a-.patch

@@ -1,85 +0,0 @@
-From 82024c95e4d00b555f93d93b9f706c4d995ab302 Mon Sep 17 00:00:00 2001
-Message-Id: <82024c95e4d00b555f93d93b9f706c4d995ab302.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:53 +0200
-Subject: [PATCH 04/20] pci: Move some PCIe register offset definitions to a
- common header
-
-Some PCI Express register offsets are currently defined in multiple
-drivers, move them to a common header to avoid re-definitions and
-as a pre-requisite for adding new PCIe driver.
-While at it replace some spaces with tabs.
-
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/pci/pci-rcar-gen3.c   |  8 --------
- drivers/pci/pcie_intel_fpga.c |  3 ---
- include/pci.h                 | 13 +++++++++++--
- 3 files changed, 11 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
-index df7b37a592..1f51854ccc 100644
---- a/drivers/pci/pci-rcar-gen3.c
-+++ b/drivers/pci/pci-rcar-gen3.c
-@@ -118,14 +118,6 @@
- #define RCAR_PCI_MAX_RESOURCES	4
- #define MAX_NR_INBOUND_MAPS	6
- 
--#define PCI_EXP_FLAGS		2		/* Capabilities register */
--#define PCI_EXP_FLAGS_TYPE	0x00f0		/* Device/Port type */
--#define PCI_EXP_TYPE_ROOT_PORT	0x4		/* Root Port */
--#define PCI_EXP_LNKCAP		12		/* Link Capabilities */
--#define PCI_EXP_LNKCAP_DLLLARC	0x00100000	/* Data Link Layer Link Active Reporting Capable */
--#define PCI_EXP_SLTCAP		20		/* Slot Capabilities */
--#define PCI_EXP_SLTCAP_PSN	0xfff80000	/* Physical Slot Number */
--
- enum {
- 	RCAR_PCI_ACCESS_READ,
- 	RCAR_PCI_ACCESS_WRITE,
-diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
-index aa1903e547..9f102c64c6 100644
---- a/drivers/pci/pcie_intel_fpga.c
-+++ b/drivers/pci/pcie_intel_fpga.c
-@@ -67,9 +67,6 @@
- #define IS_ROOT_PORT(pcie, bdf)				\
- 		((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
- 
--#define PCI_EXP_LNKSTA		18	/* Link Status */
--#define PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
--
- /**
-  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
-  * @bus: Pointer to the PCI bus
-diff --git a/include/pci.h b/include/pci.h
-index 19c9244b94..9cd8564436 100644
---- a/include/pci.h
-+++ b/include/pci.h
-@@ -471,10 +471,19 @@
- #define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
- 
- /* PCI Express capabilities */
-+#define PCI_EXP_FLAGS		2	/* Capabilities register */
-+#define  PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
-+#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
- #define PCI_EXP_DEVCAP		4	/* Device capabilities */
--#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
-+#define  PCI_EXP_DEVCAP_FLR	0x10000000 /* Function Level Reset */
- #define PCI_EXP_DEVCTL		8	/* Device Control */
--#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
-+#define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
-+#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
-+#define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
-+#define PCI_EXP_LNKSTA		18	/* Link Status */
-+#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
-+#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
-+#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
- 
- /* Include the ID list */
- 
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0005-rpi4-shorten-a-mapping-for-the-DRAM.patch

@@ -1,33 +0,0 @@
-From 5dddca0c2ca5de72b74a5fca0d3ea67251add760 Mon Sep 17 00:00:00 2001
-Message-Id: <5dddca0c2ca5de72b74a5fca0d3ea67251add760.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Mon, 25 May 2020 13:39:54 +0200
-Subject: [PATCH 05/20] rpi4: shorten a mapping for the DRAM
-
-Remove the overlap between DRAM and device's IO area.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- arch/arm/mach-bcm283x/init.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
-index f4d00d892d..f9a5209480 100644
---- a/arch/arm/mach-bcm283x/init.c
-+++ b/arch/arm/mach-bcm283x/init.c
-@@ -39,7 +39,7 @@ static struct mm_region bcm2711_mem_map[] = {
- 	{
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
--		.size = 0xfe000000UL,
-+		.size = 0xfc000000UL,
- 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- 			 PTE_BLOCK_INNER_SHARE
- 	}, {
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0006-rpi4-add-a-mapping-for-the-PCIe-XHCI-controller-MMIO.patch

@@ -1,76 +0,0 @@
-From a326f58940f16b2dc3740fd9e87eb485da939ae5 Mon Sep 17 00:00:00 2001
-Message-Id: <a326f58940f16b2dc3740fd9e87eb485da939ae5.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Mon, 25 May 2020 13:39:55 +0200
-Subject: [PATCH 06/20] rpi4: add a mapping for the PCIe XHCI controller MMIO
- registers (ARM 64bit)
-
-Create a non-cacheable mapping for the 0x600000000 physical memory region,
-where MMIO registers for the PCIe XHCI controller are instantiated by the
-PCIe bridge.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++---
- 1 file changed, 15 insertions(+), 3 deletions(-)
-
-diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
-index f9a5209480..cf4c5b245d 100644
---- a/arch/arm/mach-bcm283x/init.c
-+++ b/arch/arm/mach-bcm283x/init.c
-@@ -12,10 +12,15 @@
- #include <dm/device.h>
- #include <fdt_support.h>
- 
-+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS	0x600000000UL
-+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE	0x800000UL
-+
- #ifdef CONFIG_ARM64
- #include <asm/armv8/mmu.h>
- 
--static struct mm_region bcm283x_mem_map[] = {
-+#define MEM_MAP_MAX_ENTRIES (4)
-+
-+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
- 	{
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
-@@ -35,7 +40,7 @@ static struct mm_region bcm283x_mem_map[] = {
- 	}
- };
- 
--static struct mm_region bcm2711_mem_map[] = {
-+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
- 	{
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
-@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
- 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- 			 PTE_BLOCK_NON_SHARE |
- 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+	}, {
-+		.virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
-+		.phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
-+		.size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+			 PTE_BLOCK_NON_SHARE |
-+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
- 	}, {
- 		/* List terminator */
- 		0,
-@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
- {
- 	int i;
- 
--	for (i = 0; i < 2; i++) {
-+	for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
- 		mem_map[i].virt = pd[i].virt;
- 		mem_map[i].phys = pd[i].phys;
- 		mem_map[i].size = pd[i].size;
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0007-linux-bitfield.h-Add-primitives-for-manipulating-bit.patch

@@ -1,85 +0,0 @@
-From 9c761488487ce27517e2a9e425f4ed0777708c53 Mon Sep 17 00:00:00 2001
-Message-Id: <9c761488487ce27517e2a9e425f4ed0777708c53.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 25 May 2020 13:39:56 +0200
-Subject: [PATCH 07/20] linux/bitfield.h: Add primitives for manipulating
- bitfields both in host- and fixed-endian
-
-Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
-an in depth explanation and two fixes from Johannes Berg:
- e7d4a95da86e0 "bitfield: fix *_encode_bits()",
- 37a3862e12382 "bitfield: add u8 helpers".
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-[s.nawrocki: added empty lines between functions and macros]
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
----
- include/linux/bitfield.h | 52 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
-diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
-index 8b9d6fff00..7ad8b088ed 100644
---- a/include/linux/bitfield.h
-+++ b/include/linux/bitfield.h
-@@ -103,4 +103,56 @@
- 		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));	\
- 	})
- 
-+extern void __compiletime_error("value doesn't fit into mask")
-+__field_overflow(void);
-+extern void __compiletime_error("bad bitfield mask")
-+__bad_mask(void);
-+
-+static __always_inline u64 field_multiplier(u64 field)
-+{
-+	if ((field | (field - 1)) & ((field | (field - 1)) + 1))
-+		__bad_mask();
-+	return field & -field;
-+}
-+
-+static __always_inline u64 field_mask(u64 field)
-+{
-+	return field / field_multiplier(field);
-+}
-+
-+#define ____MAKE_OP(type, base, to, from)				\
-+static __always_inline __##type type##_encode_bits(base v, base field)	\
-+{									\
-+	if (__builtin_constant_p(v) && (v & ~field_mask(field)))	\
-+		__field_overflow();					\
-+	return to((v & field_mask(field)) * field_multiplier(field));	\
-+}									\
-+static __always_inline __##type type##_replace_bits(__##type old,	\
-+					base val, base field)		\
-+{									\
-+	return (old & ~to(field)) | type##_encode_bits(val, field);	\
-+}									\
-+static __always_inline void type##p_replace_bits(__##type * p,		\
-+					base val, base field)		\
-+{									\
-+	*p = (*p & ~to(field)) | type##_encode_bits(val, field);	\
-+}									\
-+static __always_inline base type##_get_bits(__##type v, base field)	\
-+{									\
-+	return (from(v) & field) / field_multiplier(field);		\
-+}
-+
-+#define __MAKE_OP(size)							\
-+	____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
-+	____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
-+	____MAKE_OP(u##size, u##size, ,)
-+
-+____MAKE_OP(u8, u8, ,)
-+__MAKE_OP(16)
-+__MAKE_OP(32)
-+__MAKE_OP(64)
-+
-+#undef __MAKE_OP
-+#undef ____MAKE_OP
-+
- #endif
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0008-pci-Add-some-PCI-Express-capability-register-offset-.patch

@@ -1,47 +0,0 @@
-From 376bd33efa69abfc6102eb5a56b700c0f1981cf4 Mon Sep 17 00:00:00 2001
-Message-Id: <376bd33efa69abfc6102eb5a56b700c0f1981cf4.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:57 +0200
-Subject: [PATCH 08/20] pci: Add some PCI Express capability register offset
- definitions
-
-Add PCI Express capability definitions required by the Broadcom
-STB PCIe controller driver.
-
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- include/pci.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/include/pci.h b/include/pci.h
-index 9cd8564436..281f353916 100644
---- a/include/pci.h
-+++ b/include/pci.h
-@@ -479,11 +479,20 @@
- #define PCI_EXP_DEVCTL		8	/* Device Control */
- #define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
- #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
-+#define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */
-+#define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
- #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
- #define PCI_EXP_LNKSTA		18	/* Link Status */
-+#define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */
-+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
-+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
-+#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
-+#define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Negotiated Link Width */
-+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4	/* start of NLW mask in link status */
- #define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
- #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
- #define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
-+#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
- 
- /* Include the ID list */
- 
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0009-pci-Add-driver-for-Broadcom-BCM2711-SoC-PCIe-control.patch

@@ -1,686 +0,0 @@
-From 21a9b72b4a28398c9511f3d9e3c1adc1439a8870 Mon Sep 17 00:00:00 2001
-Message-Id: <21a9b72b4a28398c9511f3d9e3c1adc1439a8870.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Sylwester Nawrocki <s.nawrocki@samsung.com>
-Date: Mon, 25 May 2020 13:39:58 +0200
-Subject: [PATCH 09/20] pci: Add driver for Broadcom BCM2711 SoC PCIe
- controller
-
-This patch adds basic driver PCI Express controller found on Broadcom
-set-top-box SoCs, e.g. BCM2711.
-The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
-handling removed. The inbound access memory region is not currently
-parsed from dma-ranges DT property and a fixed 3GB region is used.
-
-The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
-USB Host Controller.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
----
- drivers/pci/Kconfig        |   9 +
- drivers/pci/Makefile       |   1 +
- drivers/pci/pcie_brcmstb.c | 623 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 633 insertions(+)
- create mode 100644 drivers/pci/pcie_brcmstb.c
-
-diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
-index 6d8c22aacf..7e1e51d9ea 100644
---- a/drivers/pci/Kconfig
-+++ b/drivers/pci/Kconfig
-@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP
- 	  Say Y here if you want to enable PCIe controller support on
- 	  Rockchip SoCs.
- 
-+config PCI_BRCMSTB
-+	bool "Broadcom STB PCIe controller"
-+	depends on DM_PCI
-+	depends on ARCH_BCM283X
-+	help
-+	  Say Y here if you want to enable support for PCIe controller
-+	  on Broadcom set-top-box (STB) SoCs.
-+	  This driver currently supports only BCM2711 SoC and RC mode
-+	  of the controller.
- endif
-diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
-index 955351c5c2..29092916a6 100644
---- a/drivers/pci/Makefile
-+++ b/drivers/pci/Makefile
-@@ -44,3 +44,4 @@ obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
- obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
- obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
- obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
-+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
-diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
-new file mode 100644
-index 0000000000..dade79e9c8
---- /dev/null
-+++ b/drivers/pci/pcie_brcmstb.c
-@@ -0,0 +1,623 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Broadcom STB PCIe controller driver
-+ *
-+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
-+ *
-+ * Based on upstream Linux kernel driver:
-+ * drivers/pci/controller/pcie-brcmstb.c
-+ * Copyright (C) 2009 - 2017 Broadcom
-+ *
-+ * Based driver by Nicolas Saenz Julienne
-+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-+ */
-+
-+#include <common.h>
-+#include <errno.h>
-+#include <dm.h>
-+#include <dm/ofnode.h>
-+#include <pci.h>
-+#include <asm/io.h>
-+#include <linux/bitfield.h>
-+#include <linux/log2.h>
-+#include <linux/iopoll.h>
-+
-+/* Offset of the mandatory PCIe capability config registers */
-+#define BRCM_PCIE_CAP_REGS				0x00ac
-+
-+/* The PCIe controller register offsets */
-+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1		0x0188
-+#define  VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK	0xc
-+#define  VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN		0x0
-+
-+#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
-+#define  CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK		0xffffff
-+
-+#define PCIE_RC_DL_MDIO_ADDR				0x1100
-+#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
-+#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
-+
-+#define PCIE_MISC_MISC_CTRL				0x4008
-+#define  MISC_CTRL_SCB_ACCESS_EN_MASK			0x1000
-+#define  MISC_CTRL_CFG_READ_UR_MODE_MASK		0x2000
-+#define  MISC_CTRL_MAX_BURST_SIZE_MASK			0x300000
-+#define  MISC_CTRL_MAX_BURST_SIZE_128			0x0
-+#define  MISC_CTRL_SCB0_SIZE_MASK			0xf8000000
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
-+#define PCIE_MEM_WIN0_LO(win)	\
-+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
-+#define PCIE_MEM_WIN0_HI(win)	\
-+		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
-+
-+#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
-+#define  RC_BAR1_CONFIG_LO_SIZE_MASK			0x1f
-+
-+#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
-+#define  RC_BAR2_CONFIG_LO_SIZE_MASK			0x1f
-+#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
-+
-+#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
-+#define  RC_BAR3_CONFIG_LO_SIZE_MASK			0x1f
-+
-+#define PCIE_MISC_PCIE_STATUS				0x4068
-+#define  STATUS_PCIE_PORT_MASK				0x80
-+#define  STATUS_PCIE_PORT_SHIFT				7
-+#define  STATUS_PCIE_DL_ACTIVE_MASK			0x20
-+#define  STATUS_PCIE_DL_ACTIVE_SHIFT			5
-+#define  STATUS_PCIE_PHYLINKUP_MASK			0x10
-+#define  STATUS_PCIE_PHYLINKUP_SHIFT			4
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
-+#define  MEM_WIN0_BASE_LIMIT_LIMIT_MASK			0xfff00000
-+#define  MEM_WIN0_BASE_LIMIT_BASE_MASK			0xfff0
-+#define  MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT		12
-+#define PCIE_MEM_WIN0_BASE_LIMIT(win)	\
-+	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI		0x4080
-+#define  MEM_WIN0_BASE_HI_BASE_MASK			0xff
-+#define PCIE_MEM_WIN0_BASE_HI(win)	\
-+	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
-+
-+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI		0x4084
-+#define  PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK		0xff
-+#define PCIE_MEM_WIN0_LIMIT_HI(win)	\
-+	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
-+
-+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
-+#define  PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
-+#define  PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
-+
-+#define PCIE_MSI_INTR2_CLR				0x4508
-+#define PCIE_MSI_INTR2_MASK_SET				0x4510
-+
-+#define PCIE_EXT_CFG_DATA				0x8000
-+
-+#define PCIE_EXT_CFG_INDEX				0x9000
-+#define  PCIE_EXT_BUSNUM_SHIFT				20
-+#define  PCIE_EXT_SLOT_SHIFT				15
-+#define  PCIE_EXT_FUNC_SHIFT				12
-+
-+#define PCIE_RGR1_SW_INIT_1				0x9210
-+#define  RGR1_SW_INIT_1_PERST_MASK			0x1
-+#define  RGR1_SW_INIT_1_INIT_MASK			0x2
-+
-+/* PCIe parameters */
-+#define BRCM_NUM_PCIE_OUT_WINS				4
-+
-+/* MDIO registers */
-+#define MDIO_PORT0					0x0
-+#define MDIO_DATA_MASK					0x7fffffff
-+#define MDIO_DATA_SHIFT					0
-+#define MDIO_PORT_MASK					0xf0000
-+#define MDIO_PORT_SHIFT					16
-+#define MDIO_REGAD_MASK					0xffff
-+#define MDIO_REGAD_SHIFT				0
-+#define MDIO_CMD_MASK					0xfff00000
-+#define MDIO_CMD_SHIFT					20
-+#define MDIO_CMD_READ					0x1
-+#define MDIO_CMD_WRITE					0x0
-+#define MDIO_DATA_DONE_MASK				0x80000000
-+#define SSC_REGS_ADDR					0x1100
-+#define SET_ADDR_OFFSET					0x1f
-+#define SSC_CNTL_OFFSET					0x2
-+#define SSC_CNTL_OVRD_EN_MASK				0x8000
-+#define SSC_CNTL_OVRD_VAL_MASK				0x4000
-+#define SSC_STATUS_OFFSET				0x1
-+#define SSC_STATUS_SSC_MASK				0x400
-+#define SSC_STATUS_SSC_SHIFT				10
-+#define SSC_STATUS_PLL_LOCK_MASK			0x800
-+#define SSC_STATUS_PLL_LOCK_SHIFT			11
-+
-+/**
-+ * struct brcm_pcie - the PCIe controller state
-+ * @base: Base address of memory mapped IO registers of the controller
-+ * @gen: Non-zero value indicates limitation of the PCIe controller operation
-+ *       to a specific generation (1, 2 or 3)
-+ * @ssc: true indicates active Spread Spectrum Clocking operation
-+ */
-+struct brcm_pcie {
-+	void __iomem		*base;
-+
-+	int			gen;
-+	bool			ssc;
-+};
-+
-+/**
-+ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
-+ * @size: The inbound region size
-+ *
-+ * This function converts size of the inbound "BAR" region to the non-linear
-+ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
-+ *
-+ * Return: The encoded inbound region size
-+ */
-+static int brcm_pcie_encode_ibar_size(u64 size)
-+{
-+	int log2_in = ilog2(size);
-+
-+	if (log2_in >= 12 && log2_in <= 15)
-+		/* Covers 4KB to 32KB (inclusive) */
-+		return (log2_in - 12) + 0x1c;
-+	else if (log2_in >= 16 && log2_in <= 37)
-+		/* Covers 64KB to 32GB, (inclusive) */
-+		return log2_in - 15;
-+
-+	/* Something is awry so disable */
-+	return 0;
-+}
-+
-+/**
-+ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
-+ * @pcie: Pointer to the PCIe controller state
-+ *
-+ * The controller is capable of serving in both RC and EP roles.
-+ *
-+ * Return: true for RC mode, false for EP mode.
-+ */
-+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
-+{
-+	u32 val;
-+
-+	val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
-+
-+	return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
-+}
-+
-+/**
-+ * brcm_pcie_link_up() - Check whether the PCIe link is up
-+ * @pcie: Pointer to the PCIe controller state
-+ *
-+ * Return: true if the link is up, false otherwise.
-+ */
-+static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
-+{
-+	u32 val, dla, plu;
-+
-+	val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
-+	dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
-+	plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
-+
-+	return dla && plu;
-+}
-+
-+static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
-+				    uint offset, void **paddress)
-+{
-+	struct brcm_pcie *pcie = dev_get_priv(dev);
-+	unsigned int pci_bus = PCI_BUS(bdf);
-+	unsigned int pci_dev = PCI_DEV(bdf);
-+	unsigned int pci_func = PCI_FUNC(bdf);
-+	int idx;
-+
-+	/*
-+	 * Busses 0 (host PCIe bridge) and 1 (its immediate child)
-+	 * are limited to a single device each
-+	 */
-+	if (pci_bus < 2 && pci_dev > 0)
-+		return -EINVAL;
-+
-+	/* Accesses to the RC go right to the RC registers */
-+	if (pci_bus == 0) {
-+		*paddress = pcie->base + offset;
-+		return 0;
-+	}
-+
-+	/* For devices, write to the config space index register */
-+	idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
-+		| (pci_dev << PCIE_EXT_SLOT_SHIFT)
-+		| (pci_func << PCIE_EXT_FUNC_SHIFT);
-+
-+	writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
-+	*paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
-+
-+	return 0;
-+}
-+
-+static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
-+				 uint offset, ulong *valuep,
-+				 enum pci_size_t size)
-+{
-+	return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
-+					    bdf, offset, valuep, size);
-+}
-+
-+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
-+				  uint offset, ulong value,
-+				  enum pci_size_t size)
-+{
-+	return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
-+					     bdf, offset, value, size);
-+}
-+
-+static const char *link_speed_to_str(unsigned int cls)
-+{
-+	switch (cls) {
-+	case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
-+	case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
-+	case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
-+	default:
-+		break;
-+	}
-+
-+	return "??";
-+}
-+
-+static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
-+				   unsigned int cmd)
-+{
-+	u32 pkt;
-+
-+	pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
-+	pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
-+	pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
-+
-+	return pkt;
-+}
-+
-+/**
-+ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
-+ * @base: Pointer to the PCIe controller IO registers
-+ * @port: The MDIO port number
-+ * @regad: The register address
-+ * @val: A pointer at which to store the read value
-+ *
-+ * Return: 0 on success and register value in @val, negative error value
-+ *         on failure.
-+ */
-+static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
-+			       unsigned int regad, u32 *val)
-+{
-+	u32 data, addr;
-+	int ret;
-+
-+	addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
-+	writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
-+	readl(base + PCIE_RC_DL_MDIO_ADDR);
-+
-+	ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
-+				 (data & MDIO_DATA_DONE_MASK), 100);
-+
-+	*val = data & MDIO_DATA_MASK;
-+
-+	return ret;
-+}
-+
-+/**
-+ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
-+ * @base: Pointer to the PCIe controller IO registers
-+ * @port: The MDIO port number
-+ * @regad: Address of the register
-+ * @wrdata: The value to write
-+ *
-+ * Return: 0 on success, negative error value on failure.
-+ */
-+static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
-+				unsigned int regad, u16 wrdata)
-+{
-+	u32 data, addr;
-+
-+	addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
-+	writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
-+	readl(base + PCIE_RC_DL_MDIO_ADDR);
-+	writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
-+
-+	return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
-+				  !(data & MDIO_DATA_DONE_MASK), 100);
-+}
-+
-+/**
-+ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
-+ * @base: pointer to the PCIe controller IO registers
-+ *
-+ * Return: 0 on success, negative error value on failure.
-+ */
-+static int brcm_pcie_set_ssc(void __iomem *base)
-+{
-+	int pll, ssc;
-+	int ret;
-+	u32 tmp;
-+
-+	ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
-+				   SSC_REGS_ADDR);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
-+	if (ret < 0)
-+		return ret;
-+
-+	tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
-+
-+	ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
-+	if (ret < 0)
-+		return ret;
-+
-+	udelay(1000);
-+	ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
-+	if (ret < 0)
-+		return ret;
-+
-+	ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
-+	pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
-+
-+	return ssc && pll ? 0 : -EIO;
-+}
-+
-+/**
-+ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
-+ * @pcie: pointer to the PCIe controller state
-+ * @gen: PCIe generation to limit the controller's operation to
-+ */
-+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
-+{
-+	void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
-+
-+	u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
-+	u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
-+
-+	lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
-+	writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
-+
-+	lnkctl2 = (lnkctl2 & ~0xf) | gen;
-+	writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
-+}
-+
-+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
-+				       unsigned int win, u64 phys_addr,
-+				       u64 pcie_addr, u64 size)
-+{
-+	void __iomem *base = pcie->base;
-+	u32 phys_addr_mb_high, limit_addr_mb_high;
-+	phys_addr_t phys_addr_mb, limit_addr_mb;
-+	int high_addr_shift;
-+	u32 tmp;
-+
-+	/* Set the base of the pcie_addr window */
-+	writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
-+	writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
-+
-+	/* Write the addr base & limit lower bits (in MBs) */
-+	phys_addr_mb = phys_addr / SZ_1M;
-+	limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
-+
-+	tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
-+	u32p_replace_bits(&tmp, phys_addr_mb,
-+			  MEM_WIN0_BASE_LIMIT_BASE_MASK);
-+	u32p_replace_bits(&tmp, limit_addr_mb,
-+			  MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
-+	writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
-+
-+	/* Write the cpu & limit addr upper bits */
-+	high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
-+	phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
-+	tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
-+	u32p_replace_bits(&tmp, phys_addr_mb_high,
-+			  MEM_WIN0_BASE_HI_BASE_MASK);
-+	writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
-+
-+	limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
-+	tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
-+	u32p_replace_bits(&tmp, limit_addr_mb_high,
-+			  PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
-+	writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
-+}
-+
-+static int brcm_pcie_probe(struct udevice *dev)
-+{
-+	struct udevice *ctlr = pci_get_controller(dev);
-+	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
-+	struct brcm_pcie *pcie = dev_get_priv(dev);
-+	void __iomem *base = pcie->base;
-+	bool ssc_good = false;
-+	int num_out_wins = 0;
-+	u64 rc_bar2_offset, rc_bar2_size;
-+	unsigned int scb_size_val;
-+	int i, ret;
-+	u16 nlw, cls, lnksta;
-+	u32 tmp;
-+
-+	/*
-+	 * Reset the bridge, assert the fundamental reset. Note for some SoCs,
-+	 * e.g. BCM7278, the fundamental reset should not be asserted here.
-+	 * This will need to be changed when support for other SoCs is added.
-+	 */
-+	setbits_le32(base + PCIE_RGR1_SW_INIT_1,
-+		     RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
-+	/*
-+	 * The delay is a safety precaution to preclude the reset signal
-+	 * from looking like a glitch.
-+	 */
-+	udelay(100);
-+
-+	/* Take the bridge out of reset */
-+	clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
-+
-+	clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
-+		     PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
-+
-+	/* Wait for SerDes to be stable */
-+	udelay(100);
-+
-+	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
-+	clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
-+			MISC_CTRL_MAX_BURST_SIZE_MASK,
-+			MISC_CTRL_SCB_ACCESS_EN_MASK |
-+			MISC_CTRL_CFG_READ_UR_MODE_MASK |
-+			MISC_CTRL_MAX_BURST_SIZE_128);
-+	/*
-+	 * TODO: When support for other SoCs than BCM2711 is added we may
-+	 * need to use the base address and size(s) provided in the dma-ranges
-+	 * property.
-+	 */
-+	rc_bar2_offset = 0;
-+	rc_bar2_size = 0xc0000000;
-+
-+	tmp = lower_32_bits(rc_bar2_offset);
-+	u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
-+			  RC_BAR2_CONFIG_LO_SIZE_MASK);
-+	writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
-+	writel(upper_32_bits(rc_bar2_offset),
-+	       base + PCIE_MISC_RC_BAR2_CONFIG_HI);
-+
-+	scb_size_val = rc_bar2_size ?
-+		       ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
-+
-+	tmp = readl(base + PCIE_MISC_MISC_CTRL);
-+	u32p_replace_bits(&tmp, scb_size_val,
-+			  MISC_CTRL_SCB0_SIZE_MASK);
-+	writel(tmp, base + PCIE_MISC_MISC_CTRL);
-+
-+	/* Disable the PCIe->GISB memory window (RC_BAR1) */
-+	clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
-+		     RC_BAR1_CONFIG_LO_SIZE_MASK);
-+
-+	/* Disable the PCIe->SCB memory window (RC_BAR3) */
-+	clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
-+		     RC_BAR3_CONFIG_LO_SIZE_MASK);
-+
-+	/* Mask all interrupts since we are not handling any yet */
-+	writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
-+
-+	/* Clear any interrupts we find on boot */
-+	writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
-+
-+	if (pcie->gen)
-+		brcm_pcie_set_gen(pcie, pcie->gen);
-+
-+	/* Unassert the fundamental reset */
-+	clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
-+		     RGR1_SW_INIT_1_PERST_MASK);
-+
-+	/* Give the RC/EP time to wake up, before trying to configure RC.
-+	 * Intermittently check status for link-up, up to a total of 100ms.
-+	 */
-+	for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
-+		mdelay(5);
-+
-+	if (!brcm_pcie_link_up(pcie)) {
-+		printf("PCIe BRCM: link down\n");
-+		return -EINVAL;
-+	}
-+
-+	if (!brcm_pcie_rc_mode(pcie)) {
-+		printf("PCIe misconfigured; is in EP mode\n");
-+		return -EINVAL;
-+	}
-+
-+	for (i = 0; i < hose->region_count; i++) {
-+		struct pci_region *reg = &hose->regions[i];
-+
-+		if (reg->flags != PCI_REGION_MEM)
-+			continue;
-+
-+		if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
-+			return -EINVAL;
-+
-+		brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
-+					   reg->bus_start, reg->size);
-+
-+		num_out_wins++;
-+	}
-+
-+	/*
-+	 * For config space accesses on the RC, show the right class for
-+	 * a PCIe-PCIe bridge (the default setting is to be EP mode).
-+	 */
-+	clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
-+			CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
-+
-+	if (pcie->ssc) {
-+		ret = brcm_pcie_set_ssc(pcie->base);
-+		if (!ret)
-+			ssc_good = true;
-+		else
-+			printf("PCIe BRCM: failed attempt to enter SSC mode\n");
-+	}
-+
-+	lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
-+	cls = lnksta & PCI_EXP_LNKSTA_CLS;
-+	nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
-+
-+	printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
-+	       nlw, ssc_good ? "(SSC)" : "(!SSC)");
-+
-+	/* PCIe->SCB endian mode for BAR */
-+	clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
-+			VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
-+			VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
-+	/*
-+	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
-+	 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
-+	 */
-+	setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
-+		     PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
-+
-+	return 0;
-+}
-+
-+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
-+{
-+	struct brcm_pcie *pcie = dev_get_priv(dev);
-+	ofnode dn = dev_ofnode(dev);
-+	u32 max_link_speed;
-+	int ret;
-+
-+	/* Get the controller base address */
-+	pcie->base = dev_read_addr_ptr(dev);
-+	if (!pcie->base)
-+		return -EINVAL;
-+
-+	pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
-+
-+	ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
-+	if (ret < 0 || max_link_speed > 4)
-+		pcie->gen = 0;
-+	else
-+		pcie->gen = max_link_speed;
-+
-+	return 0;
-+}
-+
-+static const struct dm_pci_ops brcm_pcie_ops = {
-+	.read_config	= brcm_pcie_read_config,
-+	.write_config	= brcm_pcie_write_config,
-+};
-+
-+static const struct udevice_id brcm_pcie_ids[] = {
-+	{ .compatible = "brcm,bcm2711-pcie" },
-+	{ }
-+};
-+
-+U_BOOT_DRIVER(pcie_brcm_base) = {
-+	.name			= "pcie_brcm",
-+	.id			= UCLASS_PCI,
-+	.ops			= &brcm_pcie_ops,
-+	.of_match		= brcm_pcie_ids,
-+	.probe			= brcm_pcie_probe,
-+	.ofdata_to_platdata	= brcm_pcie_ofdata_to_platdata,
-+	.priv_auto_alloc_size	= sizeof(struct brcm_pcie),
-+};
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0010-configs-Enable-support-for-the-XHCI-controller-on-RP.patch

@@ -1,102 +0,0 @@
-From 66537b5984af81b5add420df9eb64c508268f581 Mon Sep 17 00:00:00 2001
-Message-Id: <66537b5984af81b5add420df9eb64c508268f581.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Mon, 25 May 2020 13:39:59 +0200
-Subject: [PATCH 10/20] configs: Enable support for the XHCI controller on RPI4
- board (ARM 64-bit)
-
-This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
-and USB commands. To get it working one has to call the following commands:
-"pci enum; usb start;", thus such commands have been added to the default
-"preboot" environment variable. One has to update their environment if it
-is already configured to get this feature working out of the box.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
----
- configs/rpi_4_defconfig     | 9 +++++++++
- configs/rpi_arm64_defconfig | 8 +++++++-
- 2 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
-index f0301dc8bc..b42efe6072 100644
---- a/configs/rpi_4_defconfig
-+++ b/configs/rpi_4_defconfig
-@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
- CONFIG_ENV_SIZE=0x4000
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_OF_BOARD_SETUP=y
-+CONFIG_USE_PREBOOT=y
-+CONFIG_PREBOOT="pci enum; usb start;"
- CONFIG_MISC_INIT_R=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
-@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
- CONFIG_CMD_DFU=y
- CONFIG_CMD_GPIO=y
- CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
- CONFIG_CMD_FS_UUID=y
- CONFIG_OF_BOARD=y
- CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
-@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y
- CONFIG_MMC_SDHCI_BCM2835=y
- CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
-+CONFIG_PCI=y
-+CONFIG_DM_PCI=y
-+CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
- CONFIG_DM_USB_GADGET=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PCI=y
- CONFIG_USB_GADGET=y
- CONFIG_USB_GADGET_MANUFACTURER="FSL"
- CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
-index d16c2388af..0feea7f0be 100644
---- a/configs/rpi_arm64_defconfig
-+++ b/configs/rpi_arm64_defconfig
-@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_OF_BOARD_SETUP=y
- CONFIG_USE_PREBOOT=y
--CONFIG_PREBOOT="usb start"
-+CONFIG_PREBOOT="pci enum; usb start;"
- CONFIG_MISC_INIT_R=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
- CONFIG_SYS_PROMPT="U-Boot> "
- CONFIG_CMD_GPIO=y
- CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
- CONFIG_CMD_USB=y
- CONFIG_CMD_FS_UUID=y
- CONFIG_OF_BOARD=y
-@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y
- CONFIG_MMC_SDHCI_BCM2835=y
- CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
-+CONFIG_PCI=y
-+CONFIG_DM_PCI=y
-+CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PCI=y
- CONFIG_USB_DWC2=y
- CONFIG_USB_KEYBOARD=y
- CONFIG_USB_HOST_ETHER=y
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0011-arm-rpi-Add-function-to-trigger-VL805-s-firmware-loa.patch

@@ -1,131 +0,0 @@
-From 2899e2cbe5412ee6f6a01855467fa37534ffc2be Mon Sep 17 00:00:00 2001
-Message-Id: <2899e2cbe5412ee6f6a01855467fa37534ffc2be.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:22 +0200
-Subject: [PATCH 11/20] arm: rpi: Add function to trigger VL805's firmware load
-
-On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
-may either be loaded directly from an EEPROM or, if not present, by the
-SoC's VideCore (the SoC's co-processor). Introduce the function that
-informs VideCore that VL805 may need its firmware loaded.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++
- arch/arm/mach-bcm283x/include/mach/msg.h  |  7 ++++
- arch/arm/mach-bcm283x/msg.c               | 46 +++++++++++++++++++++++
- 3 files changed, 66 insertions(+)
-
-diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
-index 60e226ce1d..2ae2d3d97c 100644
---- a/arch/arm/mach-bcm283x/include/mach/mbox.h
-+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
-@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette {
- 	} body;
- };
- 
-+#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET          0x00030058
-+
-+struct bcm2835_mbox_tag_pci_dev_addr {
-+	struct bcm2835_mbox_tag_hdr tag_hdr;
-+	union {
-+		struct {
-+			u32 dev_addr;
-+		} req;
-+		struct {
-+		} resp;
-+	} body;
-+};
-+
- /*
-  * Pass a raw u32 message to the VC, and receive a raw u32 back.
-  *
-diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h
-index 4afb08631b..e45c1bf010 100644
---- a/arch/arm/mach-bcm283x/include/mach/msg.h
-+++ b/arch/arm/mach-bcm283x/include/mach/msg.h
-@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
- 			     int pixel_order, int alpha_mode, ulong *fb_basep,
- 			     ulong *fb_sizep, int *pitchp);
- 
-+/**
-+ * bcm2711_load_vl805_firmware() - get vl805's firmware loaded
-+ *
-+ * @return 0 if OK, -EIO on error
-+ */
-+int bcm2711_notify_vl805_reset(void);
-+
- #endif
-diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
-index 94b75283f8..347aece3cd 100644
---- a/arch/arm/mach-bcm283x/msg.c
-+++ b/arch/arm/mach-bcm283x/msg.c
-@@ -7,6 +7,7 @@
- #include <memalign.h>
- #include <phys2bus.h>
- #include <asm/arch/mbox.h>
-+#include <linux/delay.h>
- 
- struct msg_set_power_state {
- 	struct bcm2835_mbox_hdr hdr;
-@@ -40,6 +41,12 @@ struct msg_setup {
- 	u32 end_tag;
- };
- 
-+struct msg_notify_vl805_reset {
-+	struct bcm2835_mbox_hdr hdr;
-+	struct bcm2835_mbox_tag_pci_dev_addr dev_addr;
-+	u32 end_tag;
-+};
-+
- int bcm2835_power_on_module(u32 module)
- {
- 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
-@@ -151,3 +158,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
- 
- 	return 0;
- }
-+
-+/*
-+ * On the Raspberry Pi 4, after a PCI reset, VL805's (the xHCI chip) firmware
-+ * may either be loaded directly from an EEPROM or, if not present, by the
-+ * SoC's VideoCore. This informs VideoCore that VL805 needs its firmware
-+ * loaded.
-+ */
-+int bcm2711_notify_vl805_reset(void)
-+{
-+	ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
-+				 msg_notify_vl805_reset, 1);
-+	int ret;
-+
-+	BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
-+	BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,
-+			      NOTIFY_XHCI_RESET);
-+
-+	/*
-+	 * The pci device address is expected like this:
-+	 *
-+	 *   PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12
-+	 *
-+	 * But since RPi4's PCIe setup is hardwired, we know the address in
-+	 * advance.
-+	 */
-+	msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000;
-+
-+	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
-+				     &msg_notify_vl805_reset->hdr);
-+	if (ret) {
-+		printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
-+		return -EIO;
-+	}
-+
-+	udelay(200);
-+
-+	return 0;
-+}
-+
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0012-reset-Add-Raspberry-Pi-4-firmware-reset-controller.patch

@@ -1,140 +0,0 @@
-From e9925f97c2c31253e1ff62de4049d90e19884f55 Mon Sep 17 00:00:00 2001
-Message-Id: <e9925f97c2c31253e1ff62de4049d90e19884f55.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:23 +0200
-Subject: [PATCH 12/20] reset: Add Raspberry Pi 4 firmware reset controller
-
-Raspberry Pi 4's co-processor controls some of the board's HW
-initialization process, but it's up to Linux to trigger it when
-relevant. Introduce a reset controller capable of interfacing with
-RPi4's co-processor that models these firmware initialization routines as
-reset lines.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/reset/Kconfig                         | 10 ++++
- drivers/reset/Makefile                        |  1 +
- drivers/reset/reset-raspberrypi.c             | 60 +++++++++++++++++++
- .../reset/raspberrypi,firmware-reset.h        | 13 ++++
- 4 files changed, 84 insertions(+)
- create mode 100644 drivers/reset/reset-raspberrypi.c
- create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
-
-diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
-index 88d3be1593..d02c1522e5 100644
---- a/drivers/reset/Kconfig
-+++ b/drivers/reset/Kconfig
-@@ -148,4 +148,14 @@ config RESET_IMX7
- 	help
- 	  Support for reset controller on i.MX7/8 SoCs.
- 
-+config RESET_RASPBERRYPI
-+	bool "Raspberry Pi 4 Firmware Reset Controller Driver"
-+	depends on DM_RESET && ARCH_BCM283X
-+	default USB_XHCI_PCI
-+	help
-+	  Raspberry Pi 4's co-processor controls some of the board's HW
-+	  initialization process, but it's up to Linux to trigger it when
-+	  relevant. This driver provides a reset controller capable of
-+	  interfacing with RPi4's co-processor and model these firmware
-+	  initialization routines as reset lines.
- endmenu
-diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
-index 0a044d5d8c..be54dae725 100644
---- a/drivers/reset/Makefile
-+++ b/drivers/reset/Makefile
-@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
- obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
- obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
- obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
-+obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
-diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c
-new file mode 100644
-index 0000000000..e2d284e5ac
---- /dev/null
-+++ b/drivers/reset/reset-raspberrypi.c
-@@ -0,0 +1,60 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Raspberry Pi 4 firmware reset driver
-+ *
-+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-+ */
-+#include <common.h>
-+#include <dm.h>
-+#include <reset-uclass.h>
-+#include <asm/arch/msg.h>
-+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-+
-+static int raspberrypi_reset_request(struct reset_ctl *reset_ctl)
-+{
-+	if (reset_ctl->id >= RASPBERRYPI_FIRMWARE_RESET_NUM_IDS)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int raspberrypi_reset_free(struct reset_ctl *reset_ctl)
-+{
-+	return 0;
-+}
-+
-+static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl)
-+{
-+	switch (reset_ctl->id) {
-+	case RASPBERRYPI_FIRMWARE_RESET_ID_USB:
-+		bcm2711_notify_vl805_reset();
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int raspberrypi_reset_deassert(struct reset_ctl *reset_ctl)
-+{
-+	return 0;
-+}
-+
-+struct reset_ops raspberrypi_reset_ops = {
-+	.request = raspberrypi_reset_request,
-+	.rfree = raspberrypi_reset_free,
-+	.rst_assert = raspberrypi_reset_assert,
-+	.rst_deassert = raspberrypi_reset_deassert,
-+};
-+
-+static const struct udevice_id raspberrypi_reset_ids[] = {
-+	{ .compatible = "raspberrypi,firmware-reset" },
-+	{ }
-+};
-+
-+U_BOOT_DRIVER(raspberrypi_reset) = {
-+	.name = "raspberrypi-reset",
-+	.id = UCLASS_RESET,
-+	.of_match = raspberrypi_reset_ids,
-+	.ops = &raspberrypi_reset_ops,
-+};
-+
-diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-new file mode 100644
-index 0000000000..1a4f4c7927
---- /dev/null
-+++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (c) 2020 Nicolas Saenz Julienne
-+ * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
-+
-+#define RASPBERRYPI_FIRMWARE_RESET_ID_USB	0
-+#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS	1
-+
-+#endif
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0013-configs-Enable-support-for-reset-controllers-on-RPi4.patch

@@ -1,57 +0,0 @@
-From d32b13ba58aa59a5ec0b71cfc2005bf1efd84ddf Mon Sep 17 00:00:00 2001
-Message-Id: <d32b13ba58aa59a5ec0b71cfc2005bf1efd84ddf.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:24 +0200
-Subject: [PATCH 13/20] configs: Enable support for reset controllers on RPi4
-
-This is required in order to access the reset controller used to
-initialize the board's xHCI chip.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- configs/rpi_4_32b_defconfig | 1 +
- configs/rpi_4_defconfig     | 1 +
- configs/rpi_arm64_defconfig | 1 +
- 3 files changed, 3 insertions(+)
-
-diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
-index a36a249540..0df5c17d6e 100644
---- a/configs/rpi_4_32b_defconfig
-+++ b/configs/rpi_4_32b_defconfig
-@@ -28,6 +28,7 @@ CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
-+CONFIG_DM_RESET=y
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
-diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
-index b42efe6072..f641ad3dfa 100644
---- a/configs/rpi_4_defconfig
-+++ b/configs/rpi_4_defconfig
-@@ -35,6 +35,7 @@ CONFIG_DM_PCI=y
- CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
-+CONFIG_DM_RESET=y
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
-diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
-index 0feea7f0be..4ce8469f43 100644
---- a/configs/rpi_arm64_defconfig
-+++ b/configs/rpi_arm64_defconfig
-@@ -32,6 +32,7 @@ CONFIG_DM_PCI=y
- CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
-+CONFIG_DM_RESET=y
- # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
- CONFIG_USB=y
- CONFIG_DM_USB=y
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0014-usb-xhci-Add-reset-controller-support.patch

@@ -1,106 +0,0 @@
-From a39dcf665d8867875b104661bd6a6325f502c5f2 Mon Sep 17 00:00:00 2001
-Message-Id: <a39dcf665d8867875b104661bd6a6325f502c5f2.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
-Date: Mon, 29 Jun 2020 18:37:25 +0200
-Subject: [PATCH 14/20] usb: xhci: Add reset controller support
-
-Some atypical users of xhci might need to manually reset their xHCI
-controller before starting the HCD setup. Check if a reset controller
-device is available to the PCI bus and trigger a reset.
-
-Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
----
- drivers/usb/host/xhci-mem.c |  2 ++
- drivers/usb/host/xhci.c     | 33 +++++++++++++++++++++++++++++++++
- include/usb/xhci.h          |  2 ++
- 3 files changed, 37 insertions(+)
-
-diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
-index f446520528..108f4bd8cf 100644
---- a/drivers/usb/host/xhci-mem.c
-+++ b/drivers/usb/host/xhci-mem.c
-@@ -180,6 +180,8 @@ void xhci_cleanup(struct xhci_ctrl *ctrl)
- 	xhci_free_virt_devices(ctrl);
- 	free(ctrl->erst.entries);
- 	free(ctrl->dcbaa);
-+	if (reset_valid(&ctrl->reset))
-+		reset_free(&ctrl->reset);
- 	memset(ctrl, '\0', sizeof(struct xhci_ctrl));
- }
- 
-diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
-index ebd2954571..e252964d0d 100644
---- a/drivers/usb/host/xhci.c
-+++ b/drivers/usb/host/xhci.c
-@@ -190,6 +190,35 @@ static int xhci_start(struct xhci_hcor *hcor)
- 	return ret;
- }
- 
-+/**
-+ * Resets XHCI Hardware
-+ *
-+ * @param ctrl	pointer to host controller
-+ * @return 0 if OK, or a negative error code.
-+ */
-+static int xhci_reset_hw(struct xhci_ctrl *ctrl)
-+{
-+	int ret;
-+
-+	ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
-+	if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
-+		dev_err(ctrl->dev, "failed to get reset\n");
-+		return ret;
-+	}
-+
-+	if (reset_valid(&ctrl->reset)) {
-+		ret = reset_assert(&ctrl->reset);
-+		if (ret)
-+			return ret;
-+
-+		ret = reset_deassert(&ctrl->reset);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
- /**
-  * Resets the XHCI Controller
-  *
-@@ -1508,6 +1537,10 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
- 
- 	ctrl->dev = dev;
- 
-+	ret = xhci_reset_hw(ctrl);
-+	if (ret)
-+		goto err;
-+
- 	/*
- 	 * XHCI needs to issue a Address device command to setup
- 	 * proper device context structures, before it can interact
-diff --git a/include/usb/xhci.h b/include/usb/xhci.h
-index 1170c0ac69..7d34103fd5 100644
---- a/include/usb/xhci.h
-+++ b/include/usb/xhci.h
-@@ -16,6 +16,7 @@
- #ifndef HOST_XHCI_H_
- #define HOST_XHCI_H_
- 
-+#include <reset.h>
- #include <asm/types.h>
- #include <asm/cache.h>
- #include <asm/io.h>
-@@ -1209,6 +1210,7 @@ struct xhci_ctrl {
- #if CONFIG_IS_ENABLED(DM_USB)
- 	struct udevice *dev;
- #endif
-+	struct reset_ctl reset;
- 	struct xhci_hccr *hccr;	/* R/O registers, not need for volatile */
- 	struct xhci_hcor *hcor;
- 	struct xhci_doorbell_array *dba;
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0016-arm-update-comments-to-the-common-style.patch

@@ -1,88 +0,0 @@
-From 32d72ef4331597864189b73b309490ac48f4ac05 Mon Sep 17 00:00:00 2001
-Message-Id: <32d72ef4331597864189b73b309490ac48f4ac05.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Wed, 3 Jun 2020 14:43:41 +0200
-Subject: [PATCH 16/20] arm: update comments to the common style
-
-Update the comments in include/asm/system.h to the common style.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Reviewed-by: Tom Rini <trini@konsulko.com>
----
- arch/arm/include/asm/system.h | 23 ++++++++++++++---------
- 1 file changed, 14 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
-index 7a40b56acd..0243f76e76 100644
---- a/arch/arm/include/asm/system.h
-+++ b/arch/arm/include/asm/system.h
-@@ -205,7 +205,7 @@ int __asm_invalidate_l3_icache(void);
- void __asm_switch_ttbr(u64 new_ttbr);
- 
- /*
-- * Switch from EL3 to EL2 for ARMv8
-+ * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
-  *
-  * @args:        For loading 64-bit OS, fdt address.
-  *               For loading 32-bit OS, zero.
-@@ -220,7 +220,7 @@ void __asm_switch_ttbr(u64 new_ttbr);
- void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
- 				    u64 arg4, u64 entry_point, u64 es_flag);
- /*
-- * Switch from EL2 to EL1 for ARMv8
-+ * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
-  *
-  * @args:        For loading 64-bit OS, fdt address.
-  *               For loading 32-bit OS, zero.
-@@ -246,11 +246,12 @@ void flush_l3_cache(void);
- void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
- 
- /*
-- *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
-+ * smc_call() - issue a secure monitor call
-+ *
-+ * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
-  * DEN0028A
-  *
-  * @args: input and output arguments
-- *
-  */
- void smc_call(struct pt_regs *args);
- 
-@@ -519,10 +520,12 @@ enum {
- #endif
- 
- /**
-+ * mmu_page_table_flush() - register an update to page tables
-+ *
-  * Register an update to the page tables, and flush the TLB
-  *
-- * \param start		start address of update in page table
-- * \param stop		stop address of update in page table
-+ * @start:	start address of update in page table
-+ * @stop:	stop address of update in page table
-  */
- void mmu_page_table_flush(unsigned long start, unsigned long stop);
- 
-@@ -583,11 +586,13 @@ s32 psci_features(u32 function_id, u32 psci_fid);
- void save_boot_params_ret(void);
- 
- /**
-+ * mmu_set_region_dcache_behaviour() - set cache settings
-+ *
-  * Change the cache settings for a region.
-  *
-- * \param start		start address of memory region to change
-- * \param size		size of memory region to change
-- * \param option	dcache option to select
-+ * @start:	start address of memory region to change
-+ * @size:	size of memory region to change
-+ * @option:	dcache option to select
-  */
- void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- 				     enum dcache_option option);
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0017-arm-provide-a-function-for-boards-init-code-to-modif.patch

@@ -1,130 +0,0 @@
-From 82a944e4d1356e9ab3c87e6dc57b1b7213cbb233 Mon Sep 17 00:00:00 2001
-Message-Id: <82a944e4d1356e9ab3c87e6dc57b1b7213cbb233.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Wed, 3 Jun 2020 14:43:42 +0200
-Subject: [PATCH 17/20] arm: provide a function for boards init code to modify
- MMU virtual-physical map
-
-Provide function for setting arbitrary virtual-physical MMU mapping
-and cache settings for the given region.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Reviewed-by: Tom Rini <trini@konsulko.com>
----
- arch/arm/include/asm/mmu.h    |  8 ++++++++
- arch/arm/include/asm/system.h | 13 +++++++++++++
- arch/arm/lib/cache-cp15.c     | 24 ++++++++++++++++++------
- 3 files changed, 39 insertions(+), 6 deletions(-)
- create mode 100644 arch/arm/include/asm/mmu.h
-
-diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
-new file mode 100644
-index 0000000000..9ac16f599e
---- /dev/null
-+++ b/arch/arm/include/asm/mmu.h
-@@ -0,0 +1,8 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+
-+#ifndef __ASM_ARM_MMU_H
-+#define __ASM_ARM_MMU_H
-+
-+void init_addr_map(void);
-+
-+#endif
-diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
-index 0243f76e76..f9290fa9b6 100644
---- a/arch/arm/include/asm/system.h
-+++ b/arch/arm/include/asm/system.h
-@@ -585,6 +585,19 @@ s32 psci_features(u32 function_id, u32 psci_fid);
-  */
- void save_boot_params_ret(void);
- 
-+/**
-+ * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
-+ *
-+ * Change the virt/phys mapping and cache settings for a region.
-+ *
-+ * @virt:	virtual start address of memory region to change
-+ * @phys:	physical address for the memory region to set
-+ * @size:	size of memory region to change
-+ * @option:	dcache option to select
-+ */
-+void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
-+					size_t size, enum dcache_option option);
-+
- /**
-  * mmu_set_region_dcache_behaviour() - set cache settings
-  *
-diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
-index 1da2e92fe2..39717610d4 100644
---- a/arch/arm/lib/cache-cp15.c
-+++ b/arch/arm/lib/cache-cp15.c
-@@ -25,7 +25,8 @@ __weak void arm_init_domains(void)
- {
- }
- 
--void set_section_dcache(int section, enum dcache_option option)
-+static void set_section_phys(int section, phys_addr_t phys,
-+			     enum dcache_option option)
- {
- #ifdef CONFIG_ARMV7_LPAE
- 	u64 *page_table = (u64 *)gd->arch.tlb_addr;
-@@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option)
- #endif
- 
- 	/* Add the page offset */
--	value |= ((u32)section << MMU_SECTION_SHIFT);
-+	value |= phys;
- 
- 	/* Add caching bits */
- 	value |= option;
-@@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option)
- 	page_table[section] = value;
- }
- 
-+void set_section_dcache(int section, enum dcache_option option)
-+{
-+	set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
-+}
-+
- __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
- {
- 	debug("%s: Warning: not implemented\n", __func__);
- }
- 
--void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
--				     enum dcache_option option)
-+void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
-+					size_t size, enum dcache_option option)
- {
- #ifdef CONFIG_ARMV7_LPAE
- 	u64 *page_table = (u64 *)gd->arch.tlb_addr;
-@@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- 	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
- 	      option);
- #endif
--	for (upto = start; upto < end; upto++)
--		set_section_dcache(upto, option);
-+	for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
-+		set_section_phys(upto, phys, option);
- 
- 	/*
- 	 * Make sure range is cache line aligned
-@@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- 	mmu_page_table_flush(startpt, stoppt);
- }
- 
-+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-+				     enum dcache_option option)
-+{
-+	mmu_set_region_dcache_behaviour_phys(start, start, size, option);
-+}
-+
- __weak void dram_bank_mmu_setup(int bank)
- {
- 	bd_t *bd = gd->bd;
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0018-mmc-bcm283x-fix-int-to-pointer-cast.patch

@@ -1,33 +0,0 @@
-From 2904bea082a1524b13af6afed08a7f5ee9faf0ae Mon Sep 17 00:00:00 2001
-Message-Id: <2904bea082a1524b13af6afed08a7f5ee9faf0ae.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Seung-Woo Kim <sw0312.kim@samsung.com>
-Date: Wed, 3 Jun 2020 14:43:43 +0200
-Subject: [PATCH 18/20] mmc: bcm283x: fix int to pointer cast
-
-On build with 32 bit, there is a warning for int-to-pointer-cast.
-Fix the int to pointer cast by using uintptr_t.
-
-Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
----
- drivers/mmc/bcm2835_sdhci.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
-index dc3dffb657..5cdf3c506f 100644
---- a/drivers/mmc/bcm2835_sdhci.c
-+++ b/drivers/mmc/bcm2835_sdhci.c
-@@ -210,7 +210,7 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
- 	priv->last_write = 0;
- 
- 	host->name = dev->name;
--	host->ioaddr = (void *)base;
-+	host->ioaddr = (void *)(uintptr_t)base;
- 	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
- 		SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
- 	host->max_clk = emmc_freq;
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0019-rpi4-add-a-mapping-for-the-PCIe-XHCI-controller-MMIO.patch

@@ -1,85 +0,0 @@
-From a8c492ef2a3a73d435765ce28944efebce5cfa17 Mon Sep 17 00:00:00 2001
-Message-Id: <a8c492ef2a3a73d435765ce28944efebce5cfa17.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Wed, 3 Jun 2020 14:43:44 +0200
-Subject: [PATCH 19/20] rpi4: add a mapping for the PCIe XHCI controller MMIO
- registers (ARM 32bit)
-
-Create a non-cacheable mapping for the 0x600000000 physical memory region,
-where MMIO registers for the PCIe XHCI controller are instantiated by the
-PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
-32bit mode, this region is mapped at 0xff800000 CPU virtual address.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
----
- arch/arm/mach-bcm283x/Kconfig             |  1 +
- arch/arm/mach-bcm283x/include/mach/base.h |  8 ++++++++
- arch/arm/mach-bcm283x/init.c              | 21 +++++++++++++++++++++
- 3 files changed, 30 insertions(+)
-
-diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
-index e6eb904e7f..b3287ce8bc 100644
---- a/arch/arm/mach-bcm283x/Kconfig
-+++ b/arch/arm/mach-bcm283x/Kconfig
-@@ -36,6 +36,7 @@ config BCM2711_32B
- 	select BCM2711
- 	select ARMV7_LPAE
- 	select CPU_V7A
-+	select PHYS_64BIT
- 
- config BCM2711_64B
- 	bool "Broadcom BCM2711 SoC 64-bit support"
-diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
-index c4ae39852f..4ccaf69693 100644
---- a/arch/arm/mach-bcm283x/include/mach/base.h
-+++ b/arch/arm/mach-bcm283x/include/mach/base.h
-@@ -8,4 +8,12 @@
- 
- extern unsigned long rpi_bcm283x_base;
- 
-+#ifdef CONFIG_ARMV7_LPAE
-+#ifdef CONFIG_TARGET_RPI_4_32B
-+#include <addr_map.h>
-+#define phys_to_virt addrmap_phys_to_virt
-+#define virt_to_phys addrmap_virt_to_phys
-+#endif
-+#endif
-+
- #endif
-diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
-index cf4c5b245d..f2a5411623 100644
---- a/arch/arm/mach-bcm283x/init.c
-+++ b/arch/arm/mach-bcm283x/init.c
-@@ -146,6 +146,27 @@ int mach_cpu_init(void)
- }
- 
- #ifdef CONFIG_ARMV7_LPAE
-+#ifdef CONFIG_TARGET_RPI_4_32B
-+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT	0xff800000UL
-+#include <addr_map.h>
-+#include <asm/system.h>
-+
-+void init_addr_map(void)
-+{
-+	mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
-+					     BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
-+					     BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
-+					     DCACHE_OFF);
-+
-+	/* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
-+	addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
-+	/* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
-+	addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
-+			  BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
-+			  BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
-+}
-+#endif
-+
- void enable_caches(void)
- {
- 	dcache_enable();
--- 
-2.27.0
-

buildroot-external/patches/uboot/2020.07/0020-config-Enable-support-for-the-XHCI-controller-on-RPI.patch

@@ -1,71 +0,0 @@
-From 52d942897bcf2c775c3c5dff9f811e1a28f3fd7d Mon Sep 17 00:00:00 2001
-Message-Id: <52d942897bcf2c775c3c5dff9f811e1a28f3fd7d.1595101389.git.stefan@agner.ch>
-In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
-From: Marek Szyprowski <m.szyprowski@samsung.com>
-Date: Wed, 3 Jun 2020 14:43:45 +0200
-Subject: [PATCH 20/20] config: Enable support for the XHCI controller on RPI4
- board
-
-This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
-and USB commands. To get it working one has to call the following commands:
-"pci enum; usb start;", thus such commands have been added to the default
-"preboot" environment variable. One has to update their environment if it
-is already configured to get this feature working out of the box.
-
-Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
----
- configs/rpi_4_32b_defconfig | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
-diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
-index 0df5c17d6e..db7b781976 100644
---- a/configs/rpi_4_32b_defconfig
-+++ b/configs/rpi_4_32b_defconfig
-@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
- CONFIG_ENV_SIZE=0x4000
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_OF_BOARD_SETUP=y
-+CONFIG_USE_PREBOOT=y
-+CONFIG_PREBOOT="pci enum; usb start;"
- CONFIG_MISC_INIT_R=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
-@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
- CONFIG_CMD_DFU=y
- CONFIG_CMD_GPIO=y
- CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
- CONFIG_CMD_FS_UUID=y
- CONFIG_OF_BOARD=y
- CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
-@@ -26,6 +30,9 @@ CONFIG_MMC_SDHCI_SDMA=y
- CONFIG_MMC_SDHCI_BCM2835=y
- CONFIG_DM_ETH=y
- CONFIG_BCMGENET=y
-+CONFIG_PCI=y
-+CONFIG_DM_PCI=y
-+CONFIG_PCI_BRCMSTB=y
- CONFIG_PINCTRL=y
- # CONFIG_PINCTRL_GENERIC is not set
- CONFIG_DM_RESET=y
-@@ -33,6 +40,8 @@ CONFIG_DM_RESET=y
- CONFIG_USB=y
- CONFIG_DM_USB=y
- CONFIG_DM_USB_GADGET=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_PCI=y
- CONFIG_USB_GADGET=y
- CONFIG_USB_GADGET_MANUFACTURER="FSL"
- CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-@@ -45,4 +54,6 @@ CONFIG_DM_VIDEO=y
- CONFIG_SYS_WHITE_ON_BLACK=y
- CONFIG_CONSOLE_SCROLL_LINES=10
- CONFIG_PHYS_TO_BUS=y
-+CONFIG_ADDR_MAP=y
-+CONFIG_SYS_NUM_ADDR_MAP=2
- CONFIG_OF_LIBFDT_OVERLAY=y
--- 
-2.27.0
-

buildroot-patches/0009-linux-forcibly-disable-use-of-gcc-plugins.patch

@@ -96,10 +96,10 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  linux/linux.mk | 4 ++++
  1 file changed, 4 insertions(+)
 
-diff --git a/linux/linux.mk b/buildroot/linux/linux.mk
+diff --git a/buildroot/linux/linux.mk b/buildroot/linux/linux.mk
 index ae1edbeb..5a1cb42e 100644
---- a/linux/linux.mk
-+++ b/linux/linux.mk
+--- a/buildroot/linux/linux.mk
++++ b/buildroot/linux/linux.mk
 @@ -408,6 +408,7 @@ define LINUX_KCONFIG_FIXUP_CMDS
  		$(call KCONFIG_ENABLE_OPT,CONFIG_FB,$(@D)/.config)
  		$(call KCONFIG_ENABLE_OPT,CONFIG_LOGO,$(@D)/.config)

buildroot/CHANGES

@@ -1,31 +1,3 @@
-2020.02.3, released June 3rd, 2020
-
-	Important / security related fixes.
-
-	Fix various build issues of host packages on hosts using GCC
-	10.
-
-	Updated/fixed packages: arm-trusted-firmware, audit, bind,
-	binutils, bison, clamav, crda, dovecot, dtc, efl, elf2flt,
-	erlang, fakeroot, ffmpeg, fmc, fmlib, freerdp, gcc, git,
-	glib-networking, gnupg, leveldb, libexif, libssh2,
-	libusb-compat, linux-headers, lrzip, ltrace, mariadb, mesa3d,
-	mp4v2, openldap, openocd, perl, php, prosody,
-	python-pycryptodomex, python-pyqt5, qemu, rpi-firmware, rustc,
-	speexdsp, sysrepo, systemd, tremor, vboot-utils, wireshark,
-	xen
-
-	Removed packages: python-pycrypto
-
-	Issues resolved (http://bugs.uclibc.org):
-
-	#12361: Init system (systemd) kills login on Raspberry Pi Zero
-	#12656: bison fails to relocate with relocate-sdk.sh
-	#12671: leveldb won't detect that snappy is present (static..
-	#12691: host-rust build fails
-	#12831: RPI-firmware package: DTB-overlay dependency
-
-
 2020.02.2, released May 12th, 2020
 
 	Important / security related fixes.

buildroot/Config.in.legacy

@@ -146,13 +146,6 @@ endif
 
 comment "Legacy options removed in 2020.02"
 
-config BR2_PACKAGE_PYTHON_PYCRYPTO
-	bool "python-pycrypto package removed"
-	select BR2_LEGACY
-	help
-	  This package has been removed, use python-pycryptodomex
-	  instead.
-
 config BR2_PACKAGE_JAMVM
 	bool "jamvm removed"
 	select BR2_LEGACY

buildroot/DEVELOPERS

@@ -465,6 +465,9 @@ N:	Biagio Montaruli <biagio.hkr@gmail.com>
 F:	board/acmesystems/
 F:	configs/acmesystems_*
 
+N:	Bimal Jacob <bimal.jacob@rockwellcollins.com>
+F:	package/nginx-upload/
+
 N:	Bogdan Radulescu <bogdan@nimblex.net>
 F:	package/iftop/
 F:	package/ncdu/
@@ -479,6 +482,27 @@ N:	Carlo Caione <carlo.caione@gmail.com>
 F:	package/jailhouse/
 F:	package/sunxi-boards/
 
+N:	Carlos Santos <unixmania@gmail.com>
+F:	package/busybox/
+F:	package/initscripts/
+F:	package/intel-microcode/
+F:	package/liburiparser/
+F:	package/modem-manager/
+F:	package/pamtester/
+F:	package/pcm-tools/
+F:	package/skeleton-custom/
+F:	package/skeleton-init-common/
+F:	package/skeleton-init-none/
+F:	package/skeleton-init-systemd/
+F:	package/skeleton-init-sysv/
+F:	package/skeleton/
+F:	package/sysvinit/
+F:	package/util-linux/
+F:	package/tpm2-abrmd/
+F:	package/tpm2-tools/
+F:	package/tpm2-totp/
+F:	package/tpm2-tss/
+
 N:	Carsten Schoenert <c.schoenert@gmail.com>
 F:	package/dvbsnoop/
 F:	package/libdvbsi/
@@ -636,6 +660,9 @@ F:	package/openldap/
 N:	David du Colombier <0intro@gmail.com>
 F:	package/x264/
 
+N:	David Graziano <david.graziano@rockwellcollins.com>
+F:	package/libcsv/
+
 N:	David Lechner <david@lechnology.com>
 F:	board/lego/ev3/
 F:	configs/lego_ev3_defconfig
@@ -1176,6 +1203,9 @@ F:	package/python-pexpect/
 F:	package/python-ptyprocess/
 F:	package/zynq-boot-bin/
 
+N:	Jared Bents <jared.bents@rockwellcollins.com>
+F:	package/davici/
+
 N:	Jarkko Sakkinen <jarkko.sakkinen@intel.com>
 F:	package/quota/
 
@@ -1580,7 +1610,6 @@ F:	package/cgroupfs-mount/
 F:	package/crda/
 F:	package/cunit/
 F:	package/dacapo/
-F:	package/davici/
 F:	package/dnsmasq/
 F:	package/dosfstools/
 F:	package/eigen/
@@ -1844,6 +1873,9 @@ F:	package/openjpeg/
 N:	Olivier Singla <olivier.singla@gmail.com>
 F:	package/shellinabox/
 
+N:	Paresh Chaudhary <paresh.chaudhary@rockwellcollins.com>
+F:	package/checksec/
+
 N:	Parnell Springmeyer <parnell@digitalmentat.com>
 F:	package/scrypt/
 
@@ -2137,6 +2169,7 @@ N:	Ryan Barnett <ryan.barnett@rockwellcollins.com>
 F:	package/atftp/
 F:	package/miraclecast/
 F:	package/python-pyasn/
+F:	package/python-pycrypto/
 F:	package/python-pysnmp/
 F:	package/python-pysnmp-mibs/
 F:	package/python-tornado/
@@ -2280,10 +2313,12 @@ F:	package/libscrypt/
 N:	Stephan Hoffmann <sho@relinux.de>
 F:	package/cache-calibrator/
 F:	package/gtest/
-F:	package/libhttpserver/
 F:	package/mtdev/
 F:	package/mtdev2tuio/
 
+N:	Stephan Hoffmann <stephan.hoffmann@ext.grandcentrix.net>
+F:	package/libhttpserver/
+
 N:	Steve Calfee <stevecalfee@gmail.com>
 F:	package/python-pymysql/
 F:	package/python-pyratemp/

buildroot/Makefile

@@ -92,9 +92,9 @@ all:
 .PHONY: all
 
 # Set and export the version string
-export BR2_VERSION := 2020.02.3
+export BR2_VERSION := 2020.02.2
 # Actual time the release is cut (for reproducible builds)
-BR2_VERSION_EPOCH = 1591196000
+BR2_VERSION_EPOCH = 1589285000
 
 # Save running make version since it's clobbered by the make package
 RUNNING_MAKE_VERSION := $(MAKE_VERSION)

buildroot/board/freescale/common/imx/genimage.cfg.template_imx8

@@ -13,7 +13,7 @@ image boot.vfat {
       %FILES%
     }
   }
-  size = 64M
+  size = 32M
 }
 
 image sdcard.img {

buildroot/boot/arm-trusted-firmware/arm-trusted-firmware.mk

@@ -19,11 +19,9 @@ else
 ARM_TRUSTED_FIRMWARE_SITE = $(call github,ARM-software,arm-trusted-firmware,$(ARM_TRUSTED_FIRMWARE_VERSION))
 # The licensing of custom or from-git versions is unknown.
 # This is valid only for the official v1.4.
-ifeq ($(BR2_TARGET_ARM_TRUSTED_FIRMWARE_LATEST_VERSION),y)
 ARM_TRUSTED_FIRMWARE_LICENSE = BSD-3-Clause
 ARM_TRUSTED_FIRMWARE_LICENSE_FILES = license.rst
 endif
-endif
 
 ifeq ($(BR2_TARGET_ARM_TRUSTED_FIRMWARE)$(BR2_TARGET_ARM_TRUSTED_FIRMWARE_LATEST_VERSION),y)
 BR_NO_CHECK_HASH_FOR += $(ARM_TRUSTED_FIRMWARE_SOURCE)

buildroot/configs/raspberrypi3_64_defconfig

@@ -17,6 +17,7 @@ BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi3"
 # Build the DTB from the kernel sources
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="broadcom/bcm2710-rpi-3-b broadcom/bcm2710-rpi-3-b-plus broadcom/bcm2837-rpi-3-b"
+BR2_LINUX_KERNEL_DTB_OVERLAY_SUPPORT=y
 
 BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
 

buildroot/configs/raspberrypi4_64_defconfig

@@ -17,6 +17,7 @@ BR2_LINUX_KERNEL_DEFCONFIG="bcm2711"
 # Build the DTB from the kernel sources
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="broadcom/bcm2711-rpi-4-b"
+BR2_LINUX_KERNEL_DTB_OVERLAY_SUPPORT=y
 
 BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
 

buildroot/docs/manual/manual.text

@@ -143,19 +143,15 @@ III. Developer guide
         21.7. Using the run-tests framework
 
     22. DEVELOPERS file and get-developers
-    23. Release Engineering
-
-        23.1. Releases
-        23.2. Development
 
 IV. Appendix
 
-    24. Makedev syntax documentation
-    25. Makeusers syntax documentation
-    26. Migrating from older Buildroot versions
+    23. Makedev syntax documentation
+    24. Makeusers syntax documentation
+    25. Migrating from older Buildroot versions
 
-        26.1. Migrating to 2016.11
-        26.2. Migrating to 2017.08
+        25.1. Migrating to 2016.11
+        25.2. Migrating to 2017.08
 
 List of Examples
 
@@ -167,13 +163,13 @@ List of Examples
 
 ---------------------------------------------------------------------
 
-Buildroot 2020.02.3 manual generated on 2020-06-03 14:56:43 UTC from
-git revision d42f3adaae
+Buildroot 2020.02.2 manual generated on 2020-05-12 12:18:45 UTC from
+git revision 2f7183d131
 
 The Buildroot manual is written by the Buildroot developers. It is
 licensed under the GNU General Public License, version 2. Refer to
 the COPYING [http://git.buildroot.org/buildroot/tree/COPYING?id=
-d42f3adaae24a6aa3abc2de4f39fa8023f971d31] file in the Buildroot
+2f7183d13133f2ded97fee273bd0cbed10226e4e] file in the Buildroot
 sources for the full text of this license.
 
 Copyright © 2004-2020 The Buildroot developers
@@ -882,7 +878,7 @@ different solutions to handle the /dev directory :
     BR2_ROOTFS_STATIC_DEVICE_TABLE to system/device_table_dev.txt
     board/<yourcompany>/<yourproject>/device_table_dev.txt. For more
     details about the format of the device table file, see
-    Chapter 24, Makedev syntax documentation.
+    Chapter 23, Makedev syntax documentation.
   * The second solution is Dynamic using devtmpfs only. devtmpfs is a
     virtual filesystem inside the Linux kernel that has been
     introduced in kernel 2.6.32 (if you use an older kernel, it is
@@ -2177,7 +2173,7 @@ directory, not to the Buildroot output directory.
 
 Note: If using an br2-external tree from before Buildroot 2016.11,
 you need to convert it before you can use it with Buildroot 2016.11
-onward. See Section 26.1, “Migrating to 2016.11” for help on doing
+onward. See Section 25.1, “Migrating to 2016.11” for help on doing
 so.
 
 Some examples:
@@ -3474,10 +3470,6 @@ Table of Contents
     21.7. Using the run-tests framework
 
 22. DEVELOPERS file and get-developers
-23. Release Engineering
-
-    23.1. Releases
-    23.2. Development
 
 Chapter 14. How Buildroot works
 
@@ -4603,17 +4595,17 @@ information is (assuming the package name is libfoo) :
   * LIBFOO_DEVICES lists the device files to be created by Buildroot
     when using the static device table. The syntax to use is the
     makedevs one. You can find some documentation for this syntax in
-    the Chapter 24, Makedev syntax documentation. This variable is
+    the Chapter 23, Makedev syntax documentation. This variable is
     optional.
   * LIBFOO_PERMISSIONS lists the changes of permissions to be done at
     the end of the build process. The syntax is once again the
     makedevs one. You can find some documentation for this syntax in
-    the Chapter 24, Makedev syntax documentation. This variable is
+    the Chapter 23, Makedev syntax documentation. This variable is
     optional.
   * LIBFOO_USERS lists the users to create for this package, if it
     installs a program you want to run as a specific user (e.g. as a
     daemon, or as a cron-job). The syntax is similar in spirit to the
-    makedevs one, and is described in the Chapter 25, Makeusers
+    makedevs one, and is described in the Chapter 24, Makeusers
     syntax documentation. This variable is optional.
   * LIBFOO_LICENSE defines the license (or licenses) under which the
     package is released. This name will appear in the manifest file
@@ -7822,50 +7814,18 @@ DEVELOPERS file for various tasks:
     the DEVELOPERS file and will note WARNINGS for items that don’t
     match.
 
-Chapter 23. Release Engineering
-
-23.1. Releases
-
-The Buildroot project makes quarterly releases with monthly bugfix
-releases. The first release of each year is a long term support
-release, LTS.
-
-  * Quarterly releases: 2020.02, 2020.05, 2020.08, and 2020.11
-  * Bugfix releases: 2020.02.1, 2020.02.2, …
-  * LTS releases: 2020.02, 2021.02, …
-
-Releases are supported until the first bugfix release of the next
-release, e.g., 2020.05.x is EOL when 2020.08.1 is released.
-
-LTS releases are supported until the first bugfix release of the next
-LTS, e.g., 2020.02.x is supported until 2021.02.1 is released.
-
-23.2. Development
-
-Each release cycle consist of two months of development on the master
-branch and one month stabilization before the release is made. During
-this phase no new features are added to master, only bugfixes.
-
-The stabilization phase starts with tagging -rc1, and every week
-until the release, another release candidate is tagged.
-
-To handle new features and version bumps during the stabilization
-phase, a next branch may be created for these features. Once the
-current release has been made, the next branch is merged into master
-and the development cycle for the next release continues there.
-
 Part IV. Appendix
 
 Table of Contents
 
-24. Makedev syntax documentation
-25. Makeusers syntax documentation
-26. Migrating from older Buildroot versions
+23. Makedev syntax documentation
+24. Makeusers syntax documentation
+25. Migrating from older Buildroot versions
 
-    26.1. Migrating to 2016.11
-    26.2. Migrating to 2017.08
+    25.1. Migrating to 2016.11
+    25.2. Migrating to 2017.08
 
-Chapter 24. Makedev syntax documentation
+Chapter 23. Makedev syntax documentation
 
 The makedev syntax is used in several places in Buildroot to define
 changes to be made for permissions, or which device files to create
@@ -7954,7 +7914,7 @@ cap_net_admin to the binary foo, you will write :
 |xattr cap_sys_admin+eip
 |xattr cap_net_admin+eip
 
-Chapter 25. Makeusers syntax documentation
+Chapter 24. Makeusers syntax documentation
 
 The syntax to create users is inspired by the makedev syntax, above,
 but is specific to Buildroot.
@@ -8039,13 +7999,13 @@ This will create this user:
   * test is not a member of any additional groups
   * comment is: Test user
 
-Chapter 26. Migrating from older Buildroot versions
+Chapter 25. Migrating from older Buildroot versions
 
 Some versions have introduced backward incompatibilities. This
 section explains those incompatibilities, and for each explains what
 to do to complete the migration.
 
-26.1. Migrating to 2016.11
+25.1. Migrating to 2016.11
 
 Before Buildroot 2016.11, it was possible to use only one
 br2-external tree at once. With Buildroot 2016.11 came the
@@ -8078,7 +8038,7 @@ onward.
 Note: This change makes your br2-external tree incompatible with
 Buildroot before 2016.11.
 
-26.2. Migrating to 2017.08
+25.2. Migrating to 2017.08
 
 Before Buildroot 2017.08, host packages were installed in $(HOST_DIR)
 /usr (with e.g. the autotools' --prefix=$(HOST_DIR)/usr). With

buildroot/docs/manual/manual.txt

@@ -66,8 +66,6 @@ include::contribute.txt[]
 
 include::developers.txt[]
 
-include::release-engineering.txt[]
-
 = Appendix
 
 include::appendix.txt[]

buildroot/docs/manual/release-engineering.txt

@@ -1,34 +0,0 @@
-// -*- mode:doc; -*-
-// vim: set syntax=asciidoc:
-
-[[RELENG]]
-== Release Engineering
-=== Releases
-
-The Buildroot project makes quarterly releases with monthly bugfix
-releases.  The first release of each year is a long term support
-release, LTS.
-
- - Quarterly releases: 2020.02, 2020.05, 2020.08, and 2020.11
- - Bugfix releases: 2020.02.1, 2020.02.2, ...
- - LTS releases: 2020.02, 2021.02, ...
-
-Releases are supported until the first bugfix release of the next
-release, e.g., 2020.05.x is EOL when 2020.08.1 is released.
-
-LTS releases are supported until the first bugfix release of the next
-LTS, e.g., 2020.02.x is supported until 2021.02.1 is released.
-
-=== Development
-
-Each release cycle consist of two months of development on the +master+
-branch and one month stabilization before the release is made.  During
-this phase no new features are added to +master+, only bugfixes.
-
-The stabilization phase starts with tagging +-rc1+, and every week until
-the release, another release candidate is tagged.
-
-To handle new features and version bumps during the stabilization phase,
-a +next+ branch may be created for these features.  Once the current
-release has been made, the +next+ branch is merged into +master+ and
-the development cycle for the next release continues there.

buildroot/linux/Config.in

@@ -128,7 +128,7 @@ endif
 
 config BR2_LINUX_KERNEL_VERSION
 	string
-	default "5.4.43" if BR2_LINUX_KERNEL_LATEST_VERSION
+	default "5.4.40" if BR2_LINUX_KERNEL_LATEST_VERSION
 	default "4.19.118-cip25" if BR2_LINUX_KERNEL_LATEST_CIP_VERSION
 	default "4.19.115-cip24-rt9" if BR2_LINUX_KERNEL_LATEST_CIP_RT_VERSION
 	default BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE \

buildroot/linux/linux.hash

@@ -1,10 +1,10 @@
 # From https://www.kernel.org/pub/linux/kernel/v5.x/sha256sums.asc
-sha256  2667b90a42d42557aca9e3d37bba1b4e71809b9523958e6870ada311c4790744  linux-5.4.43.tar.xz
+sha256  83563f027687ecaafb41d0d2d52056f40ec9822f8a9e43592e215349730020ab  linux-5.4.40.tar.xz
 # From https://www.kernel.org/pub/linux/kernel/v4.x/sha256sums.asc
-sha256  49474956a6149c16cbcba862d1f4db54835a32d336063c75094f669f1c34c65e  linux-4.4.225.tar.xz
-sha256  e547748c548b0f55f665bc78cfec322e7b96f41527b5e4b5d79430fdaa57c3e8  linux-4.9.225.tar.xz
-sha256  671d1f1d5ad0ae74fb21ee70a5544400e7d6270098d3f8b134484ded2c3e5b90  linux-4.14.182.tar.xz
-sha256  9843f40efb37491770688810d153d0779daed8eb097773a0de5abf2cb0d1bd7e  linux-4.19.125.tar.xz
+sha256  cd963e66d7fb07f142fa5274ec90f46c8388a327e2ba28c5fec245d734b0d425  linux-4.4.223.tar.xz
+sha256  cf5300e6f5d8c66c2bed8f00d53f9c58103731809862427012e4010f5d782ae5  linux-4.9.223.tar.xz
+sha256  444ef973d9b6a6ea174e4a9086f0aea980d8575d13302e431ad688f22e27ed0e  linux-4.14.180.tar.xz
+sha256  5050268ec5cf003d96366d1611ecfa4ab6974125d6fa26cea1ccb81dd4df00a5  linux-4.19.122.tar.xz
 # Locally computed
 sha256  ea53913813cb5a9069608532b327de7a7ed0fdc8fed8c6f10cd55d1ac6a58ffb  linux-cip-4.19.118-cip25.tar.gz
 sha256  7f0a0db0e1cfb14053523f4432f1ad1468b5bd42305b44905c4b103466c8d655  linux-cip-4.19.115-cip24-rt9.tar.gz

buildroot/package/Config.in

@@ -1053,6 +1053,7 @@ menu "External python modules"
 	source "package/python-pycares/Config.in"
 	source "package/python-pycli/Config.in"
 	source "package/python-pycparser/Config.in"
+	source "package/python-pycrypto/Config.in"
 	source "package/python-pycryptodomex/Config.in"
 	source "package/python-pydal/Config.in"
 	source "package/python-pydantic/Config.in"

buildroot/package/audit/0003-Header-definitions-need-to-be-external-when-building.patch

@@ -1,28 +0,0 @@
-From 017e6c6ab95df55f34e339d2139def83e5dada1f Mon Sep 17 00:00:00 2001
-From: Steve Grubb <sgrubb@redhat.com>
-Date: Fri, 10 Jan 2020 21:13:50 -0500
-Subject: [PATCH] Header definitions need to be external when building with
- -fno-common (which is default in GCC 10) - Tony Jones
-
-Patch taken from upstream: https://github.com/linux-audit/audit-userspace/commit/017e6c6ab95df55f34e339d2139def83e5dada1f
-Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
----
- src/ausearch-common.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/ausearch-common.h b/src/ausearch-common.h
-index 6669203..3040547 100644
---- a/src/ausearch-common.h
-+++ b/src/ausearch-common.h
-@@ -50,7 +50,7 @@ extern pid_t event_pid;
- extern int event_exact_match;
- extern uid_t event_uid, event_euid, event_loginuid;
- extern const char *event_tuid, *event_teuid, *event_tauid;
--slist *event_node_list;
-+extern slist *event_node_list;
- extern const char *event_comm;
- extern const char *event_filename;
- extern const char *event_hostname;
--- 
-2.20.1
-

buildroot/package/bind/bind.hash

@@ -1,4 +1,4 @@
-# Verified from https://ftp.isc.org/isc/bind9/9.11.19/bind-9.11.19.tar.gz.asc
+# Verified from https://ftp.isc.org/isc/bind9/9.11.13/bind-9.11.13.tar.gz.asc
 # with key AE3FAC796711EC59FC007AA474BB6B9A4CBB3D38
-sha256  0dee554a4caa368948b32da9a0c97b516c19103bc13ff5b3762c5d8552f52329  bind-9.11.19.tar.gz
-sha256  da2aec2b7f6f0feb16bcb080e2c587375fd3195145f047e4d92d112f5b9db501  COPYRIGHT
+sha256 fd3f3cc9fcfcdaa752db35eb24598afa1fdcc2509d3227fc90a8631b7b400f7d bind-9.11.13.tar.gz
+sha256 cd02c93b8dcda794f55dfd1231828d69633072a98eee4874f9cf732d22d9dcde COPYRIGHT

buildroot/package/bind/bind.mk

@@ -4,7 +4,7 @@
 #
 ################################################################################
 
-BIND_VERSION = 9.11.19
+BIND_VERSION = 9.11.13
 BIND_SITE = https://ftp.isc.org/isc/bind9/$(BIND_VERSION)
 # bind does not support parallel builds.
 BIND_MAKE = $(MAKE1)

buildroot/package/binutils/binutils.mk

@@ -112,7 +112,6 @@ endef
 ifneq ($(BR2_PACKAGE_BINUTILS_TARGET),y)
 define BINUTILS_INSTALL_TARGET_CMDS
 	$(TARGET_MAKE_ENV) $(MAKE) -C $(@D)/bfd DESTDIR=$(TARGET_DIR) install
-	$(TARGET_MAKE_ENV) $(MAKE) -C $(@D)/opcodes DESTDIR=$(TARGET_DIR) install
 	$(TARGET_MAKE_ENV) $(MAKE) -C $(@D)/libiberty DESTDIR=$(STAGING_DIR) install
 endef
 endif

buildroot/package/bison/0001-src-make-path-to-m4-relocatable.patch

@@ -1,70 +0,0 @@
-From 50c8a3af1661c3950b9743d673fd46872860aa08 Mon Sep 17 00:00:00 2001
-From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Date: Mon, 18 May 2020 07:53:20 +0200
-Subject: [PATCH] src: make path to m4 relocatable
-
-Commit a4ede8f85b0c9a254fcb01e5888cee1983095669 ("package: make bison
-a relocatable package") made Bison relocatable, but in fact it still
-contains one absolute reference: the M4 variable, which points to the
-M4 program. Let's fix that by using relocate().
-
-We don't use relocate2() to store the temporary buffer and re-use it,
-because m4path() is only called once.
-
-Upstream: submitted to the bison-patches@gnu.org mailing list
-https://lists.gnu.org/archive/html/bison-patches/2020-05/msg00078.html
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
----
- src/files.c  | 7 +++++++
- src/files.h  | 3 +++
- src/output.c | 2 +-
- 3 files changed, 11 insertions(+), 1 deletion(-)
-
-diff --git a/src/files.c b/src/files.c
-index 71c10e34..b8b43230 100644
---- a/src/files.c
-+++ b/src/files.c
-@@ -421,6 +421,13 @@ pkgdatadir (void)
-     }
- }
- 
-+char const *
-+m4path (void)
-+{
-+  char const *m4 = getenv("M4");
-+  return m4 ? m4 : relocate(M4);
-+}
-+
- void
- output_file_names_free (void)
- {
-diff --git a/src/files.h b/src/files.h
-index 00814ad0..64b6f8b5 100644
---- a/src/files.h
-+++ b/src/files.h
-@@ -64,6 +64,9 @@ extern char *all_but_ext;
- /* Where our data files are installed.  */
- char const *pkgdatadir (void);
- 
-+/* Where the m4 program is installed.  */
-+char const *m4path (void);
-+
- void compute_output_file_names (void);
- void output_file_names_free (void);
- 
-diff --git a/src/output.c b/src/output.c
-index 1871fd75..ebe75095 100644
---- a/src/output.c
-+++ b/src/output.c
-@@ -682,7 +682,7 @@ static void
- output_skeleton (void)
- {
-   /* Compute the names of the package data dir and skeleton files.  */
--  char const *m4 = (m4 = getenv ("M4")) ? m4 : M4;
-+  char const *m4 = m4path ();
-   char const *datadir = pkgdatadir ();
-   char *skeldir = xpath_join (datadir, "skeletons");
-   char *m4sugar = xpath_join (datadir, "m4sugar/m4sugar.m4");
--- 
-2.26.2
-

buildroot/package/bison/bison.mk

@@ -12,6 +12,5 @@ BISON_LICENSE_FILES = COPYING
 # parallel build issue in examples/c/reccalc/
 BISON_MAKE = $(MAKE1)
 HOST_BISON_DEPENDENCIES = host-m4
-HOST_BISON_CONF_OPTS = --enable-relocatable
 
 $(eval $(host-autotools-package))

buildroot/package/clamav/clamav.hash

@@ -1,14 +1,14 @@
 # Locally calculated
-sha256  ed3050c4569989ee7ab54c7b87246b41ed808259632849be0706467442dc0693  clamav-0.102.3.tar.gz
-sha256  0c4fd2fa9733fc9122503797648710851e4ee6d9e4969dd33fcbd8c63cd2f584  COPYING
-sha256  d72a145c90918184a05ef65a04c9e6f7466faa59bc1b82c8f6a8ddc7ddcb9bed  COPYING.bzip2
-sha256  dfb818a0d41411c6fb1c193c68b73018ceadd1994bda41ad541cbff292894bc6  COPYING.file
-sha256  6dce638b76399e7521ad8e182d3e33e4496c85b3b69b6ff434b53017101e82ad  COPYING.getopt
-sha256  a9bdde5616ecdd1e980b44f360600ee8783b1f99b8cc83a2beb163a0a390e861  COPYING.LGPL
-sha256  e3a9b913515a42f8ff3ef1551c3a2cdba383c39ed959729e0e2911219496ad74  COPYING.llvm
-sha256  d96d71b66aa32c4a2d1619b9ca3347dafa9460bcf0fb5ac2408916067ad31dfc  COPYING.lzma
-sha256  accdcf2455c07b99abea59016b3663eaef926a92092d103bfaa25fed27cf6b24  COPYING.pcre
-sha256  e2c1395a3d9fea6d5d25847c9d783db6e2cc8b085b4025861f459139c5dfd90b  COPYING.regex
-sha256  1faccc6b5c7b958fb807a3f573d5be9bf7889fe898f7e0617c544b05a81bfd00  COPYING.unrar
-sha256  a20d6317c5384e8d4c05f9c31097878675d9429ec46090656166039cc10bc957  COPYING.YARA
-sha256  c2f77553f8d870c5635b0dace0519253233f172b33ce1fdf6578610706294eee  COPYING.zlib
+sha256 89fcdcc0eba329ca84d270df09d2bb89ae55f5024b0c3bddb817512fb2c907d3  clamav-0.102.2.tar.gz
+sha256 0c4fd2fa9733fc9122503797648710851e4ee6d9e4969dd33fcbd8c63cd2f584  COPYING
+sha256 d72a145c90918184a05ef65a04c9e6f7466faa59bc1b82c8f6a8ddc7ddcb9bed  COPYING.bzip2
+sha256 dfb818a0d41411c6fb1c193c68b73018ceadd1994bda41ad541cbff292894bc6  COPYING.file
+sha256 6dce638b76399e7521ad8e182d3e33e4496c85b3b69b6ff434b53017101e82ad  COPYING.getopt
+sha256 a9bdde5616ecdd1e980b44f360600ee8783b1f99b8cc83a2beb163a0a390e861  COPYING.LGPL
+sha256 e3a9b913515a42f8ff3ef1551c3a2cdba383c39ed959729e0e2911219496ad74  COPYING.llvm
+sha256 d96d71b66aa32c4a2d1619b9ca3347dafa9460bcf0fb5ac2408916067ad31dfc  COPYING.lzma
+sha256 accdcf2455c07b99abea59016b3663eaef926a92092d103bfaa25fed27cf6b24  COPYING.pcre
+sha256 e2c1395a3d9fea6d5d25847c9d783db6e2cc8b085b4025861f459139c5dfd90b  COPYING.regex
+sha256 1faccc6b5c7b958fb807a3f573d5be9bf7889fe898f7e0617c544b05a81bfd00  COPYING.unrar
+sha256 a20d6317c5384e8d4c05f9c31097878675d9429ec46090656166039cc10bc957  COPYING.YARA
+sha256 c2f77553f8d870c5635b0dace0519253233f172b33ce1fdf6578610706294eee  COPYING.zlib

buildroot/package/clamav/clamav.mk

@@ -4,7 +4,7 @@
 #
 ################################################################################
 
-CLAMAV_VERSION = 0.102.3
+CLAMAV_VERSION = 0.102.2
 CLAMAV_SITE = https://www.clamav.net/downloads/production
 CLAMAV_LICENSE = GPL-2.0
 CLAMAV_LICENSE_FILES = COPYING COPYING.bzip2 COPYING.file COPYING.getopt \

buildroot/package/crda/0001-crda-support-python-3-in-utils-key2pub.py.patch

@@ -1,11 +1,11 @@
-From 8228c484a1533ff904b276c342adcb6310abe272 Mon Sep 17 00:00:00 2001
+From 4c346aa9e816bddfedc8ac99809fd1ed91bfc8ee Mon Sep 17 00:00:00 2001
 From: Taahir Ahmed <ahmed.taahir@gmail.com>
 Date: Wed, 30 Mar 2016 11:23:54 -0300
 Subject: [PATCH] crda: support python 3 in utils/key2pub.py
 
 utils/key2pub.py can now be run under either python 2.7 or python 3.x.
 This required some minor syntactical changes as well as switching from
-M2Crypto to pycryptodomex, since M2Crypto doesn't support python 3.x.
+M2Crypto to pycrypto, since M2Crypto doesn't support python 3.x.
 
 In addition, some errors in the generated source file keys-ssl.h are
 fixed:
@@ -17,22 +17,12 @@ fixed:
 
 [Gustavo: don't call /utils/key2pub.py since that doesn't compute]
 
-Use pycryptodomex insdead of pycrypto
-
-From [1]:
-"PyCryptodome is a fork of PyCrypto, which is not maintained any more
-(the last release dates back to 2013 [2]). It exposes almost the same
-API, but there are a few incompatibilities [3]."
-
-[1] https://github.com/OP-TEE/optee_os/commit/90ad2450436fdd9fc0d28a3f92f3fbcfd89a38f0
-[2] https://pypi.org/project/pycrypto/#history
-[3] https://pycryptodome.readthedocs.io/en/latest/src/vs_pycrypto.html
-
 Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar>
 [Rebased against crda-4.14]
 Signed-off-by: Peter Seiderer <ps.report@gmx.net>
-[Romain: Use pycryptodomex]
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
+---
+Status: submitted upstream by author but not (yet) accepted
+URL: http://www.spinics.net/lists/linux-wireless/msg138936.html
 ---
  Makefile         |   2 +-
  utils/key2pub.py | 146 ++++++++++++++++++++++++-----------------------
@@ -52,7 +42,7 @@ index a3ead30..8da38d0 100644
  $(LIBREG): regdb.h reglib.h reglib.c
  	$(NQ) '  CC  ' $@
 diff --git a/utils/key2pub.py b/utils/key2pub.py
-index 9bb04cd..8a0ba2a 100755
+index 9bb04cd..9f92ebd 100755
 --- a/utils/key2pub.py
 +++ b/utils/key2pub.py
 @@ -1,126 +1,128 @@
@@ -67,11 +57,11 @@ index 9bb04cd..8a0ba2a 100755
 -       sys.stderr.write('Please install the "M2Crypto" Python module.\n')
 -       sys.stderr.write('On Debian GNU/Linux the package is called "python-m2crypto".\n')
 -       sys.exit(1)
-+    from Cryptodome.PublicKey import RSA
++    from Crypto.PublicKey import RSA
 +except ImportError as e:
-+    sys.stderr.write('ERROR: Failed to import the "Cryptodome.PublicKey" module: %s\n' % e.message)
-+    sys.stderr.write('Please install the "Cryptodome.PublicKey" Python module.\n')
-+    sys.stderr.write('On Debian GNU/Linux the package is called "python-cryptodomex".\n')
++    sys.stderr.write('ERROR: Failed to import the "Crypto.PublicKey" module: %s\n' % e.message)
++    sys.stderr.write('Please install the "Crypto.PublicKey" Python module.\n')
++    sys.stderr.write('On Debian GNU/Linux the package is called "python-crypto".\n')
 +    sys.exit(1)
 +
 +def bitwise_collect(value, radix_bits):
@@ -279,5 +269,5 @@ index 9bb04cd..8a0ba2a 100755
  
  modes[mode][1](output, idx - 1)
 -- 
-2.25.3
+2.18.0
 

buildroot/package/crda/crda.mk

@@ -6,7 +6,7 @@
 
 CRDA_VERSION = 4.14
 CRDA_SITE = https://git.kernel.org/pub/scm/linux/kernel/git/mcgrof/crda.git/snapshot
-CRDA_DEPENDENCIES = host-pkgconf host-python-pycryptodomex libnl libgcrypt
+CRDA_DEPENDENCIES = host-pkgconf host-python-pycrypto libnl libgcrypt
 CRDA_LICENSE = ISC
 CRDA_LICENSE_FILES = LICENSE
 

buildroot/package/dovecot/0001-byteorder.h-fix-uclibc-build.patch

@@ -0,0 +1,32 @@
+From 902917880ca29f1007750a70cf46e7246b2d0a2a Mon Sep 17 00:00:00 2001
+From: Josef 'Jeff' Sipek <jeff.sipek@dovecot.fi>
+Date: Tue, 14 Nov 2017 06:01:21 +0100
+Subject: [PATCH] byteorder.h: fix uclibc build
+
+Patch suggested on upstream mailinglist:
+https://www.dovecot.org/pipermail/dovecot/2017-November/110019.html
+
+Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
+---
+ src/lib/byteorder.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/lib/byteorder.h b/src/lib/byteorder.h
+index 2f5dc7c17..4ffe8da21 100644
+--- a/src/lib/byteorder.h
++++ b/src/lib/byteorder.h
+@@ -23,6 +23,11 @@
+ #ifndef BYTEORDER_H
+ #define BYTEORDER_H
+ 
++#undef bswap_8
++#undef bswap_16
++#undef bswap_32
++#undef bswap_64
++
+ /*
+  * These prototypes exist to catch bugs in the code generating macros below.
+  */
+-- 
+2.11.0
+

buildroot/package/dovecot/0002-lib-ssl-iostream-Do-not-build-static-test-iostream-s.patch

@@ -0,0 +1,30 @@
+From 40851dc3471809cabe8cc3f9b71980f8d82344ae Mon Sep 17 00:00:00 2001
+From: Bernd Kuhls <bernd.kuhls@t-online.de>
+Date: Sat, 4 Jan 2020 14:39:39 +0100
+Subject: [PATCH] lib-ssl-iostream: Do not build static test-iostream-ssl
+
+Fixes broken static build:
+https://dovecot.org/pipermail/dovecot/2019-October/117326.html
+
+Patch sent upstream: https://github.com/dovecot/core/pull/111
+
+Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
+---
+ src/lib-ssl-iostream/Makefile.am | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/src/lib-ssl-iostream/Makefile.am b/src/lib-ssl-iostream/Makefile.am
+index 94ead5cec..5aaea5d51 100644
+--- a/src/lib-ssl-iostream/Makefile.am
++++ b/src/lib-ssl-iostream/Makefile.am
+@@ -46,7 +46,6 @@ test_libs = \
+ 	../lib/liblib.la
+ 
+ test_iostream_ssl_SOURCES = test-iostream-ssl.c
+-test_iostream_ssl_LDFLAGS = -static
+ test_iostream_ssl_LDADD = $(test_libs) $(SSL_LIBS) $(DLLIB)
+ test_iostream_ssl_DEPENDENCIES = $(test_libs)
+ 
+-- 
+2.20.1
+