Revert "Use Microsoft Basic Data instead of Microsoft Reserved Partition (#847)" (#852)

This reverts commit 31bb38ffd4.

.github/ISSUE_TEMPLATE.md

@@ -1,21 +1,23 @@
 <!-- READ THIS FIRST:
 - If you need additional help with this template please refer to https://www.home-assistant.io/help/reporting_issues/
-- Make sure you are running the latest version before reporting an issue: https://github.com/home-assistant/home-assistant/releases
-- Do not report issues for components here, plaese refer to https://github.com/home-assistant/home-assistant/issues
+- Make sure you are running the latest version before reporting an issue: https://github.com/home-assistant/core/releases
+- Do not report issues for integrations here, please refer to https://github.com/home-assistant/core/issues
 - This is for bugs only. Feature and enhancement requests should go in our community forum: https://community.home-assistant.io/c/feature-requests
 - Provide as many details as possible. Paste logs, configuration sample and code into the backticks. Do not delete any text from this template!
-- If you have a problem with a Add-on, make a issue on there repository.
+- If you have a problem with an add-on, make an issue in its repository.
+- If you are using Raspberry Pi overlays in config.txt and your system doesn't work anymore please report this to the Raspberry Pi kernel project.
+
 -->
 
 **HassOS release with the issue:**
 <!--
-- Frontend -> Developer tools -> Info
+- Frontend -> Configuration -> Info
 - Or use this command: hass --version
 -->
 
 **Supervisor logs:**
 <!--
-- Frontend -> Hass.io -> System
+- Frontend -> Supervisor -> System
 - Or use this command: ha su logs
 -->
 

Documentation/README.md

@@ -3,7 +3,7 @@
 ## Contents
 
 - [Getting started](./getting_started_development.md) - the place for developers to begin
-- [Development](./getting_started_development.md) - more deatils for developers
+- [Development](./development.md) - more details for developers
 - [Deployment](./deployment.md) - approach to git branching and releases
 - [Configuration](./configuration.md) - how users can configure HassOS
 - [Partition](./partition.md) - partition layout

Documentation/boards/asus/README.md

@@ -5,16 +5,26 @@
 | Device         | Release Date  | Support | Config   |
 |----------------|---------------|---------|----------|
 | Tinker RK3288  | April 2017    | yes     | [tinker](../../../buildroot-external/configs/tinker_defconfig) |
-| Tinker S RK3288| January 2018  | yes?    | [tinker](../../../buildroot-external/configs/tinker_defconfig)? |
+| Tinker S RK3288| January 2018  | yes     | [tinker](../../../buildroot-external/configs/tinker_defconfig) |
 | Tinker Edge T  | November 2019 | no?     |          |
 | Tinker Edge R  | November 2019 | no?     |          |
 
-(? is the Tinker S supported?)
-<!--
 ## eMMC
 
-eMMC support is provided transparently. Just flash the image to the eMMC by connecting your Tinker Board S to your PC via Micro-USB.
--->
+eMMC support is provided with the same image. Just flash the image to the eMMC by connecting your Tinker Board S to your PC via Micro-USB. Refer to the Tinkerboard documentation how-to flash using Micro-USB and UMS.
+
+The Home Assistant OS provided U-Boot does support UMS as well,
+however manual intervention is necessary:
+
+ 1. Set the jumper between Micro-USB and HDMI the maskrom mode
+ 2. Insert SD card and connect the board via Micro-USB to your PC
+ 3. Continusly press Ctrl+C to interrupt boot
+ 4. Set the jumper back to the park position
+ 5. Start UMS using:
+```
+ums 0 mmc 0
+```
+ 6. A mass storage device should appear. Flash Home Assistant OS to it.
 
 ## Serial console
 

Documentation/boards/raspberrypi/README.md

@@ -33,8 +33,13 @@ i2c-bcm2708
 
 ## USB Boot
 
-USB mass storage boot is available on Raspberry Pi 3B, 3B+, 3A+, and 2B v1.2.
-To enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
+USB mass storage boot is available on Raspberry Pi 4 (64-bit only), 3B, 3B+, 3A+, and 2B v1.2.
+
+For Raspberry 3B, 3A+ and 2B v1.2, to enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
+
+For Raspberry 4, make sure to update the bootloader to a stable release
+supporting USB mass storage boot (see
+[bcm2711_bootloader_config.md](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711_bootloader_config.md#usbmassstorageboot). If no SD card is used add `sd_poll_once=on` to `dtparam` in `config.txt` (comma separated). This gets rid of `mmc0: timeout waiting for hardware interrupt` kernel errors.
 
 For more information see [RaspberryPi](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/msd.md).
 

Documentation/configuration.md

@@ -59,4 +59,4 @@ FallbackNTP=0.pool.ntp.org 1.pool.ntp.org 2.pool.ntp.org 3.pool.ntp.org
 [systemd-modules]: https://www.freedesktop.org/software/systemd/man/modules-load.d.html
 [network.md]: network.md
 [hassos-release]: https://github.com/home-assistant/hassos/releases/
-[debug-homeassistant]: https://developers.home-assistant.io/docs/en/hassio_debugging.html
+[debug-homeassistant]: https://developers.home-assistant.io/docs/operating-system/debugging

Documentation/deployment.md

@@ -2,8 +2,8 @@
 
 We provide 3 different types of release builds:
 
-- development (beta/dev)
-- staging (rc)
+- development (dev)
+- staging (beta)
 - production (stable)
 
 ## Versioning
@@ -15,7 +15,7 @@ The development number they will be bump for the stable release version and the
 
 The branch `dev` ist the actual development branch and from there we never make a release. The `master` branch contains the development version and from there we build a beta release.
 
-If we create a new productive release, we create a new branch `rel-{MAJOR}`. They will be used for the whole cycle of this release.
+If we create a new productive/staging release, we create a new branch `rel-{MAJOR}`. They will be used for the whole cycle of this release.
 
 ## Upload release files
 

Documentation/kernel.md

@@ -5,14 +5,14 @@ Default Kernel tree: 5.4
 
 | Board | Version |
 |-------|---------|
-| Open Virtual Appliance | 5.4.72 |
+| Open Virtual Appliance | 5.4.63 |
 | Raspberry Pi | 4.19.127 |
 | Raspberry Pi 0-W | 4.19.127 |
 | Raspberry Pi 2 | 4.19.127 |
 | Raspberry Pi 3 | 4.19.127 |
 | Raspberry Pi 4 | 4.19.127 |
-| Tinker Board | 5.4.72 |
+| Tinker Board | 5.4.63 |
 | Odroid-C2 | 5.7.19 |
 | Odroid-N2 | 5.7.19 |
 | Odroid-XU4 | 5.7.19 |
-| Intel NUC | 5.4.72 |
+| Intel NUC | 5.4.63 |

Documentation/network.md

@@ -1,6 +1,6 @@
 # Network
 
-HassOS uses NetworkManager to control the host network.
+Home Assistant Operating System uses NetworkManager to control the host network.
 
 ## Configure network
 
@@ -148,6 +148,6 @@ If you now view the default connection `cat /etc/NetworkManager/system-connectio
 
 Doing a `nmcli con reload` does not always work, so restart the virtual machine or the physical system.
 
-[nm-manual]: https://developer.gnome.org/NetworkManager/stable/nm-settings.html
+[nm-manual]: https://developer.gnome.org/NetworkManager/stable/NetworkManager.conf.html
 [configuration-usb]: configuration.md
 [uuid]: https://www.uuidgenerator.net/

Documentation/partition.md

@@ -1,6 +1,6 @@
 # Partition
 
-The partition layout is a bit different than for regular setups. We prefer GPT, if possible. With SoCs which don't support GPT, we use the hybrid GPT. For more details about this topic, please refer to the [development](development.mnd) documentation.
+The partition layout is a bit different than for regular setups. We prefer GPT, if possible. With SoCs which don't support GPT, we use the hybrid GPT. For more details about this topic, please refer to the [development](development.md) documentation.
 
 The system is designed to have as less as possible write operations on the storage media. Which means that we have basically only write during the OTA update and 5-6 times per week on the overlay part. The data partition is having I/O. This is the reason which is should be run on a different drive.
 
@@ -36,12 +36,33 @@ Sometime the bootloader part can look different because there can be firmware or
 
 ## Data
 
-The data partition is the only partition with real I/O. It will be expanded automatic on boot time to the full size of the disk.
+The data partition is the only partition with real I/O. It will be expanded automatically at boot to the full size of the disk.
 
-This partition can be offloaded to a different drive with the utility:
+
+## Using datactl to move the data partition.
+
+In a Home Assistant OS installation, the data is stored on the `/mnt/data` partition of the SD card. This is the only read+write partition on the SD drive. Using the `datactl` move command, this partition can be moved off of the SD card onto an externally connected drive, leaving the rest of the read-only system on the SD.
+
+The storage capacity of the external drive must be larger than the storage capacity of the existing SD card.
+
+The command needs to be run from the host console by either connecting a keyboard and monitor or making use of the [debug ssh access](https://developers.home-assistant.io/docs/operating-system/debugging/) over port 22222. The command will not work from within an SSH add-on container.
+
+Log in as `root` to get to the Home Assistant CLI and then enter `login` to continue to the host.
+
+Confirm your USB SSD/HD is connected and recognized using `fdisk -l`.
+
+It is recommended to use fdisk to remove the existing partition(s) before proceeding.
+
+- Type `fdisk /dev/XXX` (replacing XXX with your drive)
+- Type `d` to delete a partition.
+- Continue if needed, then write the changes.
+
+Creating a new partition is not necessary.
+
+With the drive now prepared, use the below command (again, replacing XXX with your drive)
 
 ```sh
 $ datactl move /dev/xxx
 ```
 
-On next boot, the partition will be moved to the new drive. The drive needs to be bigger as the old one and we own the full new drive.
+Hit any key to continue, and then the move will happen after the next reboot. Once complete, the external drive will be owned and used by the system.

Makefile

@@ -7,6 +7,13 @@ DEFCONFIG_DIR = $(BUILDROOT_EXTERNAL)/configs
 TARGETS := $(notdir $(patsubst %_defconfig,%,$(wildcard $(DEFCONFIG_DIR)/*_defconfig)))
 TARGETS_CONFIG := $(notdir $(patsubst %_defconfig,%-config,$(wildcard $(DEFCONFIG_DIR)/*_defconfig)))
 
+# Set O variable if not already done on the command line
+ifneq ("$(origin O)", "command line")
+O := $(BUILDROOT)/output
+else
+override O := $(BUILDROOT)/$(O)
+endif
+
 .NOTPARALLEL: $(TARGETS) $(TARGETS_CONFIG) all
 
 .PHONY: $(TARGETS) $(TARGETS_CONFIG) all clean help
@@ -23,7 +30,7 @@ $(TARGETS_CONFIG): %-config:
 $(TARGETS): %: $(RELEASE_DIR) %-config
 	@echo "build $@"
 	$(MAKE) -C $(BUILDROOT) BR2_EXTERNAL=$(BUILDROOT_EXTERNAL)
-	cp -f $(BUILDROOT)/output/images/hassos_* $(RELEASE_DIR)/
+	cp -f $(O)/images/hassos_* $(RELEASE_DIR)/
 
 	# Do not clean when building for one target
 ifneq ($(words $(filter $(TARGETS),$(MAKECMDGOALS))), 1)

buildroot-external/board/asus/hassos-hook.sh

@@ -7,20 +7,16 @@ function hassos_pre_image() {
 
     cp -t "${BOOT_DATA}" \
         "${BINARIES_DIR}/boot.scr" \
-        "${BINARIES_DIR}/rk3288-tinker.dtb"
+        "${BINARIES_DIR}/rk3288-tinker.dtb" \
+        "${BINARIES_DIR}/rk3288-tinker-s.dtb"
 
     echo "console=tty1" > "${BOOT_DATA}/cmdline.txt"
 
-    # Create boot binary
-    rm -f "${BINARIES_DIR}/idbloader.img"
-    mkimage -n rk3288 -T rksd -d "${BINARIES_DIR}/u-boot-tpl.bin" "${BINARIES_DIR}/idbloader.img"
-    cat "${BINARIES_DIR}/u-boot-spl.bin" >> "${BINARIES_DIR}/idbloader.img"
-
     # SPL
     create_spl_image
 
     dd if="${BINARIES_DIR}/idbloader.img" of="${SPL_IMG}" conv=notrunc bs=512 seek=64
-    dd if="${BINARIES_DIR}/u-boot-dtb.img" of="${SPL_IMG}" conv=notrunc bs=512 seek=12288
+    dd if="${BINARIES_DIR}/u-boot-dtb.img" of="${SPL_IMG}" conv=notrunc bs=512 seek=8192
 }
 
 

buildroot-external/board/asus/tinker/patches/linux/0001-ARM-DTS-rk3288-tinker-Setup-the-Bluetooth-UART-pins.patch

@@ -1,7 +1,8 @@
-From 2c2e60256f2cbb2fce50a6317f85b1500efd1a6c Mon Sep 17 00:00:00 2001
+From 2ae3821fd824560ef2db3c87cfbec985177911f6 Mon Sep 17 00:00:00 2001
+Message-Id: <2ae3821fd824560ef2db3c87cfbec985177911f6.1599249626.git.stefan@agner.ch>
 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
 Date: Mon, 5 Nov 2018 22:03:26 +0100
-Subject: [PATCH] ARM: DTS: rk3288-tinker: Setup the Bluetooth UART pins
+Subject: [PATCH 1/2] ARM: DTS: rk3288-tinker: Setup the Bluetooth UART pins
 
 The most essential being the RTS pin, which is clearly needed to
 upload the initial configuration into the Realtek Bluetooth
@@ -39,24 +40,25 @@ echo 1 > value &&
 sleep 1
 
 Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+[move change to rk3288-tinker.dtsi]
+Signed-off-by: Stefan Agner <stefan@agner.ch>
 ---
- arch/arm/boot/dts/rk3288-tinker.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
+ arch/arm/boot/dts/rk3288-tinker.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
 
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index d4df13bed..b92e59c1e 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -73,3 +73,9 @@
- 	status = "okay";
- 	supports-sdio;
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
+index acfaa12ec239..284e7982925d 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
+@@ -492,6 +492,8 @@ &tsadc {
  };
-+
-+&uart0 {
+ 
+ &uart0 {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
-+};
-+
+ 	status = "okay";
+ };
+ 
 -- 
-2.16.4
+2.28.0
 

buildroot-external/board/asus/tinker/patches/linux/0002-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch

@@ -0,0 +1,55 @@
+From fc25c993bf2feb6e66d55bf03eb725ec688e47eb Mon Sep 17 00:00:00 2001
+Message-Id: <fc25c993bf2feb6e66d55bf03eb725ec688e47eb.1599250914.git.stefan@agner.ch>
+In-Reply-To: <2ae3821fd824560ef2db3c87cfbec985177911f6.1599250914.git.stefan@agner.ch>
+References: <2ae3821fd824560ef2db3c87cfbec985177911f6.1599250914.git.stefan@agner.ch>
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 5 Nov 2018 22:15:14 +0100
+Subject: [PATCH 2/3] ARM: DTS: rk3288-tinker: Defining the SPI interface
+
+Taken from, and tested by @TonyMac32 .
+
+Well, the original one was tested by him but I had to adapt the
+registers definitions to the new 64-bits LPAE-compliant syntax.
+
+Therefore that *might* break, along with a few other patches.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+[move change to rk3288-tinker.dtsi]
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/boot/dts/rk3288-tinker.dtsi | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
+index 284e7982925d..d6cc66ab5bb1 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
+@@ -485,6 +485,25 @@ &sdio0 {
+ 	status = "okay";
+ };
+ 
++&spi2 {
++	max-freq = <50000000>;
++	status = "okay";
++
++	spidev@0 {
++		compatible = "rockchip,spi_tinker";
++		reg = <0x0 0>;
++		spi-max-frequency = <50000000>;
++		spi-cpha = <1>;
++	};
++
++	spidev@1 {
++		compatible = "rockchip,spi_tinker";
++		reg = <0x1>;
++		spi-max-frequency = <50000000>;
++		spi-cpha = <1>;
++	};
++};
++
+ &tsadc {
+ 	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ 	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+-- 
+2.28.0
+

buildroot-external/board/asus/tinker/patches/linux/0003-ARM-dts-rockchip-enable-I2C1-4-on-rk3288-tinker.patch

@@ -0,0 +1,41 @@
+From 3a9d71847ae869ffdb2b0818aa86a36d57d96331 Mon Sep 17 00:00:00 2001
+Message-Id: <3a9d71847ae869ffdb2b0818aa86a36d57d96331.1599250914.git.stefan@agner.ch>
+In-Reply-To: <2ae3821fd824560ef2db3c87cfbec985177911f6.1599250914.git.stefan@agner.ch>
+References: <2ae3821fd824560ef2db3c87cfbec985177911f6.1599250914.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Fri, 4 Sep 2020 21:57:55 +0200
+Subject: [PATCH 3/3] ARM: dts: rockchip: enable I2C1/4 on rk3288-tinker
+
+Enable I2C devices which are accessible via 40-pin header.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/boot/dts/rk3288-tinker.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
+index d6cc66ab5bb1..7af5818ac77c 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
++++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
+@@ -344,10 +344,18 @@ regulator-state-mem {
+ 	};
+ };
+ 
++&i2c1 {
++	status = "okay";
++};
++
+ &i2c2 {
+ 	status = "okay";
+ };
+ 
++&i2c4 {
++	status = "okay";
++};
++
+ &i2c5 {
+ 	status = "okay";
+ };
+-- 
+2.28.0
+

buildroot-external/board/asus/tinker/patches/linux/1-2-regulator-act8865-add-restart-handler-for-act8846.patch

@@ -1,74 +0,0 @@
-Patches act8846 regulator providing the proper reset handle and exploit
-the SIPC bit in GLB_POWER_OFF register. Mainly used to reset some rockchip
-boards.
-
-Origin: <https://patchwork.kernel.org/patch/6409521/>
-
-diff --git a/drivers/regulator/act8865-regulator.c b/drivers/regulator/act8865-regulator.c
-index 2ff73d7..836d10b 100644
---- a/drivers/regulator/act8865-regulator.c
-+++ b/drivers/regulator/act8865-regulator.c
-@@ -27,6 +27,7 @@
- #include <linux/regulator/of_regulator.h>
- #include <linux/regmap.h>
- #include <dt-bindings/regulator/active-semi,8865-regulator.h>
-+#include <linux/reboot.h>
- 
- /*
-  * ACT8600 Global Register Map.
-@@ -133,6 +134,8 @@
- #define	ACT8865_VOLTAGE_NUM	64
- #define ACT8600_SUDCDC_VOLTAGE_NUM	255
- 
-+#define ACT8846_SIPC_MASK 0x01
-+
- struct act8865 {
- 	struct regmap *regmap;
- 	int off_reg;
-@@ -402,6 +405,22 @@ static void act8865_power_off(void)
- 	while (1);
- }
- 
-+static int act8846_power_cycle(struct notifier_block *this,
-+	unsigned long code, void *unused)
-+{
-+	struct act8865 *act8846;
-+
-+	act8846 = i2c_get_clientdata(act8865_i2c_client);
-+	regmap_write(act8846->regmap, ACT8846_GLB_OFF_CTRL, ACT8846_SIPC_MASK);
-+
-+	return NOTIFY_DONE;
-+}
-+
-+static struct notifier_block act8846_restart_handler = {
-+	.notifier_call = act8846_power_cycle,
-+	.priority = 129,
-+};
-+
- static int act8865_pmic_probe(struct i2c_client *client,
- 			      const struct i2c_device_id *i2c_id)
- {
-@@ -484,6 +503,8 @@ static int act8865_pmic_probe(struct i2c_client *client,
- 	}
- 
- 	if (of_device_is_system_power_controller(dev->of_node)) {
-+		int ret;
-+
- 		if (!pm_power_off && (off_reg > 0)) {
- 			act8865_i2c_client = client;
- 			act8865->off_reg = off_reg;
-@@ -492,6 +513,14 @@ static int act8865_pmic_probe(struct i2c_client *client,
- 		} else {
- 			dev_err(dev, "Failed to set poweroff capability, already defined\n");
- 		}
-+
-+		if (type == ACT8846) {
-+			act8865_i2c_client = client;
-+			ret = register_restart_handler(&act8846_restart_handler);
-+			if (ret)
-+				pr_err("%s: cannot register restart handler, %d\n",
-+					__func__, ret);
-+		}
- 	}
- 
- 	/* Finally register devices */

buildroot-external/board/asus/tinker/patches/linux/1001-dts-rk3288-miqi-Enabling-the-Mali-GPU-node.patch

@@ -1,35 +0,0 @@
-From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
-From: Myy Miouyouyou <myy@miouyouyou.fr>
-Date: Thu, 19 Oct 2017 21:09:50 +0200
-Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
-
-Why is the MiQi the only one left without a working mali GPU node ?
-
-Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
-they enable it once in the DTSI, instead of defining it as "disabled"
-and enabling it in every DTS file ?
-
-Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index 4d923aa6..3cd60674 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -149,6 +149,11 @@
- 	status = "ok";
- };
- 
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
- &hdmi {
- 	ddc-i2c-bus = <&i2c5>;
- 	status = "okay";
--- 
-2.11.0
-

buildroot-external/board/asus/tinker/patches/linux/1002-ARM-dts-rockchip-fix-the-regulator-s-voltage-range-o.patch

@@ -1,45 +0,0 @@
-From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
-From: Willy Tarreau <w@1wt.eu>
-Date: Tue, 2 Aug 2016 08:31:00 +0200
-Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
- on MiQi board
-
-The board declared too narrow a voltage range for the CPU and GPU
-regulators, preventing it from using the full CPU frequency range.
-The regulators support 712500 to 1500000 microvolts.
-
-Signed-off-by: Willy Tarreau <w@1wt.eu>
-(cherry picked from commit 95330e63a9295a2632cee8cce5db80677f01857a)
----
- arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index 3cd60674..a1c3cdaa 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -168,8 +168,8 @@
- 		fcs,suspend-voltage-selector = <1>;
- 		reg = <0x40>;
- 		regulator-name = "vdd_cpu";
--		regulator-min-microvolt = <850000>;
--		regulator-max-microvolt = <1350000>;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1500000>;
- 		regulator-always-on;
- 		regulator-boot-on;
- 		regulator-enable-ramp-delay = <300>;
-@@ -182,8 +182,8 @@
- 		fcs,suspend-voltage-selector = <1>;
- 		reg = <0x41>;
- 		regulator-name = "vdd_gpu";
--		regulator-min-microvolt = <850000>;
--		regulator-max-microvolt = <1350000>;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1500000>;
- 		regulator-always-on;
- 		vin-supply = <&vcc_sys>;
- 	};
--- 
-2.11.0
-

buildroot-external/board/asus/tinker/patches/linux/1003-ARM-dts-rockchip-add-the-MiQi-board-s-fan-definition.patch

@@ -1,46 +0,0 @@
-From c27e445527e949f3ef46d5326066196969c17d23 Mon Sep 17 00:00:00 2001
-From: Myy <myy@miouyouyou.fr>
-Date: Sun, 12 Mar 2017 19:43:15 +0000
-Subject: [PATCH 06/28] ARM: dts: rockchip: add the MiQi board's fan definition
-
-The MiQi board is sold with an enclosure in which a fan is connected
-to the second LED output, and configured by default in "heartbeat"
-mode so that it rotates slowly and increases when the CPU load
-increases, ensuring appropriate cooling by default. This LED output
-is called "Fan" in the original kernel and connected to GPIO18
-(gpiochip 0, pin 18). Here we called it "miqi:green:fan" to stay
-consistent with the kernel's naming conventions.
-
-It's worth noting that without this patch the fan doesn't work at
-all, risking to make the board overheat.
-
-Fixes: 162718c (v4.7)
-Cc: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Willy Tarreau <w@1wt.eu>
-
-Signed-off-by: Myy <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-miqi.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
-index a1c3cdaa..0e383595 100644
---- a/arch/arm/boot/dts/rk3288-miqi.dts
-+++ b/arch/arm/boot/dts/rk3288-miqi.dts
-@@ -67,6 +67,13 @@
- 	leds {
- 		compatible = "gpio-leds";
- 
-+		fan {
-+			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
-+			label = "miqi:green:fan";
-+			linux,default-trigger = "heartbeat";
-+		};
-+
-+
- 		work {
- 			gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
- 			label = "miqi:green:user";
--- 
-2.11.0
-

buildroot-external/board/asus/tinker/patches/linux/1013-ARM-DTS-rk3288-tinker-Enabling-SDIO-and-Wifi.patch

@@ -1,98 +0,0 @@
-From d5d5c53173c484a13cda62a537cbf75a5df4b0e4 Mon Sep 17 00:00:00 2001
-From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
-Date: Mon, 5 Nov 2018 21:58:56 +0100
-Subject: [PATCH] ARM: DTS: rk3288-tinker: Enabling SDIO and Wifi
-
-Adding the appropriate nodes in order to exploit the WiFi capabilities
-of the board.
-Since these capabilities are provided through SDIO, and the SDIO
-nodes were not defined, these were added too.
-
-These seems to depend on each other so they are added in one big
-patch.
-
-Split if necessary.
-
-Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-tinker.dts | 62 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 62 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index 1e43527aa..d4df13bed 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -6,8 +6,70 @@
- /dts-v1/;
- 
- #include "rk3288-tinker.dtsi"
-+#include <dt-bindings/clock/rockchip,rk808.h>
- 
- / {
- 	model = "Rockchip RK3288 Asus Tinker Board";
- 	compatible = "asus,rk3288-tinker", "rockchip,rk3288";
-+
-+	/* This is essential to get SDIO devices working.
-+	   The Wifi depends on SDIO ! */
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk808 RK808_CLKOUT1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
-+
-+		/*
-+		 * On the module itself this is one of these (depending
-+		 * on the actual card populated):
-+		 * - SDIO_RESET_L_WL_REG_ON
-+		 * - PDN (power down when low)
-+		 */
-+		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>;
-+	};
-+
-+	wireless-wlan {
-+		compatible = "wlan-platdata";
-+		rockchip,grf = <&grf>;
-+		sdio_vref = <1800>;
-+		status = "okay";
-+		wifi_chip_type = "8723bs";
-+		WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-+	};
-+};
-+
-+&io_domains {
-+	wifi-supply = <&vcc_18>;
-+};
-+
-+&pinctrl {
-+	sdio-pwrseq {
-+		wifi_enable_h: wifienable-h {
-+			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		chip_enable_h: chip-enable-h {
-+			rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&sdio0 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-sdio-irq;
-+	clock-frequency = <50000000>;
-+	clock-freq-min-max = <200000 50000000>;
-+	disable-wp;
-+	keep-power-in-suspend;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	num-slots = <1>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
-+	sd-uhs-sdr104;
-+	status = "okay";
-+	supports-sdio;
- };
--- 
-2.16.4
-

buildroot-external/board/asus/tinker/patches/linux/1017-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch

@@ -1,53 +0,0 @@
-From a72e0749acad92df7b854e38e97e1dc7b4799abe Mon Sep 17 00:00:00 2001
-From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
-Date: Mon, 5 Nov 2018 22:11:24 +0100
-Subject: [PATCH] ARM: DTS: rk3288-tinker: Defined the I2C interfaces
-
-And all the hardware behind.
-
-Taken from @TonyMac32, Butchered by @Miouyouyou .
-
-Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-tinker.dts | 25 +++++++++++++++++++++++++
- 1 file changed, 25 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index b92e59c1e..96d05fc6b 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -40,6 +40,31 @@
- 	};
- };
- 
-+&i2c1 {
-+	status = "okay";
-+};
-+
-+&i2c2 {
-+	afc0:af-controller@0 {
-+		status = "okay";
-+		compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
-+		reg = <0x0 0x0c>;
-+	};
-+
-+	eeprom:m24c08@50 {
-+		compatible = "at,24c08";
-+		reg = <0x50>;
-+	};
-+};
-+
-+&i2c3 {
-+	status = "okay";
-+};
-+
-+&i2c4 {
-+	status = "okay";
-+};
-+
- &io_domains {
- 	wifi-supply = <&vcc_18>;
- };
--- 
-2.16.4
-

buildroot-external/board/asus/tinker/patches/linux/1018-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch

@@ -1,50 +0,0 @@
-From b24b8f83e150811ad54ee2a4843e44cd1421fafa Mon Sep 17 00:00:00 2001
-From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
-Date: Mon, 5 Nov 2018 22:15:14 +0100
-Subject: [PATCH] ARM: DTS: rk3288-tinker: Defining the SPI interface
-
-Taken from, and tested by @TonyMac32 .
-
-Well, the original one was tested by him but I had to adapt the
-registers definitions to the new 64-bits LPAE-compliant syntax.
-
-Therefore that *might* break, along with a few other patches.
-
-Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-tinker.dts | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index 96d05fc6b..17bfea298 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -99,6 +99,25 @@
- 	supports-sdio;
- };
- 
-+&spi2 {
-+	max-freq = <50000000>;
-+	status = "okay";
-+
-+	spidev@0 {
-+		compatible = "rockchip,spi_tinker";
-+		reg = <0x0 0>;
-+		spi-max-frequency = <50000000>;
-+		spi-cpha = <1>;
-+	};
-+
-+	spidev@1 {
-+		compatible = "rockchip,spi_tinker";
-+		reg = <0x1>;
-+		spi-max-frequency = <50000000>;
-+		spi-cpha = <1>;
-+	};
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
--- 
-2.16.4
-

buildroot-external/board/asus/tinker/patches/linux/1024-arm-dts-veyron-Added-a-flag-to-disable-cache-flush-d.patch

@@ -1,32 +0,0 @@
-From 9177b30ab083dbda2bede3b3d61ef71ad4b1ffe0 Mon Sep 17 00:00:00 2001
-From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
-Date: Thu, 1 Nov 2018 21:31:26 +0100
-Subject: [PATCH 2/2] arm: dts: veyron: Added a flag to disable cache flush
- during reset
-
-Flushing the MMC cache of ASUS Chromebooks during initialization or
-"recovery" generates 10 minutes hangup, according to @SolidHal.
-
-This is an adaptation of @SolidHal, in order to pinpoint the fix to
-Veyron Chromebooks, and avoiding issues other RK3288 boards.
-
-Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-veyron.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
-index 2075120cf..fa4951fd7 100644
---- a/arch/arm/boot/dts/rk3288-veyron.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
-@@ -123,6 +123,7 @@
- 	mmc-hs200-1_8v;
- 	mmc-pwrseq = <&emmc_pwrseq>;
- 	non-removable;
-+	no-recovery-cache-flush;
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- };
--- 
-2.16.4
-

buildroot-external/board/asus/tinker/patches/linux/board-tinkerboard-enable-emmc-support.patch

@@ -1,25 +0,0 @@
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
-index f88c913ff..7f04ccbdf 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dtsi
-+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
-@@ -547,3 +547,20 @@
- &gpiomem {
-     status = "okay";
- };
-+
-+&emmc {
-+    bus-width = <8>;
-+    cap-mmc-highspeed;
-+    non-removable;
-+    pinctrl-names = "default";
-+    pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
-+    max-frequency = <150000000>;
-+    mmc-hs200-1_8v;
-+    mmc-ddr-1_8v;
-+    status = "okay";
-+};
-+
-+&hdmi {
-+    pinctrl-names = "default";
-+    pinctrl-0 = <&hdmi_cec_c0>;
-+};

buildroot-external/board/asus/tinker/patches/linux/xt-q8l-v10-add-dts-makefile.patch

@@ -1,13 +0,0 @@
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 37a3de760..6bcfceede 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -832,6 +832,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
- 	rk3188-radxarock.dtb \
- 	rk3228-evb.dtb \
- 	rk3229-evb.dtb \
-+	rk3288-xt-q8l-v10.dtb \
- 	rk3229-xms6.dtb \
- 	rk3288-evb-act8846.dtb \
- 	rk3288-evb-rk808.dtb \
-

buildroot-external/board/asus/tinker/patches/linux/xt-q8l-v10-remote-keymap.patch

@@ -1,103 +0,0 @@
-diff --git a/drivers/media/rc/keymaps/rc-xt-q8l-v10.c b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
-index e69de29..19c7d9e 100644
---- /dev/null
-+++ b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
-@@ -0,0 +1,76 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+// rc-xt-q8l-v10.c - Keytable for xt-q8l-v10 tv box remote controller
-+//
-+// keymap imported from ir-keymaps.c
-+//
-+// Copyright (c) 2018 Paolo Sabatino
-+
-+#include <media/rc-map.h>
-+#include <linux/module.h>
-+
-+/*
-+
-+*/
-+
-+static struct rc_map_table xt_q8l_v10[] = {
-+	
-+	{ 0xcc1d11, KEY_ENTER },
-+	{ 0xcc1d00, KEY_POWER },
-+	{ 0xcc1d15, KEY_PLAYPAUSE },
-+	{ 0xcc1d16, KEY_STOP },
-+	{ 0xcc1d06, KEY_PREVIOUSSONG },
-+	{ 0xcc1d0a, KEY_NEXTSONG },
-+	{ 0xcc1d41, KEY_1 },
-+	{ 0xcc1d45, KEY_2 },
-+	{ 0xcc1d4d, KEY_3 },
-+	{ 0xcc1d42, KEY_4 },
-+	{ 0xcc1d46, KEY_5 },
-+	{ 0xcc1d4e, KEY_6 },
-+	{ 0xcc1d43, KEY_7 },
-+	{ 0xcc1d47, KEY_8 },
-+	{ 0xcc1d4f, KEY_9 },
-+	{ 0xcc1d49, KEY_0 },
-+	{ 0xcc1d4a, KEY_BACKSPACE },
-+	{ 0xcc1d48, KEY_F6 },
-+	{ 0xcc1d03, KEY_HOME },
-+	{ 0xcc1d0f, KEY_BACK },
-+	{ 0xcc1d40, KEY_MENU },
-+	{ 0xcc1d4c, KEY_TEXT },
-+	{ 0xcc1d10, KEY_LEFT },
-+	{ 0xcc1d12, KEY_RIGHT },
-+	{ 0xcc1d44, KEY_DOWN },
-+	{ 0xcc1d07, KEY_UP },
-+	{ 0xcc1d02, KEY_VOLUMEDOWN },
-+	{ 0xcc1d0c, KEY_MUTE },
-+	{ 0xcc1d0e, KEY_VOLUMEUP },
-+	{ 0xcc1d01, KEY_F1 },
-+	{ 0xcc1d05, KEY_F2 },
-+	{ 0xcc1d09, KEY_F3 },
-+	{ 0xcc1d0d, KEY_F4 },
-+	
-+};
-+
-+static struct rc_map_list xt_q8l_v10_map = {
-+	.map = {
-+		.scan     = xt_q8l_v10,
-+		.size     = ARRAY_SIZE(xt_q8l_v10),
-+		.rc_proto = RC_PROTO_NEC,	/* Legacy IR type */
-+		.name     = RC_MAP_XT_Q8L_V10,
-+	}
-+};
-+
-+static int __init init_rc_map_xt_q8l_v10(void)
-+{
-+	return rc_map_register(&xt_q8l_v10_map);
-+}
-+
-+static void __exit exit_rc_map_xt_q8l_v10(void)
-+{
-+	rc_map_unregister(&xt_q8l_v10_map);
-+}
-+
-+module_init(init_rc_map_xt_q8l_v10)
-+module_exit(exit_rc_map_xt_q8l_v10)
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Paolo Sabatino");
-diff --git a/include/media/rc-map.h b/include/media/rc-map.h
-index d621acadf..ad7abdb97 100644
---- a/include/media/rc-map.h
-+++ b/include/media/rc-map.h
-@@ -278,6 +278,7 @@ struct rc_map *rc_map_get(const char *name);
- #define RC_MAP_WINFAST_USBII_DELUXE      "rc-winfast-usbii-deluxe"
- #define RC_MAP_SU3000                    "rc-su3000"
- #define RC_MAP_XBOX_DVD                  "rc-xbox-dvd"
-+#define RC_MAP_XT_Q8L_V10                "rc-xt-q8l-v10"
- #define RC_MAP_X96MAX                    "rc-x96max"
- 
- /*
-diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
-index 5b1399af6..ec9ce1206 100644
---- a/drivers/media/rc/keymaps/Makefile
-+++ b/drivers/media/rc/keymaps/Makefile
-@@ -117,4 +117,5 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
- 			rc-winfast-usbii-deluxe.o \
- 			rc-su3000.o \
- 			rc-xbox-dvd.o \
-+			rc-xt-q8l-v10.o \
- 			rc-x96max.o \

buildroot-external/board/asus/tinker/patches/uboot/0001-SPL-modify-load-address-of-U-Boot.patch

@@ -0,0 +1,37 @@
+From 74e929bc4713b76f58a8df82019d74078b4b8d0c Mon Sep 17 00:00:00 2001
+Message-Id: <74e929bc4713b76f58a8df82019d74078b4b8d0c.1599227174.git.stefan@agner.ch>
+From: Pascal Vizeli <pvizeli@syshack.ch>
+Date: Fri, 24 Apr 2020 12:41:50 +0000
+Subject: [PATCH 1/3] SPL: modify load address of U-Boot
+
+Default load address of U-Boot is at sector 16384, which is where HAOS
+has its first partition. Use 0x2000 (8192) instead.
+
+Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ configs/tinker-rk3288_defconfig   | 1 +
+ configs/tinker-s-rk3288_defconfig | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
+index 83c3450839..574a711a32 100644
+--- a/configs/tinker-rk3288_defconfig
++++ b/configs/tinker-rk3288_defconfig
+@@ -84,3 +84,4 @@ CONFIG_USB_ETHER_ASIX=y
+ CONFIG_USB_ETHER_SMSC95XX=y
+ CONFIG_CMD_DHRYSTONE=y
+ CONFIG_ERRNO_STR=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x2000
+diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
+index 4925b14821..df047785ea 100644
+--- a/configs/tinker-s-rk3288_defconfig
++++ b/configs/tinker-s-rk3288_defconfig
+@@ -90,3 +90,4 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+ CONFIG_CONSOLE_SCROLL_LINES=10
+ CONFIG_CMD_DHRYSTONE=y
+ CONFIG_ERRNO_STR=y
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x2000
+-- 
+2.28.0
+

buildroot-external/board/asus/tinker/patches/uboot/0001-TLP-Modify-entrypoint-for-u-boot.patch

@@ -1,23 +0,0 @@
-From 17735a28503d90db2a7173816861750f475580ea Mon Sep 17 00:00:00 2001
-From: Pascal Vizeli <pvizeli@syshack.ch>
-Date: Fri, 24 Apr 2020 12:41:50 +0000
-Subject: [PATCH 1/1] TLP: Modify entrypoint for u-boot
-
-Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
----
- configs/tinker-rk3288_defconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
-index 83c3450839..648a7904be 100644
---- a/configs/tinker-rk3288_defconfig
-+++ b/configs/tinker-rk3288_defconfig
-@@ -84,3 +84,5 @@ CONFIG_USB_ETHER_ASIX=y
- CONFIG_USB_ETHER_SMSC95XX=y
- CONFIG_CMD_DHRYSTONE=y
- CONFIG_ERRNO_STR=y
-+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x3000
-+
--- 
-2.17.1
-

buildroot-external/board/asus/tinker/patches/uboot/0002-rockchip-dts-tinker-move-i2c-node-to-shared-device-t.patch

@@ -0,0 +1,55 @@
+From 683783c7253981c0d4c3b772aeb1f9bda833e2be Mon Sep 17 00:00:00 2001
+Message-Id: <683783c7253981c0d4c3b772aeb1f9bda833e2be.1599227174.git.stefan@agner.ch>
+In-Reply-To: <74e929bc4713b76f58a8df82019d74078b4b8d0c.1599227174.git.stefan@agner.ch>
+References: <74e929bc4713b76f58a8df82019d74078b4b8d0c.1599227174.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Fri, 4 Sep 2020 15:40:55 +0200
+Subject: [PATCH 2/3] rockchip: dts: tinker: move i2c node to shared device
+ tree
+
+The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
+to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.
+
+Cc: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/dts/rk3288-tinker-u-boot.dtsi | 7 +++++++
+ arch/arm/dts/rk3288-tinker.dts         | 7 -------
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi
+index 732aa4f91f..3d169906fd 100644
+--- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi
++++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi
+@@ -17,6 +17,13 @@
+ 	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
+ };
+ 
++&i2c2 {
++    m24c08@50 {
++        compatible = "at,24c08", "i2c-eeprom";
++        reg = <0x50>;
++    };
++};
++
+ &pinctrl {
+ 	u-boot,dm-pre-reloc;
+ };
+diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts
+index 4b8405fd82..338670123b 100644
+--- a/arch/arm/dts/rk3288-tinker.dts
++++ b/arch/arm/dts/rk3288-tinker.dts
+@@ -35,10 +35,3 @@
+ 	vbus-supply = <&vcc5v0_host>;
+ 	status = "okay";
+ };
+-
+-&i2c2 {
+-    m24c08@50 {
+-        compatible = "at,24c08", "i2c-eeprom";
+-        reg = <0x50>;
+-    };
+-};
+-- 
+2.28.0
+

buildroot-external/board/asus/tinker/patches/uboot/0003-rockchip-dts-tinker-remove-unnecessary-node.patch

@@ -0,0 +1,34 @@
+From 2af46619bb66af62bbfd2a880fe57d6dd0ec43fe Mon Sep 17 00:00:00 2001
+Message-Id: <2af46619bb66af62bbfd2a880fe57d6dd0ec43fe.1599227174.git.stefan@agner.ch>
+In-Reply-To: <74e929bc4713b76f58a8df82019d74078b4b8d0c.1599227174.git.stefan@agner.ch>
+References: <74e929bc4713b76f58a8df82019d74078b4b8d0c.1599227174.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Fri, 4 Sep 2020 15:44:38 +0200
+Subject: [PATCH 3/3] rockchip: dts: tinker: remove unnecessary node
+
+The property reg-shift with the same value is present in the base
+device tree already. Remove unnecessary node from rk3288-tinker.dts.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/dts/rk3288-tinker.dts | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts
+index 338670123b..8b1848c310 100644
+--- a/arch/arm/dts/rk3288-tinker.dts
++++ b/arch/arm/dts/rk3288-tinker.dts
+@@ -27,10 +27,6 @@
+ 	status = "okay";
+ };
+ 
+-&uart2 {
+-	reg-shift = <2>;
+-};
+-
+ &usb_host1 {
+ 	vbus-supply = <&vcc5v0_host>;
+ 	status = "okay";
+-- 
+2.28.0
+

buildroot-external/board/asus/tinker/uboot-boot.ush

@@ -27,7 +27,11 @@ setenv bootargs_b "root=PARTUUID=a3ec664e-32ce-4665-95ea-7ae90ce9aa20 rootfstype
 fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
 
 # Load device tree
-fatload mmc ${devnum}:1 ${fdt_addr_r} rk3288-tinker.dtb
+if test "$devnum" = "0"; then
+  fatload mmc ${devnum}:1 ${fdt_addr_r} rk3288-tinker-s.dtb
+else
+  fatload mmc ${devnum}:1 ${fdt_addr_r} rk3288-tinker.dtb
+fi
 
 setenv bootargs
 for BOOT_SLOT in "${BOOT_ORDER}"; do

buildroot-external/board/hardkernel/patches/linux/0001-Revert-cdc-acm-introduce-a-cool-down.patch

@@ -1,132 +0,0 @@
-From 5edf98e1fa176a480686ec77a5782b61eb009842 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Thu, 15 Oct 2020 13:58:14 +0200
-Subject: [PATCH] Revert "cdc-acm: introduce a cool down"
-
-This reverts commit a4e7279cd1d19f48f0af2a10ed020febaa9ac092.
----
- drivers/usb/class/cdc-acm.c | 30 ++----------------------------
- drivers/usb/class/cdc-acm.h |  5 +----
- 2 files changed, 3 insertions(+), 32 deletions(-)
-
-diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
-index f1a9043bdfe5..0f47d74c857d 100644
---- a/drivers/usb/class/cdc-acm.c
-+++ b/drivers/usb/class/cdc-acm.c
-@@ -410,12 +410,9 @@ static void acm_ctrl_irq(struct urb *urb)
- 
- exit:
- 	retval = usb_submit_urb(urb, GFP_ATOMIC);
--	if (retval && retval != -EPERM && retval != -ENODEV)
-+	if (retval && retval != -EPERM)
- 		dev_err(&acm->control->dev,
- 			"%s - usb_submit_urb failed: %d\n", __func__, retval);
--	else
--		dev_vdbg(&acm->control->dev,
--			"control resubmission terminated %d\n", retval);
- }
- 
- static int acm_submit_read_urb(struct acm *acm, int index, gfp_t mem_flags)
-@@ -431,8 +428,6 @@ static int acm_submit_read_urb(struct acm *acm, int index, gfp_t mem_flags)
- 			dev_err(&acm->data->dev,
- 				"urb %d failed submission with %d\n",
- 				index, res);
--		} else {
--			dev_vdbg(&acm->data->dev, "intended failure %d\n", res);
- 		}
- 		set_bit(index, &acm->read_urbs_free);
- 		return res;
-@@ -474,7 +469,6 @@ static void acm_read_bulk_callback(struct urb *urb)
- 	int status = urb->status;
- 	bool stopped = false;
- 	bool stalled = false;
--	bool cooldown = false;
- 
- 	dev_vdbg(&acm->data->dev, "got urb %d, len %d, status %d\n",
- 		rb->index, urb->actual_length, status);
-@@ -501,14 +495,6 @@ static void acm_read_bulk_callback(struct urb *urb)
- 			__func__, status);
- 		stopped = true;
- 		break;
--	case -EOVERFLOW:
--	case -EPROTO:
--		dev_dbg(&acm->data->dev,
--			"%s - cooling babbling device\n", __func__);
--		usb_mark_last_busy(acm->dev);
--		set_bit(rb->index, &acm->urbs_in_error_delay);
--		cooldown = true;
--		break;
- 	default:
- 		dev_dbg(&acm->data->dev,
- 			"%s - nonzero urb status received: %d\n",
-@@ -530,11 +516,9 @@ static void acm_read_bulk_callback(struct urb *urb)
- 	 */
- 	smp_mb__after_atomic();
- 
--	if (stopped || stalled || cooldown) {
-+	if (stopped || stalled) {
- 		if (stalled)
- 			schedule_work(&acm->work);
--		else if (cooldown)
--			schedule_delayed_work(&acm->dwork, HZ / 2);
- 		return;
- 	}
- 
-@@ -581,12 +565,6 @@ static void acm_softint(struct work_struct *work)
- 		}
- 	}
- 
--	if (test_and_clear_bit(ACM_ERROR_DELAY, &acm->flags)) {
--		for (i = 0; i < acm->rx_buflimit; i++)
--			if (test_and_clear_bit(i, &acm->urbs_in_error_delay))
--					acm_submit_read_urb(acm, i, GFP_NOIO);
--	}
--
- 	if (test_and_clear_bit(EVENT_TTY_WAKEUP, &acm->flags))
- 		tty_port_tty_wakeup(&acm->port);
- }
-@@ -1353,7 +1331,6 @@ static int acm_probe(struct usb_interface *intf,
- 	acm->readsize = readsize;
- 	acm->rx_buflimit = num_rx_buf;
- 	INIT_WORK(&acm->work, acm_softint);
--	INIT_DELAYED_WORK(&acm->dwork, acm_softint);
- 	init_waitqueue_head(&acm->wioctl);
- 	spin_lock_init(&acm->write_lock);
- 	spin_lock_init(&acm->read_lock);
-@@ -1563,7 +1540,6 @@ static void acm_disconnect(struct usb_interface *intf)
- 
- 	acm_kill_urbs(acm);
- 	cancel_work_sync(&acm->work);
--	cancel_delayed_work_sync(&acm->dwork);
- 
- 	tty_unregister_device(acm_tty_driver, acm->minor);
- 
-@@ -1606,8 +1582,6 @@ static int acm_suspend(struct usb_interface *intf, pm_message_t message)
- 
- 	acm_kill_urbs(acm);
- 	cancel_work_sync(&acm->work);
--	cancel_delayed_work_sync(&acm->dwork);
--	acm->urbs_in_error_delay = 0;
- 
- 	return 0;
- }
-diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h
-index cd5e9d8ab237..ca1c026382c2 100644
---- a/drivers/usb/class/cdc-acm.h
-+++ b/drivers/usb/class/cdc-acm.h
-@@ -109,11 +109,8 @@ struct acm {
- #		define EVENT_TTY_WAKEUP	0
- #		define EVENT_RX_STALL	1
- #		define ACM_THROTTLED	2
--#		define ACM_ERROR_DELAY	3
--	unsigned long urbs_in_error_delay;		/* these need to be restarted after a delay */
- 	struct usb_cdc_line_coding line;		/* bits, stop, parity */
--	struct work_struct work;			/* work queue entry for various purposes*/
--	struct delayed_work dwork;			/* for cool downs needed in error recovery */
-+	struct work_struct work;			/* work queue entry for line discipline waking up */
- 	unsigned int ctrlin;				/* input control lines (DCD, DSR, RI, break, overruns) */
- 	unsigned int ctrlout;				/* output control lines (DTR, RTS) */
- 	struct async_icount iocount;			/* counters for control line changes */
--- 
-2.25.4
-

buildroot-external/board/intel/nuc/kernel.config

@@ -15,13 +15,3 @@ CONFIG_DRM_I915=m
 CONFIG_DRM_I915_CAPTURE_ERROR=y
 CONFIG_DRM_I915_COMPRESS_ERROR=y
 CONFIG_DRM_I915_USERPTR=y
-
-CONFIG_SND_HDA=y
-CONFIG_SND_HDA_CORE=y
-CONFIG_SND_HDA_GENERIC=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_I915=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m

buildroot-external/board/raspberrypi/kernel.config

@@ -0,0 +1,2 @@
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_AUTOFS_FS is not set

buildroot-external/board/raspberrypi/patches/linux/0001-dt-bindings-reset-Add-a-binding-for-the-RPi-Firmware.patch

@@ -0,0 +1,41 @@
+From a9f92163e6c07e5c6f57f00f4931098e0e1ee826 Mon Sep 17 00:00:00 2001
+Message-Id: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:18:37 +0200
+Subject: [PATCH 1/4] dt-bindings: reset: Add a binding for the RPi Firmware
+ reset controller
+
+The firmware running on the RPi VideoCore can be used to reset and
+initialize HW controlled by the firmware.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+[backport for RPi 4.19 kernel]
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ .../dt-bindings/reset/raspberrypi,firmware-reset.h  | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+ create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
+
+diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
+new file mode 100644
+index 000000000000..1a4f4c792723
+--- /dev/null
++++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2020 Nicolas Saenz Julienne
++ * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
++ */
++
++#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
++#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
++
++#define RASPBERRYPI_FIRMWARE_RESET_ID_USB	0
++#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS	1
++
++#endif
+-- 
+2.27.0
+

buildroot-external/board/raspberrypi/patches/linux/0002-ARM-dts-bcm2711-Add-firmware-usb-reset-node.patch

@@ -0,0 +1,38 @@
+From b15414057bc9a023fc865242f499807d82933e58 Mon Sep 17 00:00:00 2001
+Message-Id: <b15414057bc9a023fc865242f499807d82933e58.1595152741.git.stefan@agner.ch>
+In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:18:39 +0200
+Subject: [PATCH 2/4] ARM: dts: bcm2711: Add firmware usb reset node
+
+Now that the reset driver exposing Raspberry Pi 4's firmware based USB
+reset routine is available, let's add the device tree node exposing it.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+[backport for RPi 4.19 kernel]
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+index 42259dbf3919..ec0b3bb64de8 100644
+--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
++++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+@@ -80,6 +80,11 @@
+ 				  "";
+ 		status = "okay";
+ 	};
++
++	reset: reset {
++		compatible = "raspberrypi,firmware-reset";
++		#reset-cells = <1>;
++	};
+ };
+ 
+ &uart0 {
+-- 
+2.27.0
+

buildroot-external/board/raspberrypi/patches/linux/0003-ARM-dts-bcm2711-Add-reset-controller-to-xHCI-node.patch

@@ -0,0 +1,58 @@
+From 08558575c0f3d1437994590ad418d6c2cf18d96b Mon Sep 17 00:00:00 2001
+Message-Id: <08558575c0f3d1437994590ad418d6c2cf18d96b.1595152741.git.stefan@agner.ch>
+In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:18:40 +0200
+Subject: [PATCH 3/4] ARM: dts: bcm2711: Add reset controller to xHCI node
+
+The chip is hardwired to the board's PCIe bus and needs to be properly
+setup trough a firmware routine after a PCI fundamental reset. Pass the
+reset controller phandle that takes care of triggering the
+initialization to the relevant PCI device.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+[backport for RPi 4.19 kernel]
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+index ec0b3bb64de8..2c6aa1933600 100644
+--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
++++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+@@ -4,6 +4,8 @@
+ #include "bcm2711-rpi.dtsi"
+ #include "bcm283x-rpi-csi1-2lane.dtsi"
+ 
++#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
++
+ / {
+ 	compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
+ 	model = "Raspberry Pi 4 Model B";
+@@ -87,6 +89,21 @@
+ 	};
+ };
+ 
++&pcie_0 {
++	pci@1,0 {
++		#address-cells = <3>;
++		#size-cells = <2>;
++		ranges;
++
++		reg = <0 0 0 0 0>;
++
++		usb@1,0 {
++			reg = <0x10000 0 0 0 0>;
++			resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
++		};
++	};
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pins &bt_pins>;
+-- 
+2.27.0
+

buildroot-external/board/raspberrypi/patches/linux/0004-ARM-dts-bcm2838-add-upstream-property-to-enable-PCIe.patch

@@ -0,0 +1,44 @@
+From dcfb930f9c271ad303a888ce94227d2d78974e39 Mon Sep 17 00:00:00 2001
+Message-Id: <dcfb930f9c271ad303a888ce94227d2d78974e39.1595152741.git.stefan@agner.ch>
+In-Reply-To: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+References: <a9f92163e6c07e5c6f57f00f4931098e0e1ee826.1595152741.git.stefan@agner.ch>
+From: Stefan Agner <stefan@agner.ch>
+Date: Sun, 19 Jul 2020 11:49:45 +0200
+Subject: [PATCH 4/4] ARM: dts: bcm2838: add upstream property to enable PCIe
+ spread-spectrum
+
+Add the upstream device tree property brcm,enable-ssc to enable
+spread-spectrum for PCIe. This is used by the upstream U-Boot.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+---
+ arch/arm/boot/dts/bcm2838.dtsi | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi
+index 36d250d7053b..d6cc876bc720 100644
+--- a/arch/arm/boot/dts/bcm2838.dtsi
++++ b/arch/arm/boot/dts/bcm2838.dtsi
+@@ -353,11 +353,14 @@
+ 			 */
+ 			ranges = <0x02000000 0x0 0xf8000000  0x6 0x00000000
+ 				  0x0 0x04000000>;
+-			/* Map inbound accesses from pci:0x0_00000000..ffffffff
+-			 * to scb:0x0_00000000-ffffffff
+-			 */
+-			dma-ranges = <0x02000000 0x0 0x00000000  0x0 0x00000000
+-				      0x1 0x00000000>;
++                        /*
++                         * The wrapper around the PCIe block has a bug
++                         * preventing it from accessing beyond the first 3GB of
++                         * memory.
++                         */
++                        dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
++                                      0x0 0xc0000000>;
++			brcm,enable-ssc;
+ 			status = "okay";
+ 		};
+ 
+-- 
+2.27.0
+

buildroot-external/board/raspberrypi/patches/uboot/0002-avoid-block-uart-write.patch

@@ -0,0 +1,49 @@
+From 5e960cc9b208c53d5385d5a2f6c7f380e9499d4c Mon Sep 17 00:00:00 2001
+From: Alexandru Costache <alexandru@balena.io>
+Date: Wed, 18 Mar 2020 16:54:28 +0100
+Subject: [PATCH] Add a retry limit when writing to uart console
+
+Seems that if the serial console is incorrectly
+configured in the dtb, writing to it may block indefinitely,
+thus preventing the board from booting.
+
+Let's add a retry count to unblock in such cases.
+
+Upstream-status: Inappropriate [configuration]
+Signed-off-by: Alexandru Costache <alexandru@balena.io>
+---
+ drivers/serial/serial_bcm283x_mu.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
+index bd1d89ec83..bd033d14c4 100644
+--- a/drivers/serial/serial_bcm283x_mu.c
++++ b/drivers/serial/serial_bcm283x_mu.c
+@@ -49,7 +49,7 @@ struct bcm283x_mu_regs {
+ struct bcm283x_mu_priv {
+ 	struct bcm283x_mu_regs *regs;
+ };
+-
++static uint16_t putc_retry = 0;
+ static int bcm283x_mu_serial_getc(struct udevice *dev);
+ 
+ static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
+@@ -105,8 +105,14 @@ static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
+ 	struct bcm283x_mu_regs *regs = priv->regs;
+ 
+ 	/* Wait until there is space in the FIFO */
+-	if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY))
+-		return -EAGAIN;
++	if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY)) {
++		if (++putc_retry) {
++			return -EAGAIN;
++		} else {
++			/* Couldn't write for too long, drop char */
++			return 0;
++		}
++	}
+ 
+ 	/* Send the character */
+ 	writel(data, &regs->io);
+-- 
+2.17.1

buildroot-external/board/raspberrypi/rootfs-overlay/usr/lib/udev/rules.d/99-rpi.rules

@@ -1,5 +1,4 @@
-
-KERNEL=="ttyAMA0", PROGRAM="/bin/sh -c '\
+KERNEL=="ttyAMA[01]", PROGRAM="/bin/sh -c '\
 	ALIASES=/proc/device-tree/aliases; \
 	if cmp -s $ALIASES/uart0 $ALIASES/serial0; then \
 		echo 0;\
@@ -10,19 +9,6 @@ KERNEL=="ttyAMA0", PROGRAM="/bin/sh -c '\
 	fi\
 '", SYMLINK+="serial%c"
 
-KERNEL=="ttyAMA1", PROGRAM="/bin/sh -c '\
-	ALIASES=/proc/device-tree/aliases; \
-	if [ -e /dev/ttyAMA0 ]; then \
-		exit 1; \
-	elif cmp -s $ALIASES/uart0 $ALIASES/serial0; then \
-		echo 0;\
-	elif cmp -s $ALIASES/uart0 $ALIASES/serial1; then \
-		echo 1; \
-	else \
-		exit 1; \
-	fi\
-'", SYMLINK+="serial%c"
-
 KERNEL=="ttyS0", PROGRAM="/bin/sh -c '\
 	ALIASES=/proc/device-tree/aliases; \
 	if cmp -s $ALIASES/uart1 $ALIASES/serial0; then \

buildroot-external/configs/intel_nuc_defconfig

@@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.72"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.63"
 BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -80,6 +80,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/odroid_c2_defconfig

@@ -71,6 +71,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/odroid_n2_defconfig

@@ -71,6 +71,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/odroid_xu4_defconfig

@@ -73,6 +73,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/ova_defconfig

@@ -23,7 +23,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.72"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.63"
 BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
@@ -71,6 +71,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/rpi0_w_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="bcm2708-rpi-zero-w"
@@ -74,6 +74,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/rpi2_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2709"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="bcm2709-rpi-2-b bcm2710-rpi-2-b"
@@ -73,6 +73,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/rpi3_64_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi3"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="broadcom/bcm2710-rpi-3-b broadcom/bcm2837-rpi-3-b broadcom/bcm2710-rpi-3-b-plus"
@@ -74,6 +74,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/rpi3_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2709"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="bcm2710-rpi-3-b bcm2710-rpi-3-b-plus bcm2710-rpi-cm3"
@@ -74,6 +74,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/rpi4_64_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2711"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="broadcom/bcm2711-rpi-4-b"
@@ -75,6 +75,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y
@@ -87,7 +88,7 @@ BR2_TARGET_ROOTFS_SQUASHFS4_LZ4=y
 BR2_TARGET_UBOOT=y
 BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
 BR2_TARGET_UBOOT_CUSTOM_VERSION=y
-BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.01"
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.07"
 BR2_TARGET_UBOOT_BOARD_DEFCONFIG="rpi_4"
 BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/bootloader/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/uboot.config"
 BR2_TARGET_UBOOT_BOOT_SCRIPT=y

buildroot-external/configs/rpi4_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcm2711"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="bcm2711-rpi-4-b"
@@ -75,6 +75,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/rpi_defconfig

@@ -26,7 +26,7 @@ BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
 BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/cc39f1c9f82f6fe5a437836811d906c709e0661c.tar.gz"
 BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi"
-BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
 BR2_LINUX_KERNEL_INTREE_DTS_NAME="bcm2708-rpi-b bcm2708-rpi-b-plus bcm2708-rpi-cm"
@@ -73,6 +73,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y

buildroot-external/configs/tinker_defconfig

@@ -24,13 +24,13 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
 BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker $(BR2_EXTERNAL_HASSOS_PATH)/board/asus/hassos-hook.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.72"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.63"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/kernel.config"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
 BR2_LINUX_KERNEL_LZ4=y
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
-BR2_LINUX_KERNEL_INTREE_DTS_NAME="rk3288-tinker"
+BR2_LINUX_KERNEL_INTREE_DTS_NAME="rk3288-tinker rk3288-tinker-s"
 BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
 BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y
 BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_HASSOS_PATH)/busybox.config"
@@ -75,6 +75,7 @@ BR2_PACKAGE_RNG_TOOLS=y
 BR2_PACKAGE_SYSTEMD_RANDOMSEED=y
 # BR2_PACKAGE_SYSTEMD_RESOLVED is not set
 BR2_PACKAGE_SYSTEMD_COREDUMP=y
+BR2_PACKAGE_SYSTEMD_LOGIND=y
 BR2_PACKAGE_UTIL_LINUX_PARTX=y
 BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y
 BR2_PACKAGE_UTIL_LINUX_LOGIN=y
@@ -88,7 +89,7 @@ BR2_TARGET_UBOOT=y
 BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
 BR2_TARGET_UBOOT_CUSTOM_VERSION=y
 BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2020.01"
-BR2_TARGET_UBOOT_BOARD_DEFCONFIG="tinker-rk3288"
+BR2_TARGET_UBOOT_BOARD_DEFCONFIG="tinker-s-rk3288"
 BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/bootloader/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/uboot.config"
 BR2_TARGET_UBOOT_FORMAT_DTB_BIN=y
 BR2_TARGET_UBOOT_FORMAT_DTB_IMG=y

buildroot-external/kernel/device-support.config

@@ -13,7 +13,6 @@ CONFIG_USB_ACM=m
 CONFIG_USB_USBNET=m
 
 CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_SND_USB_AUDIO=m
 
 CONFIG_BT=y
 CONFIG_BT_BREDR=y
@@ -144,3 +143,15 @@ CONFIG_VIDEO_EM28XX_V4L2=m
 CONFIG_VIDEO_EM28XX_ALSA=m
 CONFIG_VIDEO_EM28XX_DVB=m
 CONFIG_VIDEO_EM28XX_RC=m
+
+# Audio devices (USB/PCI)
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_HDA=y
+CONFIG_SND_HDA_CORE=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_I915=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_CODEC_HDMI=m

buildroot-external/kernel/docker.config

@@ -71,6 +71,8 @@ CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
 CONFIG_OVERLAY_FS=y
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+CONFIG_OVERLAY_FS_METACOPY=y
 
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m

buildroot-external/meta

@@ -1,7 +1,7 @@
-VERSION_MAJOR=4
-VERSION_BUILD=15
+VERSION_MAJOR=5
+VERSION_BUILD=2
 
 HASSOS_NAME="HassOS"
 HASSOS_ID="hassos"
 
-DEPLOYMENT="production"
+DEPLOYMENT="development"

buildroot-external/package/bluetooth-bcm43xx/bluetooth-bcm43xx.mk

@@ -11,8 +11,8 @@ BLUETOOTH_BCM43XX_SITE = $(BR2_EXTERNAL_HASSOS_PATH)/package/bluetooth-bcm43xx
 BLUETOOTH_BCM43XX_SITE_METHOD = local
 
 define BLUETOOTH_BCM43XX_BUILD_CMDS
-	curl -L -o $(@D)/BCM43430A1.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/a4e08822e3f24a6211f6ac94bc98b7ef87700c70/broadcom/BCM43430A1.hcd
-	curl -L -o $(@D)/BCM4345C0.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/a4e08822e3f24a6211f6ac94bc98b7ef87700c70/broadcom/BCM4345C0.hcd
+	curl -L -o $(@D)/BCM43430A1.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/fff76cb15527c435ce99a9787848eacd6288282c/broadcom/BCM43430A1.hcd
+	curl -L -o $(@D)/BCM4345C0.hcd https://raw.githubusercontent.com/RPi-Distro/bluez-firmware/fff76cb15527c435ce99a9787848eacd6288282c/broadcom/BCM4345C0.hcd
 	curl -L -o $(@D)/btuart https://raw.githubusercontent.com/RPi-Distro/pi-bluetooth/cbdbcb66bcc5b9af05f1a9fffe2254c872bb0ace/usr/bin/btuart
 	curl -L -o $(@D)/bthelper https://raw.githubusercontent.com/RPi-Distro/pi-bluetooth/cbdbcb66bcc5b9af05f1a9fffe2254c872bb0ace/usr/bin/bthelper
 	curl -L -o $(@D)/90-pi-bluetooth.rules https://raw.githubusercontent.com/RPi-Distro/pi-bluetooth/cbdbcb66bcc5b9af05f1a9fffe2254c872bb0ace/lib/udev/rules.d/90-pi-bluetooth.rules

buildroot-external/package/hassio/builder/hostapp.sh

@@ -26,14 +26,12 @@ DNS="homeassistant/${ARCH}-hassio-dns"
 AUDIO="homeassistant/${ARCH}-hassio-audio"
 CLI="homeassistant/${ARCH}-hassio-cli"
 MULTICAST="homeassistant/${ARCH}-hassio-multicast"
-OBSERVER="homeassistant/${ARCH}-hassio-observer"
 
 SUPERVISOR_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.supervisor')
 DNS_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.dns')
 CLI_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.cli')
 AUDIO_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.audio')
 MULTICAST_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.multicast')
-OBSERVER_VERSION=$(curl -s ${VERSION_URL} | jq -e -r '.observer')
 
 # Make image
 dd if=/dev/zero of=${DATA_IMG} bs=1G count=1
@@ -74,7 +72,6 @@ docker pull "${CLI}:${CLI_VERSION}"
 docker pull "${DNS}:${DNS_VERSION}"
 docker pull "${AUDIO}:${AUDIO_VERSION}"
 docker pull "${MULTICAST}:${MULTICAST_VERSION}"
-docker pull "${OBSERVER}:${OBSERVER_VERSION}"
 
 # Setup AppArmor
 mkdir -p "/mnt/data/supervisor/apparmor"

buildroot-external/patches/systemd/0002-time-wait-sync-log-inotify-errors.patch

@@ -1,23 +0,0 @@
-From 4a4298ef78e943d36f3b8d8e78bfa21b1506961e Mon Sep 17 00:00:00 2001
-From: Aman Gupta Karmani <aman@tmm1.net>
-Date: Mon, 12 Oct 2020 13:39:26 -0700
-Subject: [PATCH] time-wait-sync: log errors trying to watch
- /run/systemd/timesync
-
----
- src/time-wait-sync/time-wait-sync.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/time-wait-sync/time-wait-sync.c b/src/time-wait-sync/time-wait-sync.c
-index 96072445f6e..c8ec4850426 100644
---- a/src/time-wait-sync/time-wait-sync.c
-+++ b/src/time-wait-sync/time-wait-sync.c
-@@ -50,7 +50,7 @@ static void clock_state_release(ClockState *sp) {
- static int clock_state_update(ClockState *sp, sd_event *event);
- 
- static int update_notify_run_systemd_timesync(ClockState *sp) {
--        sp->run_systemd_timesync_wd = inotify_add_watch(sp->inotify_fd, "/run/systemd/timesync", IN_CREATE|IN_DELETE_SELF);
-+        sp->run_systemd_timesync_wd = inotify_add_watch_and_warn(sp->inotify_fd, "/run/systemd/timesync", IN_CREATE|IN_DELETE_SELF);
-         return sp->run_systemd_timesync_wd;
- }
- 

buildroot-external/patches/systemd/0003-fix-inotify-watches.patch

@@ -1,54 +0,0 @@
-From f6f4f5fe5395a57f10dd446c7266c53f0673eaac Mon Sep 17 00:00:00 2001
-From: Balaji Punnuru <balaji_punnuru@cable.comcast.com>
-Date: Thu, 9 Apr 2020 12:21:49 -0400
-Subject: [PATCH] util: return the correct correct wd from inotify helpers
-
-We need to propagate the acquired watch descriptors because our callers
-are counting on them.
-
-[Lennart: this is split out of #15381 and simplified]
----
- src/basic/fs-util.c | 14 ++++++++------
- 1 file changed, 8 insertions(+), 6 deletions(-)
-
-diff --git a/src/basic/fs-util.c b/src/basic/fs-util.c
-index 558cafbcaf5..ef3b5a51842 100644
---- a/src/basic/fs-util.c
-+++ b/src/basic/fs-util.c
-@@ -692,28 +692,30 @@ int unlink_or_warn(const char *filename) {
- 
- int inotify_add_watch_fd(int fd, int what, uint32_t mask) {
-         char path[STRLEN("/proc/self/fd/") + DECIMAL_STR_MAX(int) + 1];
--        int r;
-+        int wd;
- 
-         /* This is like inotify_add_watch(), except that the file to watch is not referenced by a path, but by an fd */
-         xsprintf(path, "/proc/self/fd/%i", what);
- 
--        r = inotify_add_watch(fd, path, mask);
--        if (r < 0)
-+        wd = inotify_add_watch(fd, path, mask);
-+        if (wd < 0)
-                 return -errno;
- 
--        return r;
-+        return wd;
- }
- 
- int inotify_add_watch_and_warn(int fd, const char *pathname, uint32_t mask) {
-+        int wd;
- 
--        if (inotify_add_watch(fd, pathname, mask) < 0) {
-+        wd = inotify_add_watch(fd, pathname, mask);
-+        if (wd < 0) {
-                 if (errno == ENOSPC)
-                         return log_error_errno(errno, "Failed to add a watch for %s: inotify watch limit reached", pathname);
- 
-                 return log_error_errno(errno, "Failed to add a watch for %s: %m", pathname);
-         }
- 
--        return 0;
-+        return wd;
- }
- 
- static bool unsafe_transition(const struct stat *a, const struct stat *b) {

buildroot-external/patches/uboot/2020.07/0001-CMD-read-string-from-fileinto-env.patch

@@ -0,0 +1,96 @@
+From 040a141f84f2f84bf8be18f85b4cdb34bf066df0 Mon Sep 17 00:00:00 2001
+Message-Id: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595086593.git.stefan@agner.ch>
+From: Pascal Vizeli <pvizeli@syshack.ch>
+Date: Sun, 5 Aug 2018 20:43:03 +0000
+Subject: [PATCH 1/1] CMD: read string from fileinto env
+
+Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
+---
+ cmd/Kconfig   |  5 +++++
+ cmd/Makefile  |  1 +
+ cmd/fileenv.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 51 insertions(+)
+ create mode 100644 cmd/fileenv.c
+
+diff --git a/cmd/Kconfig b/cmd/Kconfig
+index 192b3b262f..b44cd64215 100644
+--- a/cmd/Kconfig
++++ b/cmd/Kconfig
+@@ -1388,6 +1388,11 @@ config CMD_SETEXPR
+ 	  Also supports loading the value at a memory location into a variable.
+ 	  If CONFIG_REGEX is enabled, setexpr also supports a gsub function.
+ 
++config CMD_FILEENV
++	bool "fileenv"
++	help
++	   Read a file into memory and store it to env.
++
+ endmenu
+ 
+ menu "Android support commands"
+diff --git a/cmd/Makefile b/cmd/Makefile
+index 974ad48b0a..287887e97f 100644
+--- a/cmd/Makefile
++++ b/cmd/Makefile
+@@ -128,6 +128,7 @@ obj-$(CONFIG_CMD_SF) += sf.o
+ obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o
+ obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
+ obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
++obj-$(CONFIG_CMD_FILEENV) += fileenv.o
+ obj-$(CONFIG_CMD_SPI) += spi.o
+ obj-$(CONFIG_CMD_STRINGS) += strings.o
+ obj-$(CONFIG_CMD_SMC) += smccc.o
+diff --git a/cmd/fileenv.c b/cmd/fileenv.c
+new file mode 100644
+index 0000000000..af24d22d0e
+--- /dev/null
++++ b/cmd/fileenv.c
+@@ -0,0 +1,45 @@
++#include <config.h>
++#include <common.h>
++#include <command.h>
++#include <linux/ctype.h>
++
++static char *fs_argv[5];
++
++int do_fileenv(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
++{
++	if (argc < 6)
++		return CMD_RET_USAGE;
++
++	fs_argv[0] = "fatload";
++	fs_argv[1] = argv[1];
++	fs_argv[2] = argv[2];
++	fs_argv[3] = argv[3];
++	fs_argv[4] = argv[4];
++
++	if (do_fat_fsload(cmdtp, 0, 5, fs_argv) != 0)
++		return 1;
++
++	char *addr = (char *)simple_strtoul(argv[3], NULL, 16);
++	size_t size = env_get_hex("filesize", 0);
++
++	// Prepare string
++	addr[size] = 0x00;
++	char *s = addr;
++	while(*s != 0x00) {
++		if (isprint(*s)) {
++			s++;
++		}
++		else {
++			*s = 0x00;
++		}
++	}
++
++	return env_set(argv[5], addr);
++}
++
++U_BOOT_CMD(
++	fileenv, 6, 0, do_fileenv,
++	"Read file and store it into env.",
++	"<interface> <dev:part> <addr> <filename> <envname>\n"
++	"    - Read file from fat32 and store it as env."
++);
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0002-usb-xhci-Add-missing-cache-flush-in-the-scratchpad-a.patch

@@ -0,0 +1,41 @@
+From b39cd5ba642ddba46268e8d873b952604844c047 Mon Sep 17 00:00:00 2001
+Message-Id: <b39cd5ba642ddba46268e8d873b952604844c047.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Date: Mon, 25 May 2020 13:39:51 +0200
+Subject: [PATCH 02/20] usb: xhci: Add missing cache flush in the scratchpad
+ array initialization
+
+In current code there is no cache flush after initializing the scratchpad
+buffer array with the scratchpad buffer pointers. This leads to a failure
+of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
+controller + VL805 USB hub) - the very first TRB transfer on the command
+ring fails and there is a timeout while waiting for the command completion
+event. After adding the missing cache flush everything seems to be working
+as expected.
+
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ drivers/usb/host/xhci-mem.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index 2d968aafb0..f446520528 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
+ 		scratchpad->sp_array[i] = cpu_to_le64(ptr);
+ 	}
+ 
++	xhci_flush_cache((uintptr_t)scratchpad->sp_array,
++			 sizeof(u64) * num_sp);
++
+ 	return 0;
+ 
+ fail_sp3:
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0003-usb-xhci-Use-only-32-bit-accesses-in-xhci_writeq-xhc.patch

@@ -0,0 +1,69 @@
+From 71343be3dd8d7f04cea781c8369aa77a36ae7123 Mon Sep 17 00:00:00 2001
+Message-Id: <71343be3dd8d7f04cea781c8369aa77a36ae7123.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Date: Mon, 25 May 2020 13:39:52 +0200
+Subject: [PATCH 03/20] usb: xhci: Use only 32-bit accesses in
+ xhci_writeq/xhci_readq
+
+There might be hardware configurations where 64-bit data accesses
+to XHCI registers are not supported properly.  This patch removes
+the readq/writeq so always two 32-bit accesses are used to read/write
+64-bit XHCI registers, similarly as it is done in Linux kernel.
+
+This patch fixes operation of the XHCI controller on RPI4 Broadcom
+BCM2711 SoC based board, where the VL805 USB XHCI controller is
+connected to the PCIe Root Complex, which is attached to the system
+through the SCB bridge.
+
+Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
+the 64-bit wide register accesses initiated by the CPU are not properly
+translated to a sequence of 32-bit PCIe accesses.
+xhci_readq(), for example, always returns same value in upper and lower
+32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
+
+Cc: Sergey Temerkhanov <s.temerkhanov@gmail.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ include/usb/xhci.h | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/include/usb/xhci.h b/include/usb/xhci.h
+index 20e4a21066..1170c0ac69 100644
+--- a/include/usb/xhci.h
++++ b/include/usb/xhci.h
+@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val)
+  */
+ static inline u64 xhci_readq(__le64 volatile *regs)
+ {
+-#if BITS_PER_LONG == 64
+-	return readq(regs);
+-#else
+ 	__u32 *ptr = (__u32 *)regs;
+ 	u64 val_lo = readl(ptr);
+ 	u64 val_hi = readl(ptr + 1);
+ 	return val_lo + (val_hi << 32);
+-#endif
+ }
+ 
+ static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
+ {
+-#if BITS_PER_LONG == 64
+-	writeq(val, regs);
+-#else
+ 	__u32 *ptr = (__u32 *)regs;
+ 	u32 val_lo = lower_32_bits(val);
+ 	/* FIXME */
+ 	u32 val_hi = upper_32_bits(val);
+ 	writel(val_lo, ptr);
+ 	writel(val_hi, ptr + 1);
+-#endif
+ }
+ 
+ int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0004-pci-Move-some-PCIe-register-offset-definitions-to-a-.patch

@@ -0,0 +1,85 @@
+From 82024c95e4d00b555f93d93b9f706c4d995ab302 Mon Sep 17 00:00:00 2001
+Message-Id: <82024c95e4d00b555f93d93b9f706c4d995ab302.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Date: Mon, 25 May 2020 13:39:53 +0200
+Subject: [PATCH 04/20] pci: Move some PCIe register offset definitions to a
+ common header
+
+Some PCI Express register offsets are currently defined in multiple
+drivers, move them to a common header to avoid re-definitions and
+as a pre-requisite for adding new PCIe driver.
+While at it replace some spaces with tabs.
+
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ drivers/pci/pci-rcar-gen3.c   |  8 --------
+ drivers/pci/pcie_intel_fpga.c |  3 ---
+ include/pci.h                 | 13 +++++++++++--
+ 3 files changed, 11 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c
+index df7b37a592..1f51854ccc 100644
+--- a/drivers/pci/pci-rcar-gen3.c
++++ b/drivers/pci/pci-rcar-gen3.c
+@@ -118,14 +118,6 @@
+ #define RCAR_PCI_MAX_RESOURCES	4
+ #define MAX_NR_INBOUND_MAPS	6
+ 
+-#define PCI_EXP_FLAGS		2		/* Capabilities register */
+-#define PCI_EXP_FLAGS_TYPE	0x00f0		/* Device/Port type */
+-#define PCI_EXP_TYPE_ROOT_PORT	0x4		/* Root Port */
+-#define PCI_EXP_LNKCAP		12		/* Link Capabilities */
+-#define PCI_EXP_LNKCAP_DLLLARC	0x00100000	/* Data Link Layer Link Active Reporting Capable */
+-#define PCI_EXP_SLTCAP		20		/* Slot Capabilities */
+-#define PCI_EXP_SLTCAP_PSN	0xfff80000	/* Physical Slot Number */
+-
+ enum {
+ 	RCAR_PCI_ACCESS_READ,
+ 	RCAR_PCI_ACCESS_WRITE,
+diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c
+index aa1903e547..9f102c64c6 100644
+--- a/drivers/pci/pcie_intel_fpga.c
++++ b/drivers/pci/pcie_intel_fpga.c
+@@ -67,9 +67,6 @@
+ #define IS_ROOT_PORT(pcie, bdf)				\
+ 		((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
+ 
+-#define PCI_EXP_LNKSTA		18	/* Link Status */
+-#define PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
+-
+ /**
+  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
+  * @bus: Pointer to the PCI bus
+diff --git a/include/pci.h b/include/pci.h
+index 19c9244b94..9cd8564436 100644
+--- a/include/pci.h
++++ b/include/pci.h
+@@ -471,10 +471,19 @@
+ #define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
+ 
+ /* PCI Express capabilities */
++#define PCI_EXP_FLAGS		2	/* Capabilities register */
++#define  PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
++#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
+ #define PCI_EXP_DEVCAP		4	/* Device capabilities */
+-#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
++#define  PCI_EXP_DEVCAP_FLR	0x10000000 /* Function Level Reset */
+ #define PCI_EXP_DEVCTL		8	/* Device Control */
+-#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
++#define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
++#define PCI_EXP_LNKCAP		12	/* Link Capabilities */
++#define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
++#define PCI_EXP_LNKSTA		18	/* Link Status */
++#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
++#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
++#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
+ 
+ /* Include the ID list */
+ 
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0005-rpi4-shorten-a-mapping-for-the-DRAM.patch

@@ -0,0 +1,33 @@
+From 5dddca0c2ca5de72b74a5fca0d3ea67251add760 Mon Sep 17 00:00:00 2001
+Message-Id: <5dddca0c2ca5de72b74a5fca0d3ea67251add760.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Mon, 25 May 2020 13:39:54 +0200
+Subject: [PATCH 05/20] rpi4: shorten a mapping for the DRAM
+
+Remove the overlap between DRAM and device's IO area.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ arch/arm/mach-bcm283x/init.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
+index f4d00d892d..f9a5209480 100644
+--- a/arch/arm/mach-bcm283x/init.c
++++ b/arch/arm/mach-bcm283x/init.c
+@@ -39,7 +39,7 @@ static struct mm_region bcm2711_mem_map[] = {
+ 	{
+ 		.virt = 0x00000000UL,
+ 		.phys = 0x00000000UL,
+-		.size = 0xfe000000UL,
++		.size = 0xfc000000UL,
+ 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ 			 PTE_BLOCK_INNER_SHARE
+ 	}, {
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0006-rpi4-add-a-mapping-for-the-PCIe-XHCI-controller-MMIO.patch

@@ -0,0 +1,76 @@
+From a326f58940f16b2dc3740fd9e87eb485da939ae5 Mon Sep 17 00:00:00 2001
+Message-Id: <a326f58940f16b2dc3740fd9e87eb485da939ae5.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Mon, 25 May 2020 13:39:55 +0200
+Subject: [PATCH 06/20] rpi4: add a mapping for the PCIe XHCI controller MMIO
+ registers (ARM 64bit)
+
+Create a non-cacheable mapping for the 0x600000000 physical memory region,
+where MMIO registers for the PCIe XHCI controller are instantiated by the
+PCIe bridge.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
+index f9a5209480..cf4c5b245d 100644
+--- a/arch/arm/mach-bcm283x/init.c
++++ b/arch/arm/mach-bcm283x/init.c
+@@ -12,10 +12,15 @@
+ #include <dm/device.h>
+ #include <fdt_support.h>
+ 
++#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS	0x600000000UL
++#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE	0x800000UL
++
+ #ifdef CONFIG_ARM64
+ #include <asm/armv8/mmu.h>
+ 
+-static struct mm_region bcm283x_mem_map[] = {
++#define MEM_MAP_MAX_ENTRIES (4)
++
++static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
+ 	{
+ 		.virt = 0x00000000UL,
+ 		.phys = 0x00000000UL,
+@@ -35,7 +40,7 @@ static struct mm_region bcm283x_mem_map[] = {
+ 	}
+ };
+ 
+-static struct mm_region bcm2711_mem_map[] = {
++static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
+ 	{
+ 		.virt = 0x00000000UL,
+ 		.phys = 0x00000000UL,
+@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
+ 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ 			 PTE_BLOCK_NON_SHARE |
+ 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
++	}, {
++		.virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
++		.phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
++		.size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
++		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
++			 PTE_BLOCK_NON_SHARE |
++			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ 	}, {
+ 		/* List terminator */
+ 		0,
+@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
+ {
+ 	int i;
+ 
+-	for (i = 0; i < 2; i++) {
++	for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
+ 		mem_map[i].virt = pd[i].virt;
+ 		mem_map[i].phys = pd[i].phys;
+ 		mem_map[i].size = pd[i].size;
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0007-linux-bitfield.h-Add-primitives-for-manipulating-bit.patch

@@ -0,0 +1,85 @@
+From 9c761488487ce27517e2a9e425f4ed0777708c53 Mon Sep 17 00:00:00 2001
+Message-Id: <9c761488487ce27517e2a9e425f4ed0777708c53.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 25 May 2020 13:39:56 +0200
+Subject: [PATCH 07/20] linux/bitfield.h: Add primitives for manipulating
+ bitfields both in host- and fixed-endian
+
+Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
+an in depth explanation and two fixes from Johannes Berg:
+ e7d4a95da86e0 "bitfield: fix *_encode_bits()",
+ 37a3862e12382 "bitfield: add u8 helpers".
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+[s.nawrocki: added empty lines between functions and macros]
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+---
+ include/linux/bitfield.h | 52 ++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
+index 8b9d6fff00..7ad8b088ed 100644
+--- a/include/linux/bitfield.h
++++ b/include/linux/bitfield.h
+@@ -103,4 +103,56 @@
+ 		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));	\
+ 	})
+ 
++extern void __compiletime_error("value doesn't fit into mask")
++__field_overflow(void);
++extern void __compiletime_error("bad bitfield mask")
++__bad_mask(void);
++
++static __always_inline u64 field_multiplier(u64 field)
++{
++	if ((field | (field - 1)) & ((field | (field - 1)) + 1))
++		__bad_mask();
++	return field & -field;
++}
++
++static __always_inline u64 field_mask(u64 field)
++{
++	return field / field_multiplier(field);
++}
++
++#define ____MAKE_OP(type, base, to, from)				\
++static __always_inline __##type type##_encode_bits(base v, base field)	\
++{									\
++	if (__builtin_constant_p(v) && (v & ~field_mask(field)))	\
++		__field_overflow();					\
++	return to((v & field_mask(field)) * field_multiplier(field));	\
++}									\
++static __always_inline __##type type##_replace_bits(__##type old,	\
++					base val, base field)		\
++{									\
++	return (old & ~to(field)) | type##_encode_bits(val, field);	\
++}									\
++static __always_inline void type##p_replace_bits(__##type * p,		\
++					base val, base field)		\
++{									\
++	*p = (*p & ~to(field)) | type##_encode_bits(val, field);	\
++}									\
++static __always_inline base type##_get_bits(__##type v, base field)	\
++{									\
++	return (from(v) & field) / field_multiplier(field);		\
++}
++
++#define __MAKE_OP(size)							\
++	____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \
++	____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \
++	____MAKE_OP(u##size, u##size, ,)
++
++____MAKE_OP(u8, u8, ,)
++__MAKE_OP(16)
++__MAKE_OP(32)
++__MAKE_OP(64)
++
++#undef __MAKE_OP
++#undef ____MAKE_OP
++
+ #endif
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0008-pci-Add-some-PCI-Express-capability-register-offset-.patch

@@ -0,0 +1,47 @@
+From 376bd33efa69abfc6102eb5a56b700c0f1981cf4 Mon Sep 17 00:00:00 2001
+Message-Id: <376bd33efa69abfc6102eb5a56b700c0f1981cf4.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Date: Mon, 25 May 2020 13:39:57 +0200
+Subject: [PATCH 08/20] pci: Add some PCI Express capability register offset
+ definitions
+
+Add PCI Express capability definitions required by the Broadcom
+STB PCIe controller driver.
+
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ include/pci.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/include/pci.h b/include/pci.h
+index 9cd8564436..281f353916 100644
+--- a/include/pci.h
++++ b/include/pci.h
+@@ -479,11 +479,20 @@
+ #define PCI_EXP_DEVCTL		8	/* Device Control */
+ #define  PCI_EXP_DEVCTL_BCR_FLR	0x8000  /* Bridge Configuration Retry / FLR */
+ #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
++#define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */
++#define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
+ #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
+ #define PCI_EXP_LNKSTA		18	/* Link Status */
++#define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */
++#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
++#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
++#define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
++#define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Negotiated Link Width */
++#define  PCI_EXP_LNKSTA_NLW_SHIFT 4	/* start of NLW mask in link status */
+ #define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
+ #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
+ #define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
++#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
+ 
+ /* Include the ID list */
+ 
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0009-pci-Add-driver-for-Broadcom-BCM2711-SoC-PCIe-control.patch

@@ -0,0 +1,686 @@
+From 21a9b72b4a28398c9511f3d9e3c1adc1439a8870 Mon Sep 17 00:00:00 2001
+Message-Id: <21a9b72b4a28398c9511f3d9e3c1adc1439a8870.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Sylwester Nawrocki <s.nawrocki@samsung.com>
+Date: Mon, 25 May 2020 13:39:58 +0200
+Subject: [PATCH 09/20] pci: Add driver for Broadcom BCM2711 SoC PCIe
+ controller
+
+This patch adds basic driver PCI Express controller found on Broadcom
+set-top-box SoCs, e.g. BCM2711.
+The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
+handling removed. The inbound access memory region is not currently
+parsed from dma-ranges DT property and a fixed 3GB region is used.
+
+The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
+USB Host Controller.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+---
+ drivers/pci/Kconfig        |   9 +
+ drivers/pci/Makefile       |   1 +
+ drivers/pci/pcie_brcmstb.c | 623 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 633 insertions(+)
+ create mode 100644 drivers/pci/pcie_brcmstb.c
+
+diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
+index 6d8c22aacf..7e1e51d9ea 100644
+--- a/drivers/pci/Kconfig
++++ b/drivers/pci/Kconfig
+@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP
+ 	  Say Y here if you want to enable PCIe controller support on
+ 	  Rockchip SoCs.
+ 
++config PCI_BRCMSTB
++	bool "Broadcom STB PCIe controller"
++	depends on DM_PCI
++	depends on ARCH_BCM283X
++	help
++	  Say Y here if you want to enable support for PCIe controller
++	  on Broadcom set-top-box (STB) SoCs.
++	  This driver currently supports only BCM2711 SoC and RC mode
++	  of the controller.
+ endif
+diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
+index 955351c5c2..29092916a6 100644
+--- a/drivers/pci/Makefile
++++ b/drivers/pci/Makefile
+@@ -44,3 +44,4 @@ obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
+ obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
+ obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
+ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
++obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
+diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
+new file mode 100644
+index 0000000000..dade79e9c8
+--- /dev/null
++++ b/drivers/pci/pcie_brcmstb.c
+@@ -0,0 +1,623 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Broadcom STB PCIe controller driver
++ *
++ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
++ *
++ * Based on upstream Linux kernel driver:
++ * drivers/pci/controller/pcie-brcmstb.c
++ * Copyright (C) 2009 - 2017 Broadcom
++ *
++ * Based driver by Nicolas Saenz Julienne
++ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
++ */
++
++#include <common.h>
++#include <errno.h>
++#include <dm.h>
++#include <dm/ofnode.h>
++#include <pci.h>
++#include <asm/io.h>
++#include <linux/bitfield.h>
++#include <linux/log2.h>
++#include <linux/iopoll.h>
++
++/* Offset of the mandatory PCIe capability config registers */
++#define BRCM_PCIE_CAP_REGS				0x00ac
++
++/* The PCIe controller register offsets */
++#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1		0x0188
++#define  VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK	0xc
++#define  VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN		0x0
++
++#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
++#define  CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK		0xffffff
++
++#define PCIE_RC_DL_MDIO_ADDR				0x1100
++#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
++#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
++
++#define PCIE_MISC_MISC_CTRL				0x4008
++#define  MISC_CTRL_SCB_ACCESS_EN_MASK			0x1000
++#define  MISC_CTRL_CFG_READ_UR_MODE_MASK		0x2000
++#define  MISC_CTRL_MAX_BURST_SIZE_MASK			0x300000
++#define  MISC_CTRL_MAX_BURST_SIZE_128			0x0
++#define  MISC_CTRL_SCB0_SIZE_MASK			0xf8000000
++
++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
++#define PCIE_MEM_WIN0_LO(win)	\
++		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
++
++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
++#define PCIE_MEM_WIN0_HI(win)	\
++		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
++
++#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
++#define  RC_BAR1_CONFIG_LO_SIZE_MASK			0x1f
++
++#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
++#define  RC_BAR2_CONFIG_LO_SIZE_MASK			0x1f
++#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
++
++#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
++#define  RC_BAR3_CONFIG_LO_SIZE_MASK			0x1f
++
++#define PCIE_MISC_PCIE_STATUS				0x4068
++#define  STATUS_PCIE_PORT_MASK				0x80
++#define  STATUS_PCIE_PORT_SHIFT				7
++#define  STATUS_PCIE_DL_ACTIVE_MASK			0x20
++#define  STATUS_PCIE_DL_ACTIVE_SHIFT			5
++#define  STATUS_PCIE_PHYLINKUP_MASK			0x10
++#define  STATUS_PCIE_PHYLINKUP_SHIFT			4
++
++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
++#define  MEM_WIN0_BASE_LIMIT_LIMIT_MASK			0xfff00000
++#define  MEM_WIN0_BASE_LIMIT_BASE_MASK			0xfff0
++#define  MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT		12
++#define PCIE_MEM_WIN0_BASE_LIMIT(win)	\
++	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
++
++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI		0x4080
++#define  MEM_WIN0_BASE_HI_BASE_MASK			0xff
++#define PCIE_MEM_WIN0_BASE_HI(win)	\
++	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
++
++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI		0x4084
++#define  PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK		0xff
++#define PCIE_MEM_WIN0_LIMIT_HI(win)	\
++	 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
++
++#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
++#define  PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
++#define  PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
++
++#define PCIE_MSI_INTR2_CLR				0x4508
++#define PCIE_MSI_INTR2_MASK_SET				0x4510
++
++#define PCIE_EXT_CFG_DATA				0x8000
++
++#define PCIE_EXT_CFG_INDEX				0x9000
++#define  PCIE_EXT_BUSNUM_SHIFT				20
++#define  PCIE_EXT_SLOT_SHIFT				15
++#define  PCIE_EXT_FUNC_SHIFT				12
++
++#define PCIE_RGR1_SW_INIT_1				0x9210
++#define  RGR1_SW_INIT_1_PERST_MASK			0x1
++#define  RGR1_SW_INIT_1_INIT_MASK			0x2
++
++/* PCIe parameters */
++#define BRCM_NUM_PCIE_OUT_WINS				4
++
++/* MDIO registers */
++#define MDIO_PORT0					0x0
++#define MDIO_DATA_MASK					0x7fffffff
++#define MDIO_DATA_SHIFT					0
++#define MDIO_PORT_MASK					0xf0000
++#define MDIO_PORT_SHIFT					16
++#define MDIO_REGAD_MASK					0xffff
++#define MDIO_REGAD_SHIFT				0
++#define MDIO_CMD_MASK					0xfff00000
++#define MDIO_CMD_SHIFT					20
++#define MDIO_CMD_READ					0x1
++#define MDIO_CMD_WRITE					0x0
++#define MDIO_DATA_DONE_MASK				0x80000000
++#define SSC_REGS_ADDR					0x1100
++#define SET_ADDR_OFFSET					0x1f
++#define SSC_CNTL_OFFSET					0x2
++#define SSC_CNTL_OVRD_EN_MASK				0x8000
++#define SSC_CNTL_OVRD_VAL_MASK				0x4000
++#define SSC_STATUS_OFFSET				0x1
++#define SSC_STATUS_SSC_MASK				0x400
++#define SSC_STATUS_SSC_SHIFT				10
++#define SSC_STATUS_PLL_LOCK_MASK			0x800
++#define SSC_STATUS_PLL_LOCK_SHIFT			11
++
++/**
++ * struct brcm_pcie - the PCIe controller state
++ * @base: Base address of memory mapped IO registers of the controller
++ * @gen: Non-zero value indicates limitation of the PCIe controller operation
++ *       to a specific generation (1, 2 or 3)
++ * @ssc: true indicates active Spread Spectrum Clocking operation
++ */
++struct brcm_pcie {
++	void __iomem		*base;
++
++	int			gen;
++	bool			ssc;
++};
++
++/**
++ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
++ * @size: The inbound region size
++ *
++ * This function converts size of the inbound "BAR" region to the non-linear
++ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
++ *
++ * Return: The encoded inbound region size
++ */
++static int brcm_pcie_encode_ibar_size(u64 size)
++{
++	int log2_in = ilog2(size);
++
++	if (log2_in >= 12 && log2_in <= 15)
++		/* Covers 4KB to 32KB (inclusive) */
++		return (log2_in - 12) + 0x1c;
++	else if (log2_in >= 16 && log2_in <= 37)
++		/* Covers 64KB to 32GB, (inclusive) */
++		return log2_in - 15;
++
++	/* Something is awry so disable */
++	return 0;
++}
++
++/**
++ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
++ * @pcie: Pointer to the PCIe controller state
++ *
++ * The controller is capable of serving in both RC and EP roles.
++ *
++ * Return: true for RC mode, false for EP mode.
++ */
++static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
++{
++	u32 val;
++
++	val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
++
++	return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
++}
++
++/**
++ * brcm_pcie_link_up() - Check whether the PCIe link is up
++ * @pcie: Pointer to the PCIe controller state
++ *
++ * Return: true if the link is up, false otherwise.
++ */
++static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
++{
++	u32 val, dla, plu;
++
++	val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
++	dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
++	plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
++
++	return dla && plu;
++}
++
++static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
++				    uint offset, void **paddress)
++{
++	struct brcm_pcie *pcie = dev_get_priv(dev);
++	unsigned int pci_bus = PCI_BUS(bdf);
++	unsigned int pci_dev = PCI_DEV(bdf);
++	unsigned int pci_func = PCI_FUNC(bdf);
++	int idx;
++
++	/*
++	 * Busses 0 (host PCIe bridge) and 1 (its immediate child)
++	 * are limited to a single device each
++	 */
++	if (pci_bus < 2 && pci_dev > 0)
++		return -EINVAL;
++
++	/* Accesses to the RC go right to the RC registers */
++	if (pci_bus == 0) {
++		*paddress = pcie->base + offset;
++		return 0;
++	}
++
++	/* For devices, write to the config space index register */
++	idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
++		| (pci_dev << PCIE_EXT_SLOT_SHIFT)
++		| (pci_func << PCIE_EXT_FUNC_SHIFT);
++
++	writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
++	*paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
++
++	return 0;
++}
++
++static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
++				 uint offset, ulong *valuep,
++				 enum pci_size_t size)
++{
++	return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
++					    bdf, offset, valuep, size);
++}
++
++static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
++				  uint offset, ulong value,
++				  enum pci_size_t size)
++{
++	return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
++					     bdf, offset, value, size);
++}
++
++static const char *link_speed_to_str(unsigned int cls)
++{
++	switch (cls) {
++	case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
++	case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
++	case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
++	default:
++		break;
++	}
++
++	return "??";
++}
++
++static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
++				   unsigned int cmd)
++{
++	u32 pkt;
++
++	pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
++	pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
++	pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
++
++	return pkt;
++}
++
++/**
++ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
++ * @base: Pointer to the PCIe controller IO registers
++ * @port: The MDIO port number
++ * @regad: The register address
++ * @val: A pointer at which to store the read value
++ *
++ * Return: 0 on success and register value in @val, negative error value
++ *         on failure.
++ */
++static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
++			       unsigned int regad, u32 *val)
++{
++	u32 data, addr;
++	int ret;
++
++	addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
++	writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
++	readl(base + PCIE_RC_DL_MDIO_ADDR);
++
++	ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
++				 (data & MDIO_DATA_DONE_MASK), 100);
++
++	*val = data & MDIO_DATA_MASK;
++
++	return ret;
++}
++
++/**
++ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
++ * @base: Pointer to the PCIe controller IO registers
++ * @port: The MDIO port number
++ * @regad: Address of the register
++ * @wrdata: The value to write
++ *
++ * Return: 0 on success, negative error value on failure.
++ */
++static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
++				unsigned int regad, u16 wrdata)
++{
++	u32 data, addr;
++
++	addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
++	writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
++	readl(base + PCIE_RC_DL_MDIO_ADDR);
++	writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
++
++	return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
++				  !(data & MDIO_DATA_DONE_MASK), 100);
++}
++
++/**
++ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
++ * @base: pointer to the PCIe controller IO registers
++ *
++ * Return: 0 on success, negative error value on failure.
++ */
++static int brcm_pcie_set_ssc(void __iomem *base)
++{
++	int pll, ssc;
++	int ret;
++	u32 tmp;
++
++	ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
++				   SSC_REGS_ADDR);
++	if (ret < 0)
++		return ret;
++
++	ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
++	if (ret < 0)
++		return ret;
++
++	tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
++
++	ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
++	if (ret < 0)
++		return ret;
++
++	udelay(1000);
++	ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
++	if (ret < 0)
++		return ret;
++
++	ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
++	pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
++
++	return ssc && pll ? 0 : -EIO;
++}
++
++/**
++ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
++ * @pcie: pointer to the PCIe controller state
++ * @gen: PCIe generation to limit the controller's operation to
++ */
++static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
++{
++	void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
++
++	u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
++	u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
++
++	lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
++	writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
++
++	lnkctl2 = (lnkctl2 & ~0xf) | gen;
++	writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
++}
++
++static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
++				       unsigned int win, u64 phys_addr,
++				       u64 pcie_addr, u64 size)
++{
++	void __iomem *base = pcie->base;
++	u32 phys_addr_mb_high, limit_addr_mb_high;
++	phys_addr_t phys_addr_mb, limit_addr_mb;
++	int high_addr_shift;
++	u32 tmp;
++
++	/* Set the base of the pcie_addr window */
++	writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
++	writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
++
++	/* Write the addr base & limit lower bits (in MBs) */
++	phys_addr_mb = phys_addr / SZ_1M;
++	limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
++
++	tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
++	u32p_replace_bits(&tmp, phys_addr_mb,
++			  MEM_WIN0_BASE_LIMIT_BASE_MASK);
++	u32p_replace_bits(&tmp, limit_addr_mb,
++			  MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
++	writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
++
++	/* Write the cpu & limit addr upper bits */
++	high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
++	phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
++	tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
++	u32p_replace_bits(&tmp, phys_addr_mb_high,
++			  MEM_WIN0_BASE_HI_BASE_MASK);
++	writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
++
++	limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
++	tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
++	u32p_replace_bits(&tmp, limit_addr_mb_high,
++			  PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
++	writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
++}
++
++static int brcm_pcie_probe(struct udevice *dev)
++{
++	struct udevice *ctlr = pci_get_controller(dev);
++	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
++	struct brcm_pcie *pcie = dev_get_priv(dev);
++	void __iomem *base = pcie->base;
++	bool ssc_good = false;
++	int num_out_wins = 0;
++	u64 rc_bar2_offset, rc_bar2_size;
++	unsigned int scb_size_val;
++	int i, ret;
++	u16 nlw, cls, lnksta;
++	u32 tmp;
++
++	/*
++	 * Reset the bridge, assert the fundamental reset. Note for some SoCs,
++	 * e.g. BCM7278, the fundamental reset should not be asserted here.
++	 * This will need to be changed when support for other SoCs is added.
++	 */
++	setbits_le32(base + PCIE_RGR1_SW_INIT_1,
++		     RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
++	/*
++	 * The delay is a safety precaution to preclude the reset signal
++	 * from looking like a glitch.
++	 */
++	udelay(100);
++
++	/* Take the bridge out of reset */
++	clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
++
++	clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
++		     PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
++
++	/* Wait for SerDes to be stable */
++	udelay(100);
++
++	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
++	clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
++			MISC_CTRL_MAX_BURST_SIZE_MASK,
++			MISC_CTRL_SCB_ACCESS_EN_MASK |
++			MISC_CTRL_CFG_READ_UR_MODE_MASK |
++			MISC_CTRL_MAX_BURST_SIZE_128);
++	/*
++	 * TODO: When support for other SoCs than BCM2711 is added we may
++	 * need to use the base address and size(s) provided in the dma-ranges
++	 * property.
++	 */
++	rc_bar2_offset = 0;
++	rc_bar2_size = 0xc0000000;
++
++	tmp = lower_32_bits(rc_bar2_offset);
++	u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
++			  RC_BAR2_CONFIG_LO_SIZE_MASK);
++	writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
++	writel(upper_32_bits(rc_bar2_offset),
++	       base + PCIE_MISC_RC_BAR2_CONFIG_HI);
++
++	scb_size_val = rc_bar2_size ?
++		       ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
++
++	tmp = readl(base + PCIE_MISC_MISC_CTRL);
++	u32p_replace_bits(&tmp, scb_size_val,
++			  MISC_CTRL_SCB0_SIZE_MASK);
++	writel(tmp, base + PCIE_MISC_MISC_CTRL);
++
++	/* Disable the PCIe->GISB memory window (RC_BAR1) */
++	clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
++		     RC_BAR1_CONFIG_LO_SIZE_MASK);
++
++	/* Disable the PCIe->SCB memory window (RC_BAR3) */
++	clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
++		     RC_BAR3_CONFIG_LO_SIZE_MASK);
++
++	/* Mask all interrupts since we are not handling any yet */
++	writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
++
++	/* Clear any interrupts we find on boot */
++	writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
++
++	if (pcie->gen)
++		brcm_pcie_set_gen(pcie, pcie->gen);
++
++	/* Unassert the fundamental reset */
++	clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
++		     RGR1_SW_INIT_1_PERST_MASK);
++
++	/* Give the RC/EP time to wake up, before trying to configure RC.
++	 * Intermittently check status for link-up, up to a total of 100ms.
++	 */
++	for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
++		mdelay(5);
++
++	if (!brcm_pcie_link_up(pcie)) {
++		printf("PCIe BRCM: link down\n");
++		return -EINVAL;
++	}
++
++	if (!brcm_pcie_rc_mode(pcie)) {
++		printf("PCIe misconfigured; is in EP mode\n");
++		return -EINVAL;
++	}
++
++	for (i = 0; i < hose->region_count; i++) {
++		struct pci_region *reg = &hose->regions[i];
++
++		if (reg->flags != PCI_REGION_MEM)
++			continue;
++
++		if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
++			return -EINVAL;
++
++		brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
++					   reg->bus_start, reg->size);
++
++		num_out_wins++;
++	}
++
++	/*
++	 * For config space accesses on the RC, show the right class for
++	 * a PCIe-PCIe bridge (the default setting is to be EP mode).
++	 */
++	clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
++			CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
++
++	if (pcie->ssc) {
++		ret = brcm_pcie_set_ssc(pcie->base);
++		if (!ret)
++			ssc_good = true;
++		else
++			printf("PCIe BRCM: failed attempt to enter SSC mode\n");
++	}
++
++	lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
++	cls = lnksta & PCI_EXP_LNKSTA_CLS;
++	nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
++
++	printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
++	       nlw, ssc_good ? "(SSC)" : "(!SSC)");
++
++	/* PCIe->SCB endian mode for BAR */
++	clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
++			VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
++			VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
++	/*
++	 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
++	 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
++	 */
++	setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
++		     PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
++
++	return 0;
++}
++
++static int brcm_pcie_ofdata_to_platdata(struct udevice *dev)
++{
++	struct brcm_pcie *pcie = dev_get_priv(dev);
++	ofnode dn = dev_ofnode(dev);
++	u32 max_link_speed;
++	int ret;
++
++	/* Get the controller base address */
++	pcie->base = dev_read_addr_ptr(dev);
++	if (!pcie->base)
++		return -EINVAL;
++
++	pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
++
++	ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
++	if (ret < 0 || max_link_speed > 4)
++		pcie->gen = 0;
++	else
++		pcie->gen = max_link_speed;
++
++	return 0;
++}
++
++static const struct dm_pci_ops brcm_pcie_ops = {
++	.read_config	= brcm_pcie_read_config,
++	.write_config	= brcm_pcie_write_config,
++};
++
++static const struct udevice_id brcm_pcie_ids[] = {
++	{ .compatible = "brcm,bcm2711-pcie" },
++	{ }
++};
++
++U_BOOT_DRIVER(pcie_brcm_base) = {
++	.name			= "pcie_brcm",
++	.id			= UCLASS_PCI,
++	.ops			= &brcm_pcie_ops,
++	.of_match		= brcm_pcie_ids,
++	.probe			= brcm_pcie_probe,
++	.ofdata_to_platdata	= brcm_pcie_ofdata_to_platdata,
++	.priv_auto_alloc_size	= sizeof(struct brcm_pcie),
++};
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0010-configs-Enable-support-for-the-XHCI-controller-on-RP.patch

@@ -0,0 +1,102 @@
+From 66537b5984af81b5add420df9eb64c508268f581 Mon Sep 17 00:00:00 2001
+Message-Id: <66537b5984af81b5add420df9eb64c508268f581.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Mon, 25 May 2020 13:39:59 +0200
+Subject: [PATCH 10/20] configs: Enable support for the XHCI controller on RPI4
+ board (ARM 64-bit)
+
+This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
+and USB commands. To get it working one has to call the following commands:
+"pci enum; usb start;", thus such commands have been added to the default
+"preboot" environment variable. One has to update their environment if it
+is already configured to get this feature working out of the box.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
+---
+ configs/rpi_4_defconfig     | 9 +++++++++
+ configs/rpi_arm64_defconfig | 8 +++++++-
+ 2 files changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
+index f0301dc8bc..b42efe6072 100644
+--- a/configs/rpi_4_defconfig
++++ b/configs/rpi_4_defconfig
+@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_ENV_SIZE=0x4000
+ CONFIG_DISTRO_DEFAULTS=y
+ CONFIG_OF_BOARD_SETUP=y
++CONFIG_USE_PREBOOT=y
++CONFIG_PREBOOT="pci enum; usb start;"
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
+@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_DFU=y
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_USB=y
+ CONFIG_CMD_FS_UUID=y
+ CONFIG_OF_BOARD=y
+ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y
+ CONFIG_MMC_SDHCI_BCM2835=y
+ CONFIG_DM_ETH=y
+ CONFIG_BCMGENET=y
++CONFIG_PCI=y
++CONFIG_DM_PCI=y
++CONFIG_PCI_BRCMSTB=y
+ CONFIG_PINCTRL=y
+ # CONFIG_PINCTRL_GENERIC is not set
+ # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_DM_USB_GADGET=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_MANUFACTURER="FSL"
+ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
+index d16c2388af..0feea7f0be 100644
+--- a/configs/rpi_arm64_defconfig
++++ b/configs/rpi_arm64_defconfig
+@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000
+ CONFIG_DISTRO_DEFAULTS=y
+ CONFIG_OF_BOARD_SETUP=y
+ CONFIG_USE_PREBOOT=y
+-CONFIG_PREBOOT="usb start"
++CONFIG_PREBOOT="pci enum; usb start;"
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
+ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_FS_UUID=y
+ CONFIG_OF_BOARD=y
+@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y
+ CONFIG_MMC_SDHCI_BCM2835=y
+ CONFIG_DM_ETH=y
+ CONFIG_BCMGENET=y
++CONFIG_PCI=y
++CONFIG_DM_PCI=y
++CONFIG_PCI_BRCMSTB=y
+ CONFIG_PINCTRL=y
+ # CONFIG_PINCTRL_GENERIC is not set
+ # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
+ CONFIG_USB_DWC2=y
+ CONFIG_USB_KEYBOARD=y
+ CONFIG_USB_HOST_ETHER=y
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0011-arm-rpi-Add-function-to-trigger-VL805-s-firmware-loa.patch

@@ -0,0 +1,131 @@
+From 2899e2cbe5412ee6f6a01855467fa37534ffc2be Mon Sep 17 00:00:00 2001
+Message-Id: <2899e2cbe5412ee6f6a01855467fa37534ffc2be.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:37:22 +0200
+Subject: [PATCH 11/20] arm: rpi: Add function to trigger VL805's firmware load
+
+On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
+may either be loaded directly from an EEPROM or, if not present, by the
+SoC's VideCore (the SoC's co-processor). Introduce the function that
+informs VideCore that VL805 may need its firmware loaded.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++
+ arch/arm/mach-bcm283x/include/mach/msg.h  |  7 ++++
+ arch/arm/mach-bcm283x/msg.c               | 46 +++++++++++++++++++++++
+ 3 files changed, 66 insertions(+)
+
+diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
+index 60e226ce1d..2ae2d3d97c 100644
+--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
++++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
+@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette {
+ 	} body;
+ };
+ 
++#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET          0x00030058
++
++struct bcm2835_mbox_tag_pci_dev_addr {
++	struct bcm2835_mbox_tag_hdr tag_hdr;
++	union {
++		struct {
++			u32 dev_addr;
++		} req;
++		struct {
++		} resp;
++	} body;
++};
++
+ /*
+  * Pass a raw u32 message to the VC, and receive a raw u32 back.
+  *
+diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h
+index 4afb08631b..e45c1bf010 100644
+--- a/arch/arm/mach-bcm283x/include/mach/msg.h
++++ b/arch/arm/mach-bcm283x/include/mach/msg.h
+@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
+ 			     int pixel_order, int alpha_mode, ulong *fb_basep,
+ 			     ulong *fb_sizep, int *pitchp);
+ 
++/**
++ * bcm2711_load_vl805_firmware() - get vl805's firmware loaded
++ *
++ * @return 0 if OK, -EIO on error
++ */
++int bcm2711_notify_vl805_reset(void);
++
+ #endif
+diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c
+index 94b75283f8..347aece3cd 100644
+--- a/arch/arm/mach-bcm283x/msg.c
++++ b/arch/arm/mach-bcm283x/msg.c
+@@ -7,6 +7,7 @@
+ #include <memalign.h>
+ #include <phys2bus.h>
+ #include <asm/arch/mbox.h>
++#include <linux/delay.h>
+ 
+ struct msg_set_power_state {
+ 	struct bcm2835_mbox_hdr hdr;
+@@ -40,6 +41,12 @@ struct msg_setup {
+ 	u32 end_tag;
+ };
+ 
++struct msg_notify_vl805_reset {
++	struct bcm2835_mbox_hdr hdr;
++	struct bcm2835_mbox_tag_pci_dev_addr dev_addr;
++	u32 end_tag;
++};
++
+ int bcm2835_power_on_module(u32 module)
+ {
+ 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
+@@ -151,3 +158,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
+ 
+ 	return 0;
+ }
++
++/*
++ * On the Raspberry Pi 4, after a PCI reset, VL805's (the xHCI chip) firmware
++ * may either be loaded directly from an EEPROM or, if not present, by the
++ * SoC's VideoCore. This informs VideoCore that VL805 needs its firmware
++ * loaded.
++ */
++int bcm2711_notify_vl805_reset(void)
++{
++	ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
++				 msg_notify_vl805_reset, 1);
++	int ret;
++
++	BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
++	BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,
++			      NOTIFY_XHCI_RESET);
++
++	/*
++	 * The pci device address is expected like this:
++	 *
++	 *   PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12
++	 *
++	 * But since RPi4's PCIe setup is hardwired, we know the address in
++	 * advance.
++	 */
++	msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000;
++
++	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
++				     &msg_notify_vl805_reset->hdr);
++	if (ret) {
++		printf("bcm2711: Faild to load vl805's firmware, %d\n", ret);
++		return -EIO;
++	}
++
++	udelay(200);
++
++	return 0;
++}
++
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0012-reset-Add-Raspberry-Pi-4-firmware-reset-controller.patch

@@ -0,0 +1,140 @@
+From e9925f97c2c31253e1ff62de4049d90e19884f55 Mon Sep 17 00:00:00 2001
+Message-Id: <e9925f97c2c31253e1ff62de4049d90e19884f55.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:37:23 +0200
+Subject: [PATCH 12/20] reset: Add Raspberry Pi 4 firmware reset controller
+
+Raspberry Pi 4's co-processor controls some of the board's HW
+initialization process, but it's up to Linux to trigger it when
+relevant. Introduce a reset controller capable of interfacing with
+RPi4's co-processor that models these firmware initialization routines as
+reset lines.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ drivers/reset/Kconfig                         | 10 ++++
+ drivers/reset/Makefile                        |  1 +
+ drivers/reset/reset-raspberrypi.c             | 60 +++++++++++++++++++
+ .../reset/raspberrypi,firmware-reset.h        | 13 ++++
+ 4 files changed, 84 insertions(+)
+ create mode 100644 drivers/reset/reset-raspberrypi.c
+ create mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h
+
+diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
+index 88d3be1593..d02c1522e5 100644
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -148,4 +148,14 @@ config RESET_IMX7
+ 	help
+ 	  Support for reset controller on i.MX7/8 SoCs.
+ 
++config RESET_RASPBERRYPI
++	bool "Raspberry Pi 4 Firmware Reset Controller Driver"
++	depends on DM_RESET && ARCH_BCM283X
++	default USB_XHCI_PCI
++	help
++	  Raspberry Pi 4's co-processor controls some of the board's HW
++	  initialization process, but it's up to Linux to trigger it when
++	  relevant. This driver provides a reset controller capable of
++	  interfacing with RPi4's co-processor and model these firmware
++	  initialization routines as reset lines.
+ endmenu
+diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
+index 0a044d5d8c..be54dae725 100644
+--- a/drivers/reset/Makefile
++++ b/drivers/reset/Makefile
+@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
+ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
+ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
++obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
+diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c
+new file mode 100644
+index 0000000000..e2d284e5ac
+--- /dev/null
++++ b/drivers/reset/reset-raspberrypi.c
+@@ -0,0 +1,60 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Raspberry Pi 4 firmware reset driver
++ *
++ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
++ */
++#include <common.h>
++#include <dm.h>
++#include <reset-uclass.h>
++#include <asm/arch/msg.h>
++#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
++
++static int raspberrypi_reset_request(struct reset_ctl *reset_ctl)
++{
++	if (reset_ctl->id >= RASPBERRYPI_FIRMWARE_RESET_NUM_IDS)
++		return -EINVAL;
++
++	return 0;
++}
++
++static int raspberrypi_reset_free(struct reset_ctl *reset_ctl)
++{
++	return 0;
++}
++
++static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl)
++{
++	switch (reset_ctl->id) {
++	case RASPBERRYPI_FIRMWARE_RESET_ID_USB:
++		bcm2711_notify_vl805_reset();
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static int raspberrypi_reset_deassert(struct reset_ctl *reset_ctl)
++{
++	return 0;
++}
++
++struct reset_ops raspberrypi_reset_ops = {
++	.request = raspberrypi_reset_request,
++	.rfree = raspberrypi_reset_free,
++	.rst_assert = raspberrypi_reset_assert,
++	.rst_deassert = raspberrypi_reset_deassert,
++};
++
++static const struct udevice_id raspberrypi_reset_ids[] = {
++	{ .compatible = "raspberrypi,firmware-reset" },
++	{ }
++};
++
++U_BOOT_DRIVER(raspberrypi_reset) = {
++	.name = "raspberrypi-reset",
++	.id = UCLASS_RESET,
++	.of_match = raspberrypi_reset_ids,
++	.ops = &raspberrypi_reset_ops,
++};
++
+diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
+new file mode 100644
+index 0000000000..1a4f4c7927
+--- /dev/null
++++ b/include/dt-bindings/reset/raspberrypi,firmware-reset.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (c) 2020 Nicolas Saenz Julienne
++ * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com>
++ */
++
++#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
++#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H
++
++#define RASPBERRYPI_FIRMWARE_RESET_ID_USB	0
++#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS	1
++
++#endif
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0013-configs-Enable-support-for-reset-controllers-on-RPi4.patch

@@ -0,0 +1,57 @@
+From d32b13ba58aa59a5ec0b71cfc2005bf1efd84ddf Mon Sep 17 00:00:00 2001
+Message-Id: <d32b13ba58aa59a5ec0b71cfc2005bf1efd84ddf.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:37:24 +0200
+Subject: [PATCH 13/20] configs: Enable support for reset controllers on RPi4
+
+This is required in order to access the reset controller used to
+initialize the board's xHCI chip.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ configs/rpi_4_32b_defconfig | 1 +
+ configs/rpi_4_defconfig     | 1 +
+ configs/rpi_arm64_defconfig | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
+index a36a249540..0df5c17d6e 100644
+--- a/configs/rpi_4_32b_defconfig
++++ b/configs/rpi_4_32b_defconfig
+@@ -28,6 +28,7 @@ CONFIG_DM_ETH=y
+ CONFIG_BCMGENET=y
+ CONFIG_PINCTRL=y
+ # CONFIG_PINCTRL_GENERIC is not set
++CONFIG_DM_RESET=y
+ # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
+index b42efe6072..f641ad3dfa 100644
+--- a/configs/rpi_4_defconfig
++++ b/configs/rpi_4_defconfig
+@@ -35,6 +35,7 @@ CONFIG_DM_PCI=y
+ CONFIG_PCI_BRCMSTB=y
+ CONFIG_PINCTRL=y
+ # CONFIG_PINCTRL_GENERIC is not set
++CONFIG_DM_RESET=y
+ # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
+index 0feea7f0be..4ce8469f43 100644
+--- a/configs/rpi_arm64_defconfig
++++ b/configs/rpi_arm64_defconfig
+@@ -32,6 +32,7 @@ CONFIG_DM_PCI=y
+ CONFIG_PCI_BRCMSTB=y
+ CONFIG_PINCTRL=y
+ # CONFIG_PINCTRL_GENERIC is not set
++CONFIG_DM_RESET=y
+ # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0014-usb-xhci-Add-reset-controller-support.patch

@@ -0,0 +1,106 @@
+From a39dcf665d8867875b104661bd6a6325f502c5f2 Mon Sep 17 00:00:00 2001
+Message-Id: <a39dcf665d8867875b104661bd6a6325f502c5f2.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Mon, 29 Jun 2020 18:37:25 +0200
+Subject: [PATCH 14/20] usb: xhci: Add reset controller support
+
+Some atypical users of xhci might need to manually reset their xHCI
+controller before starting the HCD setup. Check if a reset controller
+device is available to the PCI bus and trigger a reset.
+
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+---
+ drivers/usb/host/xhci-mem.c |  2 ++
+ drivers/usb/host/xhci.c     | 33 +++++++++++++++++++++++++++++++++
+ include/usb/xhci.h          |  2 ++
+ 3 files changed, 37 insertions(+)
+
+diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
+index f446520528..108f4bd8cf 100644
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -180,6 +180,8 @@ void xhci_cleanup(struct xhci_ctrl *ctrl)
+ 	xhci_free_virt_devices(ctrl);
+ 	free(ctrl->erst.entries);
+ 	free(ctrl->dcbaa);
++	if (reset_valid(&ctrl->reset))
++		reset_free(&ctrl->reset);
+ 	memset(ctrl, '\0', sizeof(struct xhci_ctrl));
+ }
+ 
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index ebd2954571..e252964d0d 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -190,6 +190,35 @@ static int xhci_start(struct xhci_hcor *hcor)
+ 	return ret;
+ }
+ 
++/**
++ * Resets XHCI Hardware
++ *
++ * @param ctrl	pointer to host controller
++ * @return 0 if OK, or a negative error code.
++ */
++static int xhci_reset_hw(struct xhci_ctrl *ctrl)
++{
++	int ret;
++
++	ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
++	if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
++		dev_err(ctrl->dev, "failed to get reset\n");
++		return ret;
++	}
++
++	if (reset_valid(&ctrl->reset)) {
++		ret = reset_assert(&ctrl->reset);
++		if (ret)
++			return ret;
++
++		ret = reset_deassert(&ctrl->reset);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
+ /**
+  * Resets the XHCI Controller
+  *
+@@ -1508,6 +1537,10 @@ int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
+ 
+ 	ctrl->dev = dev;
+ 
++	ret = xhci_reset_hw(ctrl);
++	if (ret)
++		goto err;
++
+ 	/*
+ 	 * XHCI needs to issue a Address device command to setup
+ 	 * proper device context structures, before it can interact
+diff --git a/include/usb/xhci.h b/include/usb/xhci.h
+index 1170c0ac69..7d34103fd5 100644
+--- a/include/usb/xhci.h
++++ b/include/usb/xhci.h
+@@ -16,6 +16,7 @@
+ #ifndef HOST_XHCI_H_
+ #define HOST_XHCI_H_
+ 
++#include <reset.h>
+ #include <asm/types.h>
+ #include <asm/cache.h>
+ #include <asm/io.h>
+@@ -1209,6 +1210,7 @@ struct xhci_ctrl {
+ #if CONFIG_IS_ENABLED(DM_USB)
+ 	struct udevice *dev;
+ #endif
++	struct reset_ctl reset;
+ 	struct xhci_hccr *hccr;	/* R/O registers, not need for volatile */
+ 	struct xhci_hcor *hcor;
+ 	struct xhci_doorbell_array *dba;
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0016-arm-update-comments-to-the-common-style.patch

@@ -0,0 +1,88 @@
+From 32d72ef4331597864189b73b309490ac48f4ac05 Mon Sep 17 00:00:00 2001
+Message-Id: <32d72ef4331597864189b73b309490ac48f4ac05.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Wed, 3 Jun 2020 14:43:41 +0200
+Subject: [PATCH 16/20] arm: update comments to the common style
+
+Update the comments in include/asm/system.h to the common style.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Reviewed-by: Tom Rini <trini@konsulko.com>
+---
+ arch/arm/include/asm/system.h | 23 ++++++++++++++---------
+ 1 file changed, 14 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+index 7a40b56acd..0243f76e76 100644
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -205,7 +205,7 @@ int __asm_invalidate_l3_icache(void);
+ void __asm_switch_ttbr(u64 new_ttbr);
+ 
+ /*
+- * Switch from EL3 to EL2 for ARMv8
++ * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
+  *
+  * @args:        For loading 64-bit OS, fdt address.
+  *               For loading 32-bit OS, zero.
+@@ -220,7 +220,7 @@ void __asm_switch_ttbr(u64 new_ttbr);
+ void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
+ 				    u64 arg4, u64 entry_point, u64 es_flag);
+ /*
+- * Switch from EL2 to EL1 for ARMv8
++ * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
+  *
+  * @args:        For loading 64-bit OS, fdt address.
+  *               For loading 32-bit OS, zero.
+@@ -246,11 +246,12 @@ void flush_l3_cache(void);
+ void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
+ 
+ /*
+- *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
++ * smc_call() - issue a secure monitor call
++ *
++ * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+  * DEN0028A
+  *
+  * @args: input and output arguments
+- *
+  */
+ void smc_call(struct pt_regs *args);
+ 
+@@ -519,10 +520,12 @@ enum {
+ #endif
+ 
+ /**
++ * mmu_page_table_flush() - register an update to page tables
++ *
+  * Register an update to the page tables, and flush the TLB
+  *
+- * \param start		start address of update in page table
+- * \param stop		stop address of update in page table
++ * @start:	start address of update in page table
++ * @stop:	stop address of update in page table
+  */
+ void mmu_page_table_flush(unsigned long start, unsigned long stop);
+ 
+@@ -583,11 +586,13 @@ s32 psci_features(u32 function_id, u32 psci_fid);
+ void save_boot_params_ret(void);
+ 
+ /**
++ * mmu_set_region_dcache_behaviour() - set cache settings
++ *
+  * Change the cache settings for a region.
+  *
+- * \param start		start address of memory region to change
+- * \param size		size of memory region to change
+- * \param option	dcache option to select
++ * @start:	start address of memory region to change
++ * @size:	size of memory region to change
++ * @option:	dcache option to select
+  */
+ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ 				     enum dcache_option option);
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0017-arm-provide-a-function-for-boards-init-code-to-modif.patch

@@ -0,0 +1,130 @@
+From 82a944e4d1356e9ab3c87e6dc57b1b7213cbb233 Mon Sep 17 00:00:00 2001
+Message-Id: <82a944e4d1356e9ab3c87e6dc57b1b7213cbb233.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Wed, 3 Jun 2020 14:43:42 +0200
+Subject: [PATCH 17/20] arm: provide a function for boards init code to modify
+ MMU virtual-physical map
+
+Provide function for setting arbitrary virtual-physical MMU mapping
+and cache settings for the given region.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Reviewed-by: Tom Rini <trini@konsulko.com>
+---
+ arch/arm/include/asm/mmu.h    |  8 ++++++++
+ arch/arm/include/asm/system.h | 13 +++++++++++++
+ arch/arm/lib/cache-cp15.c     | 24 ++++++++++++++++++------
+ 3 files changed, 39 insertions(+), 6 deletions(-)
+ create mode 100644 arch/arm/include/asm/mmu.h
+
+diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
+new file mode 100644
+index 0000000000..9ac16f599e
+--- /dev/null
++++ b/arch/arm/include/asm/mmu.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++
++#ifndef __ASM_ARM_MMU_H
++#define __ASM_ARM_MMU_H
++
++void init_addr_map(void);
++
++#endif
+diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+index 0243f76e76..f9290fa9b6 100644
+--- a/arch/arm/include/asm/system.h
++++ b/arch/arm/include/asm/system.h
+@@ -585,6 +585,19 @@ s32 psci_features(u32 function_id, u32 psci_fid);
+  */
+ void save_boot_params_ret(void);
+ 
++/**
++ * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
++ *
++ * Change the virt/phys mapping and cache settings for a region.
++ *
++ * @virt:	virtual start address of memory region to change
++ * @phys:	physical address for the memory region to set
++ * @size:	size of memory region to change
++ * @option:	dcache option to select
++ */
++void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
++					size_t size, enum dcache_option option);
++
+ /**
+  * mmu_set_region_dcache_behaviour() - set cache settings
+  *
+diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
+index 1da2e92fe2..39717610d4 100644
+--- a/arch/arm/lib/cache-cp15.c
++++ b/arch/arm/lib/cache-cp15.c
+@@ -25,7 +25,8 @@ __weak void arm_init_domains(void)
+ {
+ }
+ 
+-void set_section_dcache(int section, enum dcache_option option)
++static void set_section_phys(int section, phys_addr_t phys,
++			     enum dcache_option option)
+ {
+ #ifdef CONFIG_ARMV7_LPAE
+ 	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+@@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option)
+ #endif
+ 
+ 	/* Add the page offset */
+-	value |= ((u32)section << MMU_SECTION_SHIFT);
++	value |= phys;
+ 
+ 	/* Add caching bits */
+ 	value |= option;
+@@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option)
+ 	page_table[section] = value;
+ }
+ 
++void set_section_dcache(int section, enum dcache_option option)
++{
++	set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
++}
++
+ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
+ {
+ 	debug("%s: Warning: not implemented\n", __func__);
+ }
+ 
+-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+-				     enum dcache_option option)
++void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
++					size_t size, enum dcache_option option)
+ {
+ #ifdef CONFIG_ARMV7_LPAE
+ 	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+@@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ 	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
+ 	      option);
+ #endif
+-	for (upto = start; upto < end; upto++)
+-		set_section_dcache(upto, option);
++	for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
++		set_section_phys(upto, phys, option);
+ 
+ 	/*
+ 	 * Make sure range is cache line aligned
+@@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ 	mmu_page_table_flush(startpt, stoppt);
+ }
+ 
++void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
++				     enum dcache_option option)
++{
++	mmu_set_region_dcache_behaviour_phys(start, start, size, option);
++}
++
+ __weak void dram_bank_mmu_setup(int bank)
+ {
+ 	bd_t *bd = gd->bd;
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0018-mmc-bcm283x-fix-int-to-pointer-cast.patch

@@ -0,0 +1,33 @@
+From 2904bea082a1524b13af6afed08a7f5ee9faf0ae Mon Sep 17 00:00:00 2001
+Message-Id: <2904bea082a1524b13af6afed08a7f5ee9faf0ae.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Seung-Woo Kim <sw0312.kim@samsung.com>
+Date: Wed, 3 Jun 2020 14:43:43 +0200
+Subject: [PATCH 18/20] mmc: bcm283x: fix int to pointer cast
+
+On build with 32 bit, there is a warning for int-to-pointer-cast.
+Fix the int to pointer cast by using uintptr_t.
+
+Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+---
+ drivers/mmc/bcm2835_sdhci.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
+index dc3dffb657..5cdf3c506f 100644
+--- a/drivers/mmc/bcm2835_sdhci.c
++++ b/drivers/mmc/bcm2835_sdhci.c
+@@ -210,7 +210,7 @@ static int bcm2835_sdhci_probe(struct udevice *dev)
+ 	priv->last_write = 0;
+ 
+ 	host->name = dev->name;
+-	host->ioaddr = (void *)base;
++	host->ioaddr = (void *)(uintptr_t)base;
+ 	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
+ 		SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
+ 	host->max_clk = emmc_freq;
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0019-rpi4-add-a-mapping-for-the-PCIe-XHCI-controller-MMIO.patch

@@ -0,0 +1,85 @@
+From a8c492ef2a3a73d435765ce28944efebce5cfa17 Mon Sep 17 00:00:00 2001
+Message-Id: <a8c492ef2a3a73d435765ce28944efebce5cfa17.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Wed, 3 Jun 2020 14:43:44 +0200
+Subject: [PATCH 19/20] rpi4: add a mapping for the PCIe XHCI controller MMIO
+ registers (ARM 32bit)
+
+Create a non-cacheable mapping for the 0x600000000 physical memory region,
+where MMIO registers for the PCIe XHCI controller are instantiated by the
+PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
+32bit mode, this region is mapped at 0xff800000 CPU virtual address.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+---
+ arch/arm/mach-bcm283x/Kconfig             |  1 +
+ arch/arm/mach-bcm283x/include/mach/base.h |  8 ++++++++
+ arch/arm/mach-bcm283x/init.c              | 21 +++++++++++++++++++++
+ 3 files changed, 30 insertions(+)
+
+diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
+index e6eb904e7f..b3287ce8bc 100644
+--- a/arch/arm/mach-bcm283x/Kconfig
++++ b/arch/arm/mach-bcm283x/Kconfig
+@@ -36,6 +36,7 @@ config BCM2711_32B
+ 	select BCM2711
+ 	select ARMV7_LPAE
+ 	select CPU_V7A
++	select PHYS_64BIT
+ 
+ config BCM2711_64B
+ 	bool "Broadcom BCM2711 SoC 64-bit support"
+diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
+index c4ae39852f..4ccaf69693 100644
+--- a/arch/arm/mach-bcm283x/include/mach/base.h
++++ b/arch/arm/mach-bcm283x/include/mach/base.h
+@@ -8,4 +8,12 @@
+ 
+ extern unsigned long rpi_bcm283x_base;
+ 
++#ifdef CONFIG_ARMV7_LPAE
++#ifdef CONFIG_TARGET_RPI_4_32B
++#include <addr_map.h>
++#define phys_to_virt addrmap_phys_to_virt
++#define virt_to_phys addrmap_virt_to_phys
++#endif
++#endif
++
+ #endif
+diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
+index cf4c5b245d..f2a5411623 100644
+--- a/arch/arm/mach-bcm283x/init.c
++++ b/arch/arm/mach-bcm283x/init.c
+@@ -146,6 +146,27 @@ int mach_cpu_init(void)
+ }
+ 
+ #ifdef CONFIG_ARMV7_LPAE
++#ifdef CONFIG_TARGET_RPI_4_32B
++#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT	0xff800000UL
++#include <addr_map.h>
++#include <asm/system.h>
++
++void init_addr_map(void)
++{
++	mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
++					     BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
++					     BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
++					     DCACHE_OFF);
++
++	/* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
++	addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
++	/* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
++	addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
++			  BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
++			  BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
++}
++#endif
++
+ void enable_caches(void)
+ {
+ 	dcache_enable();
+-- 
+2.27.0
+

buildroot-external/patches/uboot/2020.07/0020-config-Enable-support-for-the-XHCI-controller-on-RPI.patch

@@ -0,0 +1,71 @@
+From 52d942897bcf2c775c3c5dff9f811e1a28f3fd7d Mon Sep 17 00:00:00 2001
+Message-Id: <52d942897bcf2c775c3c5dff9f811e1a28f3fd7d.1595101389.git.stefan@agner.ch>
+In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Wed, 3 Jun 2020 14:43:45 +0200
+Subject: [PATCH 20/20] config: Enable support for the XHCI controller on RPI4
+ board
+
+This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
+and USB commands. To get it working one has to call the following commands:
+"pci enum; usb start;", thus such commands have been added to the default
+"preboot" environment variable. One has to update their environment if it
+is already configured to get this feature working out of the box.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+---
+ configs/rpi_4_32b_defconfig | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
+index 0df5c17d6e..db7b781976 100644
+--- a/configs/rpi_4_32b_defconfig
++++ b/configs/rpi_4_32b_defconfig
+@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_ENV_SIZE=0x4000
+ CONFIG_DISTRO_DEFAULTS=y
+ CONFIG_OF_BOARD_SETUP=y
++CONFIG_USE_PREBOOT=y
++CONFIG_PREBOOT="pci enum; usb start;"
+ CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
+@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_DFU=y
+ CONFIG_CMD_GPIO=y
+ CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_USB=y
+ CONFIG_CMD_FS_UUID=y
+ CONFIG_OF_BOARD=y
+ CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+@@ -26,6 +30,9 @@ CONFIG_MMC_SDHCI_SDMA=y
+ CONFIG_MMC_SDHCI_BCM2835=y
+ CONFIG_DM_ETH=y
+ CONFIG_BCMGENET=y
++CONFIG_PCI=y
++CONFIG_DM_PCI=y
++CONFIG_PCI_BRCMSTB=y
+ CONFIG_PINCTRL=y
+ # CONFIG_PINCTRL_GENERIC is not set
+ CONFIG_DM_RESET=y
+@@ -33,6 +40,8 @@ CONFIG_DM_RESET=y
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_DM_USB_GADGET=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI=y
+ CONFIG_USB_GADGET=y
+ CONFIG_USB_GADGET_MANUFACTURER="FSL"
+ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+@@ -45,4 +54,6 @@ CONFIG_DM_VIDEO=y
+ CONFIG_SYS_WHITE_ON_BLACK=y
+ CONFIG_CONSOLE_SCROLL_LINES=10
+ CONFIG_PHYS_TO_BUS=y
++CONFIG_ADDR_MAP=y
++CONFIG_SYS_NUM_ADDR_MAP=2
+ CONFIG_OF_LIBFDT_OVERLAY=y
+-- 
+2.27.0
+

buildroot-external/rootfs-overlay/usr/lib/systemd/system/var-lib-NetworkManager.mount

@@ -1,7 +1,7 @@
 [Unit]
 Description=NetworkManager persistent data
-Requires=mnt-overlay.mount
-After=mnt-overlay.mount hassos-overlay.service
+Requires=mnt-data.mount
+After=mnt-data.mount
 Before=NetworkManager.service
 
 [Mount]

buildroot-external/rootfs-overlay/usr/sbin/hassos-cli

@@ -3,12 +3,6 @@
 # Run logging cli
 # ==============================================================================
 
-# Setup terminal size on serial console
-if [ "${TERM}" = "vt220" ] || [ "${TERM}" = "vt102" ] || \
-   [ "${TERM}" = "vt100" ]; then
-	resize
-fi
-
 # Run CLI container
 if [ "$(docker ps -q -f name=hassio_cli)" ]; then
     docker container exec \

scripts/enter.sh

@@ -2,11 +2,18 @@
 BUILDER_UID="$(id -u)"
 BUILDER_GID="$(id -g)"
 CACHE_DIR="${CACHE_DIR:-$HOME/hassos-cache}"
+ARGS="$*"
+COMMAND="${ARGS:-bash}"
 
 sudo mkdir -p "${CACHE_DIR}"
 sudo chown -R "${BUILDER_UID}:${BUILDER_GID}" "${CACHE_DIR}"
 sudo docker build -t hassos:local .
+
+# Make sure loop devices are present before starting the container
+sudo losetup -f > /dev/null
+
+# shellcheck disable=SC2086
 sudo docker run -it --rm --privileged \
   -v "$(pwd):/build" -v "${CACHE_DIR}:/cache" \
   -e BUILDER_UID="${BUILDER_UID}" -e BUILDER_GID="${BUILDER_GID}" \
-  hassos:local bash
+  hassos:local ${COMMAND}