Bump version to 2.6 (RC)

Prepare new release tree

.dockerignore

@@ -1,3 +1,7 @@
-buildroot
-buildroot-external
-buildroot-patches
+# We don't need this folder because we map the hole folder
+buildroot/
+buildroot-external/
+buildroot-patches/
+
+# Ignore too
+release/

.github/move.yml

@@ -1,13 +0,0 @@
-# Configuration for move-issues - https://github.com/dessant/move-issues
-
-# Delete the command comment. Ignored when the comment also contains other content
-deleteCommand: true
-# Close the source issue after moving
-closeSourceIssue: true
-# Lock the source issue after moving
-lockSourceIssue: false
-# Set custom aliases for targets
-# aliases:
-#   r: repo
-#   or: owner/repo
-

.travis.yml

@@ -0,0 +1,25 @@
+language: bash
+
+sudo: required
+service: docker
+
+addons:
+  apt:
+    packages:
+     - docker-ce
+
+before_install:
+  - shopt -s globstar
+  - docker pull koalaman/shellcheck
+
+script:
+ - docker run -v $(pwd):/mnt koalaman/shellcheck scripts/*.sh
+ - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/scripts/*.sh
+ - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/scripts/*.sh
+ - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/board/**/*.sh
+ - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/rootfs-overlay/usr/sbin/*
+ - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/rootfs-overlay/usr/libexec/*
+ - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/rootfs-overlay/usr/lib/rauc/*
+
+matrix:
+  fast_finish: true

Documentation/boards/nuc.md

@@ -0,0 +1,50 @@
+# Intel NUC
+
+This board configuration supports the Intel NUC mini PCs and compatibles. 
+Probably most recent computers will work.
+
+Requirements:
+- x86-64 support
+- UEFI boot
+- SATA/AHCI storage
+- Supported NIC:
+  - Intel Gigabit NIC (e1000, e1000e, igb)
+  - Realtek Gigabit NIC (r8169)
+  - Intel Wireless Wifi 802.11ac (iwlwifi, see below)
+
+## Tested Hardware
+
+| Device | Quirks | 
+|--------|-----------|
+| Intel NUC5CPYH |  |
+| Gigabyte GB-BPCE-3455 | needs 'nomodeset' in cmdline.txt if you want a console |
+
+
+## Wifi
+
+The following cards are supported:
+
+- Intel Wireless 3160
+- Intel Wireless 7260
+- Intel Wireless 7265
+- Intel Wireless-AC 3165
+- Intel Wireless-AC 3168
+- Intel Wireless-AC 8260
+- Intel Wireless-AC 8265
+- Intel Wireless-AC 9260
+- Intel Wireless-AC 9461
+- Intel Wireless-AC 9462
+- Intel Wireless-AC 9560
+
+## Bluetooth
+
+Bluetooth is untested.
+
+## Installation
+
+Currently there is no shiny installation method. Checklist:
+- Boot PC to live-environment using PXE or USB
+- Copy or download the hassos image into your live environment
+- zcat the image to local harddisk
+- Reboot
+

Documentation/boards/orangepi.md

@@ -0,0 +1,20 @@
+# Raspberry PI
+
+Supported Hardware:
+
+| Device | Board | 
+|--------|-----------|
+| Orange Pi Prime | opi-prime |
+
+## Serial console
+
+The serial port on the Orange Pi Prime is a 3 pin header located between the
+power and reset buttons. The pins are labelled away from the board edge. Flow
+control must be disabled in order to send data. The serial specs are 3.3V TTL,
+115200,8,n,1
+
+## I2C
+
+Add `dtparam=i2c0=on` to `cmdline.txt`
+
+[config]: ../configuration.md#automatic

Documentation/boards/ova.md

@@ -1,7 +1,7 @@
 # OVA
 
-The OVA stay for open virtual appliance. Currently we had remove the ova files and publish a vmdk virtual disk,
-until we have better OVF template to generate our OVA. This vmdk work with (maybe you need convert the disk):
+OVA stands for Open Virtual Appliance. Currently we had remove the ova files and publish a vmdk virtual disk,
+until we have better OVF template to generate our OVA. This VMDK work with (maybe you need convert the disk):
 - HyperV
 - VirtualBox
 - VMware

Documentation/configuration.md

@@ -3,18 +3,22 @@
 ## Automatic
 
 You can use an USB drive with HassOS to configure network options, SSH access to the host and to install updates.
-Format a USB stick with FAT32/EXT4/NTFS and name it `CONFIG`. Use the following directory structure within the USB drive:
+Format a USB stick with FAT32/EXT4/NTFS and name it `CONFIG`. Alternative you can create a `CONFIG` folder inside boot partition. Use the following directory structure within the USB drive:
 
 ```text
 network/
 modules/
+udev/
 authorized_keys
+timesyncd.conf
 hassos-xy.raucb
 ```
 
 - The `network` folder can contain any kind of NetworkManager connection files. For more information see [Network][network.md]. 
 - The `modules` folder is for modules-load configuration files.
+- The `udev` folder is for udev rules files.
 - The `authorized_keys` file activates debug SSH access on port `22222`. See [Debugging Hassio][debug-hassio].
+- The `timesyncd.conf` file allow you to set different NTP servers. HassOS won't boot without correct working time servers!
 - The `hassos-*.raucb` file is a firmware OTA update which will be installed. These can be found on on the [release][hassos-release] page. 
 
 You can put this USB stick into the device and it will be read on startup. You can also trigger this process later over the
@@ -30,10 +34,24 @@ You can edit or create a `cmdline.txt` in your boot partition. That will be read
 
 The kernel module folder `/etc/modules-load.d` is persistent and you can add your configuration files there. See [Systemd modules load][systemd-modules].
 
+### Udev rules
+
+The udev rules folder `/etc/udev/rules.d` is persistent and you can add your configuration files there.
+
 ### Network
 
 You can manual add, edit or remove connections configurations from `/etc/NetworkManager/system-connections`.
 
+### NTP
+
+You can manual edit the systemd timesync file on `/etc/systemd/timesyncd.conf`.
+Our default ntp configuration look like:
+```
+[Time]
+NTP=time1.google.com time2.google.com time3.google.com
+FallbackNTP=0.pool.ntp.org 1.pool.ntp.org 2.pool.ntp.org 3.pool.ntp.org
+```
+
 [systemd-modules]: https://www.freedesktop.org/software/systemd/man/modules-load.d.html
 [network.md]: network.md
 [hassos-release]: https://github.com/home-assistant/hassos/releases/

Documentation/deployment.md

@@ -9,14 +9,7 @@ We provide 3 different types of release builds:
 ## Versioning
 
 The format of version is *MAJOR.BUILD*. Everytime we create a new release with same userland, we bump the build number.
-The development use here own major number they will be bump for the stable version and the development version go to next major number.
-
-```
-0.x = development
-1.x = stable
-2.x = development
-3.x = stable
-```
+The development number they will be bump for the stable release version and the development version go to next major number.
 
 ## Git branch/Tag
 

Documentation/getting_started_development.md

@@ -0,0 +1,106 @@
+Getting started with Hassos development using Docker on GNU/Linux
+=================================================================
+
+First, install **docker** for your distribution - I'd advise to use your distro's provided packages, since that will make sure permissions et al. are sanely set up for what you are about to run. You're also expected to have your current user properly set up in in your sudoers policy, so that this account may elevate to root and execute arbitrary commands as UID 0 (this is required, since at some point during the build process, a new loopback device-backed filesystem image will be mounted inside a docker container - which requires a "privileged" container to run, which can only be done as root).
+
+Next, make sure the docker daemon is running:
+
+```
+$ sudo systemctl status docker
+● docker.service - Docker Application Container Engine
+   Loaded: loaded (/usr/lib/systemd/system/docker.service; disabled; vendor preset: disabled)
+   Active: inactive (dead)
+     Docs: https://docs.docker.com
+```
+
+My desktop distro doesn't start newly installed services by default, which means I'll have to manually fire up the `docker` service:
+
+```
+$ sudo systemctl start docker
+$ sudo systemctl --no-pager status docker -n0
+● docker.service - Docker Application Container Engine
+   Loaded: loaded (/usr/lib/systemd/system/docker.service; disabled; vendor preset: disabled)
+   Active: active (running) since Wed 2018-10-10 21:08:23 CEST; 25s ago
+     Docs: https://docs.docker.com
+ Main PID: 1531 (dockerd)
+    Tasks: 27 (limit: 4915)
+   Memory: 163.4M
+   CGroup: /system.slice/docker.service
+           ├─1531 /usr/bin/dockerd -H fd://
+           └─1539 docker-containerd --config /var/run/docker/containerd/containerd.toml
+```
+
+Now, change your working directory to your hassos repo checkout (please adapt pathnames as needed), make sure your intended changes to the source tree are applied (and committed, ideally :)), and execute the `enter.sh` helper script:
+
+```
+$ cd ~/codebase/hassos/
+$ sudo scripts/enter.sh
+Sending build context to Docker daemon  30.48MB
+Step 1/6 : FROM ubuntu:18.04
+[...]
+ ---> 4dc25a21556b
+Successfully built 4dc25a21556b
+Successfully tagged hassbuildroot:latest
+```
+
+Note that the current iteration of `enter.sh` will try to load the **overlayfs** kernel module, which is not strictly required for docker's operation, as far as I can tell. It's OK if loading that module fails; the shell script will continue executing. If everything works out, you will find yourself in an interactive login shell inside your docker container/build environment, where you can peek around:
+
+```
+root@somehashinhex:/build#
+root@somehashinhex:/build# make help
+[...]
+```
+
+The _hassos_ developers provide a Makefile that will build hassos images for a (rather long!) list of targets. For example run the command below to start building the _ova_ variant, and go make a cup of tea. Or fifteen.
+
+```
+root@0db6f7079872:/build# make ova
+[...]
+```
+
+That will result in a single VMDK image file at the very end of the build process. This image file is a compressed block device dump with a proper GPT partition table, prepared to ship into any OVA-compatible hypervisor's innards. For me, the end of the **ova** build steps looks like this:
+
+```
+[...]
+2097152+0 records out
+1073741824 bytes (1.1 GB, 1.0 GiB) copied, 12.2145 s, 87.9 MB/s
+make: Leaving directory '/build/buildroot'
+make: Entering directory '/build/buildroot'
+rm -rf /build/buildroot/output/target /build/buildroot/output/images /build/buildroot/output/host  \
+	/build/buildroot/output/build /build/buildroot/output/staging \
+	/build/buildroot/output/legal-info /build/buildroot/output/graphs
+make: Leaving directory '/build/buildroot'
+```
+
+The artifacts you just built are placed in the `target/` subdirectory:
+
+```
+root@fd292c061896:/build# ls -lh release/
+total 141M
+-rw-r--r-- 1 root root 141M Oct 10 20:22 hassos_ova-2.2.vmdk.gz
+```
+
+In order to be able to use this image file with the **qemu** hypervisor, you'll need to unpack it, and convert it to an image format that qemu can work with. Conveniently, the _hassos_ buildenv already provides all the tools we need for this conversion:
+
+```
+root@fd292c061896:/build# gunzip release/hassos_ova-2.2.vmdk.gz
+root@fd292c061896:/build# qemu-img convert -O qcow2 release/hassos_ova-2.2.vmdk release/hassos_ova-2.2.qcow2
+root@fd292c061896:/build# ls -lh release/
+total 673M
+-rw-r--r-- 1 root root 337M Oct 10 20:25 hassos_ova-2.2.qcow2
+-rw-r--r-- 1 root root 337M Oct 10 20:22 hassos_ova-2.2.vmdk
+```
+
+Now, exit the docker container's environment, and find the build artifacts in the `releases/` directory beneath your repository checkout dir. (The generated files will be owned by _root_; make sure to `chown` them to your user account, if needed.)
+
+From there, qemu can try to boot it. Since the generated image assumes UEFI support in the host/hypervisor, this is slightly more tricky than with "classic"(/legacy) MBR-based images. On the *Debian* host I use to run my qemu virtual machine on, you'll need to install the **ovmf** package, which is described as providing "UEFI firmware for 64-bit x86 virtual machines". That package will install a _TianoCore_-derived qemu UEFI image build at `/usr/share/OVMF/OVMF_CODE.fd`, which we'll use with qemu to boot the generated qcow2 image. (Please adapt pathnames as necessary, for example if you have installed the ovmf firmware image at another location.)
+
+```
+$ /usr/bin/qemu-system-x86_64 -enable-kvm -name hassos_ova -smp 2 -m 1024 -drive file=release/hassos_ova-2.2.qcow2,index=0,media=disk,if=ide,cache=none,format=qcow2 -drive file=/usr/share/ovmf/x64/OVMF_CODE.fd,if=pflash,format=raw,readonly=on
+```
+
+This should pop up qemu's SDL frontend, displaying _hassos_' VT/CLI environment. Specifying addtional options and flags to qemu for network access, keyboard layout et al. are left as an exercise for the reader.
+
+After the boot process has finished, you can log in to _hassos_ without a password, providing *root* as the username. From there, executing `login` on the *hassio>* shell prompt will yield a root shell in the host OS.
+
+Happy hacking! :)

Documentation/kernel.md

@@ -3,7 +3,10 @@
 
 | Board | Version |
 |-------|---------|
-| Open Virtual Applicance | 4.14.67 |
-| Raspberry Pi | 4.14.66 |
-| Tinker Board | 4.14.67 |
-| Odroid-C2 | 4.14.36 |
+| Open Virtual Applicance | 4.14.82 |
+| Raspberry Pi | 4.14.81 |
+| Tinker Board | 4.14.82 |
+| Odroid-C2 | 4.19.15 |
+| Odroid-XU4 | 4.19.15 |
+| Orangepi-Prime | 4.19.13 |
+| Intel NUC | 4.14.82 |

Documentation/network.md

@@ -1,10 +1,10 @@
 # Network
 
-HassOS uses NetworkManager to control the host network. In future releases, you will be able to set up the configuration using the API/UI. Currently only a manual configuration using NetworkManager connection files is supported. Without a configuration file, the device will use DHCP by default. These network connection files can be placed on a USB drive as described in [Configuration][configuration-usb].
+HassOS uses NetworkManager to control the host network. In future releases, you will be able to set up the configuration using the API/UI. Currently only a manual configuration using NetworkManager connection files is supported. Without a configuration file, the device will use DHCP by default. These network connection files can be placed on a USB drive and imported to the host as described in [Configuration][configuration-usb].
 
 ## Configuration Examples
 
-You can also read the [Official Manual][keyfile] or there are a lot of examples accross internet. The system is read-only, if you don't want the IP address to change every boot, you should set the UUID property with a generic [UUID4][uuid]. Inside the `network` folder create the file `my-network` and add the appropriate contents below:
+You can read the [Official Manual][keyfile] or find many configuration examples across the internet. The system is read-only, if you don't want the IP address to change on every boot, you should set the UUID property with a generic [UUID4][uuid]. Inside `\CONFIG\network\` on the USB or SD, create a file called `my-network` and add the appropriate contents below:
 
 ### Default
 
@@ -51,11 +51,13 @@ type=802-11-wireless
 [802-11-wireless]
 mode=infrastructure
 ssid=MY_SSID
+# Uncomment below if your SSID is not broadcasted
+#hidden=true
 
 [802-11-wireless-security]
 auth-alg=open
 key-mgmt=wpa-psk
-psk=MY_WLAN_SECRED_KEY
+psk=MY_WLAN_SECRET_KEY
 
 [ipv4]
 method=auto
@@ -67,20 +69,21 @@ method=auto
 
 ### Static IP
 
-Replace follow configuration:
+Replace the following configuration:
 
 ```ini
 [ipv4]
 method=manual
-address1=192.168.1.111/24,192.168.1.1
+address=192.168.1.111/24,192.168.1.1
 dns=8.8.8.8;8.8.4.4;
 ```
+For address, the value before the comma is the IP address and subnet prefix bitlength; the second value is the IP address of the gateway.
 
 ## Tips
 
 ### Reset network
 
-If you want reset the network configuration to default, use follow commands on the host:
+If you want to reset the network configuration back to the default DHCP settings, use the following commands on the host:
 
 ```bash
 $ rm /etc/NetworkManager/system-connections/*
@@ -97,6 +100,44 @@ If you have trouble with powersave you can do following:
 # Values are 0 (use default), 1 (ignore/don't touch), 2 (disable) or 3 (enable).
 powersave=0
 ```
+## Using nmcli to set a static IPV4 address
+
+Log into the HASSOS base system via a console:
+
+```
+Welcome to HassOS
+Hassio login:
+```
+Login as `root` (no password needed)
+
+At the `hassio >` prompt, type `login` (as instructed).
+
+From here you will use the `nmcli` configuration tool.
+
+`# nmcli connection show` will list the “HassOS default” connection in use.
+
+`# nmcli con show "HassOS default"` will list all the properties of the connection.
+
+`# nmcli con edit "HassOS default"` will put you in a position to edit the connection.
+
+`nmcli> print ipv4` will show you the ipv4 properties of this connection.
+
+To add your static IP address (select 'yes' for manual method);
+```
+nmcli> set ipv4.addresses 192.168.100.10/24
+Do you also want to set 'ipv4.method' to 'manual'? [yes]:
+```
+In addition I have found it is wise to set the dns server and the local gateway.  For most home routers these will be the same address.  If you are using Pi-Hole you can set the dns to that.
+```
+nmcli> set ipv4.dns 192.168.100.1
+nmcli> set ipv4.gateway 192.168.100.1
+nmcli> save
+nmcli> quit
+```
+
+If you now view the default connection `cat /etc/NetworkManager/system-connections/default` you should see the method is manual and the address is set.
+
+Doing a `nmcli con reload` does not always work so restart the VM.
 
 [keyfile]: https://developer.gnome.org/NetworkManager/stable/nm-settings.html
 [configuration-usb]: configuration.md

Makefile

@@ -0,0 +1,43 @@
+RELEASE_DIR = /build/release
+
+BUILDROOT=/build/buildroot
+BUILDROOT_EXTERNAL=/build/buildroot-external
+DEFCONFIG_DIR = $(BUILDROOT_EXTERNAL)/configs
+
+TARGETS := $(notdir $(patsubst %_defconfig,%,$(wildcard $(DEFCONFIG_DIR)/*_defconfig)))
+TARGETS_CONFIG := $(notdir $(patsubst %_defconfig,%-config,$(wildcard $(DEFCONFIG_DIR)/*_defconfig)))
+
+.NOTPARALLEL: $(TARGETS) $(TARGETS_CONFIG) all
+
+.PHONY: $(TARGETS) $(TARGETS_CONFIG) all clean help
+
+all: $(TARGETS)
+
+$(RELEASE_DIR):
+	mkdir -p $(RELEASE_DIR)
+
+$(TARGETS_CONFIG): %-config:
+	@echo "config $*"
+	$(MAKE) -C $(BUILDROOT) BR2_EXTERNAL=$(BUILDROOT_EXTERNAL) "$*_defconfig"
+
+$(TARGETS): %: $(RELEASE_DIR) %-config
+	@echo "build $@"
+	$(MAKE) -C $(BUILDROOT) BR2_EXTERNAL=$(BUILDROOT_EXTERNAL)
+	cp -f $(BUILDROOT)/output/images/hassos_* $(RELEASE_DIR)/
+
+	# Do not clean when building for one target
+ifneq ($(words $(filter $(TARGETS),$(MAKECMDGOALS))), 1)
+	@echo "clean $@"
+	$(MAKE) -C $(BUILDROOT) BR2_EXTERNAL=$(BUILDROOT_EXTERNAL) clean
+endif
+	@echo "finished $@"
+
+clean:
+	$(MAKE) -C $(BUILDROOT) BR2_EXTERNAL=$(BUILDROOT_EXTERNAL) clean
+
+help:
+	@echo "Supported targets: $(TARGETS)"
+	@echo "Run 'make <target>' to build a target image."
+	@echo "Run 'make all' to build all target images."
+	@echo "Run 'make clean' to clean the build output."
+	@echo "Run 'make <target>-config' to configure buildroot for a target."

README.md

@@ -3,12 +3,11 @@ Hass.io OS based on [buildroot](https://buildroot.org/). It's a hypervisor for D
 
 ## Focus
 
-- Linux kernel 4.14 (LT)
 - Barebox as bootloader on EFI
 - U-Boot as bootloader on IoT
 - RAUC for OTA updates
 - SquashFS LZ4 as filesystem
-- Docker 18.03.1
+- Docker 18.09.0
 - AppArmor protected
 - ZRAM LZ4 for /tmp, /var, swap
 - Run every supervisor

buildroot-external/board/asus/hassos-hook.sh

@@ -1,28 +1,28 @@
 #!/bin/bash
+# shellcheck disable=SC2155
 
 function hassos_pre_image() {
     local BOOT_DATA="$(path_boot_dir)"
     local SPL_IMG="$(path_spl_img)"
 
-    cp -t ${BOOT_DATA} \
-        ${BINARIES_DIR}/boot.scr \
-        ${BINARIES_DIR}/rk3288-tinker.dtb
+    cp -t "${BOOT_DATA}" \
+        "${BINARIES_DIR}/boot.scr" \
+        "${BINARIES_DIR}/rk3288-tinker.dtb"
 
-    echo "console=tty1" > ${BOOT_DATA}/cmdline.txt
+    echo "console=tty1" > "${BOOT_DATA}/cmdline.txt"
 
     # Create boot binary
-    rm -f ${BINARIES_DIR}/u-boot-spl-dtb.img
-    mkimage -n rk3288 -T rksd -d ${BINARIES_DIR}/u-boot-spl-dtb.bin ${BINARIES_DIR}/u-boot-spl-dtb.img
-    cat ${BINARIES_DIR}/u-boot-dtb.bin >> ${BINARIES_DIR}/u-boot-spl-dtb.img
+    rm -f "${BINARIES_DIR}/u-boot-spl-dtb.img"
+    mkimage -n rk3288 -T rksd -d "${BINARIES_DIR}/u-boot-spl-dtb.bin" "${BINARIES_DIR}/u-boot-spl-dtb.img"
+    cat "${BINARIES_DIR}/u-boot-dtb.bin" >> "${BINARIES_DIR}/u-boot-spl-dtb.img"
 
     # SPL
     create_spl_image
 
-    dd if=${BINARIES_DIR}/u-boot-spl-dtb.img of=${SPL_IMG} conv=notrunc bs=512 seek=64
+    dd if="${BINARIES_DIR}/u-boot-spl-dtb.img" of="${SPL_IMG}" conv=notrunc bs=512 seek=64
 }
 
 
 function hassos_post_image() {
     convert_disk_image_gz
 }
-

buildroot-external/board/asus/tinker/patches/README.md

@@ -0,0 +1,5 @@
+## Kernel
+https://github.com/armbian/build/tree/master/patch/kernel/rockchip-next
+
+## u-boot
+https://github.com/armbian/build/tree/master/patch/u-boot/u-boot-rockchip/board_tinkerboard

buildroot-external/board/asus/tinker/patches/uboot/0001-Support-HassOS-bootstate-partition.patch

@@ -1,29 +0,0 @@
-From 8458beb24f2540fff3c3faed4fa068553b9e474e Mon Sep 17 00:00:00 2001
-From: Pascal Vizeli <pvizeli@syshack.ch>
-Date: Wed, 8 Aug 2018 09:45:07 +0000
-Subject: [PATCH 1/1] Support HassOS bootstate partition
-
-Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
----
- env/mmc.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/env/mmc.c b/env/mmc.c
-index 5e3da6dca75..353f58a12c9 100644
---- a/env/mmc.c
-+++ b/env/mmc.c
-@@ -18,6 +18,11 @@
- #include <search.h>
- #include <errno.h>
- 
-+#undef CONFIG_SYS_MMC_ENV_DEV
-+#define CONFIG_SYS_MMC_ENV_DEV 1
-+#undef CONFIG_ENV_OFFSET
-+#define CONFIG_ENV_OFFSET 0x25100000
-+
- #define __STR(X) #X
- #define STR(X) __STR(X)
- 
--- 
-2.17.1
-

buildroot-external/board/asus/tinker/uboot-boot.ush

@@ -1,3 +1,17 @@
+
+part start mmc ${devnum} 6 mmc_env
+mmc dev ${devnum}
+setenv loadbootstate " \
+    echo 'loading env...'; \
+    mmc read ${ramdisk_addr_r} ${mmc_env} 0x40; \
+    env import -c ${ramdisk_addr_r} 0x8000;"
+
+setenv storebootstate " \
+    echo 'storing env...'; \
+    env export -c -s 0x8000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT; \
+    mmc write ${ramdisk_addr_r} ${mmc_env} 0x40;"
+
+run loadbootstate
 test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"
 test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3
 test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3
@@ -10,10 +24,10 @@ setenv bootargs_a "root=PARTUUID=8d3d53e3-6d49-4c38-8349-aff6859e82fd rootfstype
 setenv bootargs_b "root=PARTUUID=a3ec664e-32ce-4665-95ea-7ae90ce9aa20 rootfstype=squashfs ro"
 
 # Load extraargs
-fileenv mmc 1:1 ${ramdisk_addr_r} cmdline.txt cmdline
+fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
 
 # Load device tree
-fatload mmc 1:1 ${fdt_addr_r} rk3288-tinker.dtb
+fatload mmc ${devnum}:1 ${fdt_addr_r} rk3288-tinker.dtb
 
 setenv bootargs
 for BOOT_SLOT in "${BOOT_ORDER}"; do
@@ -23,26 +37,26 @@ for BOOT_SLOT in "${BOOT_ORDER}"; do
     if test ${BOOT_A_LEFT} -gt 0; then
       setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
       echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc 1:2 ${kernel_addr_r} zImage"
+      setenv load_kernel "ext4load mmc ${devnum}:2 ${kernel_addr_r} zImage"
       setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
     fi
   elif test "x${BOOT_SLOT}" = "xB"; then
     if test ${BOOT_B_LEFT} -gt 0; then
       setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
       echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
-      setenv load_kernel "ext4load mmc 1:4 ${kernel_addr_r} zImage"
+      setenv load_kernel "ext4load mmc ${devnum}:4 ${kernel_addr_r} zImage"
       setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
     fi
   fi
 done
 
 if test -n "${bootargs}"; then
-  saveenv
+  run storebootstate
 else
   echo "No valid slot found, resetting tries to 3"
   setenv BOOT_A_LEFT 3
   setenv BOOT_B_LEFT 3
-  saveenv
+  run storebootstate
   reset
 fi
 

buildroot-external/board/asus/tinker/uboot.config

@@ -2,5 +2,4 @@
 # CONFIG_DOS_PARTITION is not set
 CONFIG_DM_VIDEO=y
 CONFIG_CMD_FILEENV=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_OFFSET=0x25100000
+CONFIG_ENV_IS_NOWHERE=Y

buildroot-external/board/hardkernel/odroid-c2/hassos-hook.sh

@@ -1,4 +1,5 @@
 #!/bin/bash
+# shellcheck disable=SC2155
 
 function hassos_pre_image() {
     local BOOT_DATA="$(path_boot_dir)"
@@ -6,18 +7,18 @@ function hassos_pre_image() {
     local UBOOT_GXBB="${BINARIES_DIR}/u-boot.gxbb"
     local spl_img="$(path_spl_img)"
 
-    cp ${BINARIES_DIR}/boot.scr ${BOOT_DATA}/boot.scr
-    cp ${BOARD_DIR}/boot-env.txt ${BOOT_DATA}/config.txt
-    cp ${BINARIES_DIR}/meson-gxbb-odroidc2.dtb ${BOOT_DATA}/meson-gxbb-odroidc2.dtb
+    cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
+    cp "${BOARD_DIR}/boot-env.txt" "${BOOT_DATA}/config.txt"
+    cp "${BINARIES_DIR}/meson-gxbb-odroidc2.dtb" "${BOOT_DATA}/meson-gxbb-odroidc2.dtb"
 
-    echo "console=tty0 console=ttyAML0,115200n8" > ${BOOT_DATA}/cmdline.txt
+    echo "console=tty0 console=ttyAML0,115200n8" > "${BOOT_DATA}/cmdline.txt"
 
     # SPL
     create_spl_image
 
-    dd if=${BL1} of=${spl_img} conv=notrunc bs=1 count=440
-    dd if=${BL1} of=${spl_img} conv=notrunc bs=512 skip=1 seek=1
-    dd if=${UBOOT_GXBB} of=${spl_img} conv=notrunc bs=512 seek=97
+    dd if="${BL1}" of="${spl_img}" conv=notrunc bs=1 count=440
+    dd if="${BL1}" of="${spl_img}" conv=notrunc bs=512 skip=1 seek=1
+    dd if="${UBOOT_GXBB}" of="${spl_img}" conv=notrunc bs=512 seek=97
 }
 
 

buildroot-external/board/hardkernel/odroid-c2/patches/README

@@ -1,2 +0,0 @@
-kernel patches from
-https://github.com/superna9999/meta-meson/tree/sumo/recipes-kernel/linux/linux-yocto-meson64-4.14

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0001-ARM64-dts-meson-gxm-Add-support-for-Khadas-VIM2.patch

@@ -1,455 +0,0 @@
-From f802405c9aba2fb198d55fc010e7336f155c2713 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Wed, 2 Aug 2017 16:11:23 +0200
-Subject: [PATCH 01/39] ARM64: dts: meson-gxm: Add support for Khadas VIM2
-
-The Khadas VIM2 is a Single Board Computer, respin of the origin
-Khadas VIM board, using an Amlogic S912 SoC and more server oriented.
-
-It provides the same external connectors and header pinout, plus a SPI
-NOR Flash, a reprogrammable STM8S003 MCU, FPC Connector, Cooling FAN header
-and Pogo Pads Arrays.
-
-Cc: Gouwa <gouwa@szwesion.com>
-Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- Documentation/devicetree/bindings/arm/amlogic.txt  |   1 +
- arch/arm64/boot/dts/amlogic/Makefile               |   1 +
- .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts     | 399 +++++++++++++++++++++
- 3 files changed, 401 insertions(+)
- create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-
-diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
-index 4e4bc0b..a445997 100644
---- a/Documentation/devicetree/bindings/arm/amlogic.txt
-+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
-@@ -71,6 +71,7 @@ Board compatible values (alphabetically, grouped by SoC):
- 
-   - "amlogic,q200" (Meson gxm s912)
-   - "amlogic,q201" (Meson gxm s912)
-+  - "khadas,vim2" (Meson gxm s912)
-   - "kingnovel,r-box-pro" (Meson gxm S912)
-   - "nexbox,a1" (Meson gxm s912)
- 
-diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
-index 543416b..747bcc3 100644
---- a/arch/arm64/boot/dts/amlogic/Makefile
-+++ b/arch/arm64/boot/dts/amlogic/Makefile
-@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
-+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-new file mode 100644
-index 0000000..32c138e
---- /dev/null
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-@@ -0,0 +1,399 @@
-+/*
-+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
-+ * Copyright (c) 2017 BayLibre, SAS
-+ * Author: Neil Armstrong <narmstrong@baylibre.com>
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/thermal/thermal.h>
-+
-+#include "meson-gxm.dtsi"
-+
-+/ {
-+	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
-+	model = "Khadas VIM2";
-+
-+	aliases {
-+		serial0 = &uart_AO;
-+		serial1 = &uart_A;
-+		serial2 = &uart_AO_B;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x0 0x0 0x0 0x80000000>;
-+	};
-+
-+	adc-keys {
-+		compatible = "adc-keys";
-+		io-channels = <&saradc 0>;
-+		io-channel-names = "buttons";
-+		keyup-threshold-microvolt = <1710000>;
-+
-+		button-function {
-+			label = "Function";
-+			linux,code = <KEY_FN>;
-+			press-threshold-microvolt = <10000>;
-+		};
-+	};
-+
-+	emmc_pwrseq: emmc-pwrseq {
-+		compatible = "mmc-pwrseq-emmc";
-+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
-+	};
-+
-+	gpio_fan: gpio-fan {
-+		compatible = "gpio-fan";
-+		gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
-+			 &gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
-+		/* Dummy RPM values since fan is optional */
-+		gpio-fan,speed-map = <0 0
-+				      1 1
-+				      2 2
-+				      3 3>;
-+		cooling-min-level = <0>;
-+		cooling-max-level = <3>;
-+		#cooling-cells = <2>;
-+	};
-+
-+	gpio-keys-polled {
-+		compatible = "gpio-keys-polled";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		poll-interval = <100>;
-+
-+		button@0 {
-+			label = "power";
-+			linux,code = <KEY_POWER>;
-+			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	hdmi-connector {
-+		compatible = "hdmi-connector";
-+		type = "a";
-+
-+		port {
-+			hdmi_connector_in: endpoint {
-+				remote-endpoint = <&hdmi_tx_tmds_out>;
-+			};
-+		};
-+	};
-+
-+	pwmleds {
-+		compatible = "pwm-leds";
-+
-+		power {
-+			label = "vim:red:power";
-+			pwms = <&pwm_AO_ab 1 7812500 0>;
-+			max-brightness = <255>;
-+			linux,default-trigger = "default-on";
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
-+		clocks = <&wifi32k>;
-+		clock-names = "ext_clock";
-+	};
-+
-+	thermal-zones {
-+		cpu-thermal {
-+			polling-delay-passive = <250>; /* milliseconds */
-+			polling-delay = <1000>; /* milliseconds */
-+
-+			thermal-sensors = <&scpi_sensors 0>;
-+
-+			trips {
-+				cpu_alert0: cpu-alert0 {
-+					temperature = <70000>; /* millicelsius */
-+					hysteresis = <2000>; /* millicelsius */
-+					type = "active";
-+				};
-+
-+				cpu_alert1: cpu-alert1 {
-+					temperature = <80000>; /* millicelsius */
-+					hysteresis = <2000>; /* millicelsius */
-+					type = "passive";
-+				};
-+			};
-+
-+			cooling-maps {
-+				map0 {
-+					trip = <&cpu_alert0>;
-+					cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
-+				};
-+
-+				map1 {
-+					trip = <&cpu_alert1>;
-+					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>;
-+				};
-+
-+				map2 {
-+					trip = <&cpu_alert1>;
-+					cooling-device =
-+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+
-+				map3 {
-+					trip = <&cpu_alert1>;
-+					cooling-device =
-+						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+		};
-+	};
-+
-+	vcc_3v3: regulator-vcc_3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VCC_3V3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+	};
-+
-+	vddio_ao18: regulator-vddio_ao18 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VDDIO_AO18";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+	};
-+
-+	vddio_boot: regulator-vddio_boot {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VDDIO_BOOT";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+	};
-+
-+	vddao_3v3: regulator-vddao_3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VDDAO_3V3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+	};
-+
-+	wifi32k: wifi32k {
-+		compatible = "pwm-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <32768>;
-+		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
-+	};
-+};
-+
-+&cec_AO {
-+	status = "okay";
-+	pinctrl-0 = <&ao_cec_pins>;
-+	pinctrl-names = "default";
-+	hdmi-phandle = <&hdmi_tx>;
-+};
-+
-+&cpu0 {
-+	cooling-min-level = <0>;
-+	cooling-max-level = <6>;
-+	#cooling-cells = <2>;
-+};
-+
-+&cpu4 {
-+	cooling-min-level = <0>;
-+	cooling-max-level = <4>;
-+	#cooling-cells = <2>;
-+};
-+
-+&ethmac {
-+	pinctrl-0 = <&eth_pins>;
-+	pinctrl-names = "default";
-+
-+	/* Select external PHY by default */
-+	phy-handle = <&external_phy>;
-+
-+	amlogic,tx-delay-ns = <2>;
-+
-+	/* External PHY reset is shared with internal PHY Led signals */
-+	snps,reset-gpio = <&gpio GPIOZ_14 0>;
-+	snps,reset-delays-us = <0 10000 1000000>;
-+	snps,reset-active-low;
-+
-+	/* External PHY is in RGMII */
-+	phy-mode = "rgmii";
-+
-+	status = "okay";
-+};
-+
-+&external_mdio {
-+	external_phy: ethernet-phy@0 {
-+		/* Realtek RTL8211F (0x001cc916) */
-+		reg = <0>;
-+	};
-+};
-+
-+&hdmi_tx {
-+	status = "okay";
-+	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&hdmi_tx_tmds_port {
-+	hdmi_tx_tmds_out: endpoint {
-+		remote-endpoint = <&hdmi_connector_in>;
-+	};
-+};
-+
-+&i2c_A {
-+	status = "okay";
-+	pinctrl-0 = <&i2c_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&i2c_B {
-+	status = "okay";
-+	pinctrl-0 = <&i2c_b_pins>;
-+	pinctrl-names = "default";
-+
-+	rtc: rtc@51 {
-+		/* has to be enabled manually when a battery is connected: */
-+		status = "disabled";
-+		compatible = "haoyu,hym8563";
-+		reg = <0x51>;
-+		#clock-cells = <0>;
-+		clock-frequency = <32768>;
-+		clock-output-names = "xin32k";
-+	};
-+};
-+
-+&ir {
-+	status = "okay";
-+	pinctrl-0 = <&remote_input_ao_pins>;
-+	pinctrl-names = "default";
-+	linux,rc-map-name = "rc-geekbox";
-+};
-+
-+&pwm_AO_ab {
-+	status = "okay";
-+	pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
-+	pinctrl-names = "default";
-+	clocks = <&clkc CLKID_FCLK_DIV4>;
-+	clock-names = "clkin0";
-+};
-+
-+&pwm_ef {
-+	status = "okay";
-+	pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
-+	pinctrl-names = "default";
-+	clocks = <&clkc CLKID_FCLK_DIV4>;
-+	clock-names = "clkin0";
-+};
-+
-+&sd_emmc_a {
-+	status = "okay";
-+	pinctrl-0 = <&sdio_pins>;
-+	pinctrl-names = "default";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	bus-width = <4>;
-+	max-frequency = <100000000>;
-+
-+	non-removable;
-+	disable-wp;
-+
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+
-+	vmmc-supply = <&vddao_3v3>;
-+	vqmmc-supply = <&vddio_boot>;
-+
-+	brcmf: wifi@1 {
-+		reg = <1>;
-+		compatible = "brcm,bcm4329-fmac";
-+	};
-+};
-+
-+/* SD card */
-+&sd_emmc_b {
-+	status = "okay";
-+	pinctrl-0 = <&sdcard_pins>;
-+	pinctrl-names = "default";
-+
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	max-frequency = <100000000>;
-+	disable-wp;
-+
-+	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
-+	cd-inverted;
-+
-+	vmmc-supply = <&vddao_3v3>;
-+	vqmmc-supply = <&vddio_boot>;
-+};
-+
-+/* eMMC */
-+&sd_emmc_c {
-+	status = "okay";
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
-+	pinctrl-names = "default";
-+
-+	bus-width = <8>;
-+	cap-sd-highspeed;
-+	cap-mmc-highspeed;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	disable-wp;
-+	mmc-ddr-1_8v;
-+	mmc-hs200-1_8v;
-+
-+	mmc-pwrseq = <&emmc_pwrseq>;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vddio_boot>;
-+};
-+
-+/*
-+ * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
-+ * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled
-+ */
-+&spifc {
-+	status = "disabled";
-+	pinctrl-0 = <&nor_pins>;
-+	pinctrl-names = "default";
-+
-+	w25q32: spi-flash@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "winbond,w25q16", "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <3000000>;
-+	};
-+};
-+
-+/* This one is connected to the Bluetooth module */
-+&uart_A {
-+	status = "okay";
-+	pinctrl-0 = <&uart_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
-+&uart_AO {
-+	status = "okay";
-+	pinctrl-0 = <&uart_ao_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
-+&uart_AO_B {
-+	status = "okay";
-+	pinctrl-0 = <&uart_ao_b_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&saradc {
-+	status = "okay";
-+	vref-supply = <&vddio_ao18>;
-+};
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0002-ARM64-dts-meson-gxbb-allow-child-devices-on-the-USB-.patch

@@ -1,41 +0,0 @@
-From 841ec7b8484dee021a15fdc187cdadc1c89220f2 Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Thu, 12 Jan 2017 01:38:26 +0100
-Subject: [PATCH 02/39] ARM64: dts: meson-gxbb: allow child devices on the USB
- controller
-
-Add the size and adress cells to the USB controllers to allow specifying
-child devices (for example the USB hub on the Odroid-C2 which must be
-taken out of reset to work).
-
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-index af834cd..7d38d55 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-@@ -73,6 +73,8 @@
- 
- 		usb0: usb@c9000000 {
- 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
- 			reg = <0x0 0xc9000000 0x0 0x40000>;
- 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- 			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
-@@ -85,6 +87,8 @@
- 
- 		usb1: usb@c9100000 {
- 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
- 			reg = <0x0 0xc9100000 0x0 0x40000>;
- 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- 			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0003-ARM64-dts-meson-gxbb-odroidc2-take-USB-hub-out-of-re.patch

@@ -1,34 +0,0 @@
-From 564bc89139a6bf0833cef64993dfe3fe2784c6a8 Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Thu, 12 Jan 2017 01:39:20 +0100
-Subject: [PATCH 03/39] ARM64: dts: meson-gxbb-odroidc2: take USB hub out of
- reset
-
-This takes the USB hub out of reset, otherwise the hub is not working.
-
-Fixes: 5a0803bd5ae ("ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes")
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-index 08b7bb7..c3a7b7f 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-@@ -310,4 +310,11 @@
- 
- &usb1 {
- 	status = "okay";
-+
-+	hub@1 {
-+		compatible = "usb5e3,610";
-+		reg = <1>;
-+		reset-gpios = <&gpio GPIOAO_4 GPIO_ACTIVE_LOW>;
-+		reset-duration-us = <3000>;
-+	};
- };
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0004-phy-meson-add-USB3-PHY-support-for-Meson-GXL.patch

@@ -1,260 +0,0 @@
-From 563fa3aaad2752079c8ee05819bf9923370f39aa Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Sat, 26 Nov 2016 15:56:32 +0100
-Subject: [PATCH 04/39] phy: meson: add USB3 PHY support for Meson GXL
-
-This adds USB3 PHY driver found on Meson GXL and GXM SoCs.
-
-Unfortunately there are no datasheets available for any of these PHYs.
-Both drivers were written by reading the reference drivers provided by
-Amlogic and analyzing the registers on the kernel that was shipped with
-my board.
-
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/phy/amlogic/Kconfig              |  13 ++
- drivers/phy/amlogic/Makefile             |   1 +
- drivers/phy/amlogic/phy-meson-gxl-usb3.c | 198 +++++++++++++++++++++++++++++++
- 3 files changed, 212 insertions(+)
- create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c
-
-diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
-index cb8f450..5d11a3e 100644
---- a/drivers/phy/amlogic/Kconfig
-+++ b/drivers/phy/amlogic/Kconfig
-@@ -13,6 +13,19 @@ config PHY_MESON8B_USB2
- 	  Meson8b and GXBB SoCs.
- 	  If unsure, say N.
- 
-+config PHY_MESON_GXL_USB3
-+	tristate "Meson GXL and GXM USB3 PHY drivers"
-+	default ARCH_MESON
-+	depends on OF && (ARCH_MESON || COMPILE_TEST)
-+	depends on USB_SUPPORT
-+	select USB_COMMON
-+	select GENERIC_PHY
-+	select REGMAP_MMIO
-+	help
-+	  Enable this to support the Meson USB3 PHY found in Meson
-+	  GXL and GXM SoCs.
-+	  If unsure, say N.
-+
- config PHY_MESON_GXL_USB2
- 	tristate "Meson GXL and GXM USB2 PHY drivers"
- 	default ARCH_MESON
-diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
-index cfdc987..4fd8848 100644
---- a/drivers/phy/amlogic/Makefile
-+++ b/drivers/phy/amlogic/Makefile
-@@ -1,2 +1,3 @@
- obj-$(CONFIG_PHY_MESON8B_USB2)		+= phy-meson8b-usb2.o
- obj-$(CONFIG_PHY_MESON_GXL_USB2)	+= phy-meson-gxl-usb2.o
-+obj-$(CONFIG_PHY_MESON_GXL_USB3)	+= phy-meson-gxl-usb3.o
-diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb3.c b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
-new file mode 100644
-index 0000000..9af5222
---- /dev/null
-+++ b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
-@@ -0,0 +1,198 @@
-+/*
-+ * Meson GXL USB3 PHY driver
-+ *
-+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/reset.h>
-+#include <linux/regmap.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb/of.h>
-+#include <linux/workqueue.h>
-+
-+#define USB_R0							0x00
-+	#define USB_R0_P30_FSEL_SHIFT				0
-+	#define USB_R0_P30_FSEL_MASK				GENMASK(5, 0)
-+	#define USB_R0_P30_PHY_RESET				BIT(6)
-+	#define USB_R0_P30_TEST_POWERDOWN_HSP			BIT(7)
-+	#define USB_R0_P30_TEST_POWERDOWN_SSP			BIT(8)
-+	#define USB_R0_P30_ACJT_LEVEL_SHIFT			9
-+	#define USB_R0_P30_ACJT_LEVEL_MASK			GENMASK(13, 9)
-+	#define USB_R0_P30_TX_BOOST_LEVEL_SHIFT			14
-+	#define USB_R0_P30_TX_BOOST_LEVEL_MASK			GENMASK(16, 14)
-+	#define USB_R0_P30_LANE0_TX2RX_LOOPBACK			BIT(17)
-+	#define USB_R0_P30_LANE0_EXT_PCLK_REQ			BIT(18)
-+	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_SHIFT		19
-+	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
-+	#define USB_R0_U2D_SS_SCALEDOWN_MODE_SHIFT		29
-+	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
-+	#define USB_R0_U2D_ACT					BIT(31)
-+
-+#define USB_R1							0x04
-+	#define USB_R1_U3H_BIGENDIAN_GS				BIT(0)
-+	#define USB_R1_U3H_PME_ENABLE				BIT(1)
-+	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_SHIFT		2
-+	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(6, 2)
-+	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_SHIFT		7
-+	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(11, 7)
-+	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_SHIFT		12
-+	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(15, 12)
-+	#define USB_R1_U3H_HOST_U3_PORT_DISABLE			BIT(16)
-+	#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT	BIT(17)
-+	#define USB_R1_U3H_HOST_MSI_ENABLE			BIT(18)
-+	#define USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT		19
-+	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
-+	#define USB_R1_P30_PCS_TX_SWING_FULL_SHIFT		25
-+	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)
-+
-+#define USB_R2							0x08
-+	#define USB_R2_P30_CR_DATA_IN_SHIFT			0
-+	#define USB_R2_P30_CR_DATA_IN_MASK			GENMASK(15, 0)
-+	#define USB_R2_P30_CR_READ				BIT(16)
-+	#define USB_R2_P30_CR_WRITE				BIT(17)
-+	#define USB_R2_P30_CR_CAP_ADDR				BIT(18)
-+	#define USB_R2_P30_CR_CAP_DATA				BIT(19)
-+	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_SHIFT		20
-+	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
-+	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_SHIFT		26
-+	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)
-+
-+#define USB_R3							0x0c
-+	#define USB_R3_P30_SSC_ENABLE				BIT(0)
-+	#define USB_R3_P30_SSC_RANGE_SHIFT			1
-+	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
-+	#define USB_R3_P30_SSC_REF_CLK_SEL_SHIFT		4
-+	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
-+	#define USB_R3_P30_REF_SSP_EN				BIT(13)
-+	#define USB_R3_P30_LOS_BIAS_SHIFT			16
-+	#define USB_R3_P30_LOS_BIAS_MASK			GENMASK(18, 16)
-+	#define USB_R3_P30_LOS_LEVEL_SHIFT			19
-+	#define USB_R3_P30_LOS_LEVEL_MASK			GENMASK(23, 19)
-+	#define USB_R3_P30_MPLL_MULTIPLIER_SHIFT		24
-+	#define USB_R3_P30_MPLL_MULTIPLIER_MASK			GENMASK(30, 24)
-+
-+#define USB_R4							0x10
-+	#define USB_R4_P21_PORT_RESET_0				BIT(0)
-+	#define USB_R4_P21_SLEEP_M0				BIT(1)
-+	#define USB_R4_MEM_PD_SHIFT				2
-+	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
-+	#define USB_R4_P21_ONLY					BIT(4)
-+
-+#define USB_R5							0x14
-+	#define USB_R5_ID_DIG_SYNC				BIT(0)
-+	#define USB_R5_ID_DIG_REG				BIT(1)
-+	#define USB_R5_ID_DIG_CFG_SHIFT				2
-+	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
-+	#define USB_R5_ID_DIG_EN_0				BIT(4)
-+	#define USB_R5_ID_DIG_EN_1				BIT(5)
-+	#define USB_R5_ID_DIG_CURR				BIT(6)
-+	#define USB_R5_ID_DIG_IRQ				BIT(7)
-+	#define USB_R5_ID_DIG_TH_SHIFT				8
-+	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
-+	#define USB_R5_ID_DIG_CNT_SHIFT				16
-+	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)
-+
-+/* read-only register */
-+#define USB_R6							0x18
-+	#define USB_R6_P30_CR_DATA_OUT_SHIFT			0
-+	#define USB_R6_P30_CR_DATA_OUT_MASK			GENMASK(15, 0)
-+	#define USB_R6_P30_CR_ACK				BIT(16)
-+
-+#define RESET_COMPLETE_TIME				500
-+
-+struct phy_meson_gxl_usb3_priv {
-+	struct regmap		*regmap;
-+	struct phy		*this_phy;
-+};
-+
-+static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = {
-+	.reg_bits = 32,
-+	.val_bits = 32,
-+	.reg_stride = 4,
-+	.max_register = USB_R6,
-+};
-+
-+static int phy_meson_gxl_usb3_power_on(struct phy *phy)
-+{
-+	struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
-+
-+	regmap_update_bits(priv->regmap, USB_R1,
-+			   USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
-+			   0x20 << USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT);
-+
-+	return 0;
-+}
-+
-+static const struct phy_ops phy_meson_gxl_usb3_ops = {
-+	.power_on	= phy_meson_gxl_usb3_power_on,
-+	.owner		= THIS_MODULE,
-+};
-+
-+static int phy_meson_gxl_usb3_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev->of_node;
-+	struct phy_meson_gxl_usb3_priv *priv;
-+	struct resource *res;
-+	struct phy *phy;
-+	struct phy_provider *phy_provider;
-+	void __iomem *base;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	base = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	priv->regmap = devm_regmap_init_mmio(dev, base,
-+					     &phy_meson_gxl_usb3_regmap_conf);
-+	if (IS_ERR(priv->regmap))
-+		return PTR_ERR(priv->regmap);
-+
-+	phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops);
-+	if (IS_ERR(phy)) {
-+		dev_err(dev, "failed to create PHY\n");
-+		return PTR_ERR(phy);
-+	}
-+
-+	phy_set_drvdata(phy, priv);
-+
-+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+
-+	return PTR_ERR_OR_ZERO(phy_provider);
-+}
-+
-+static const struct of_device_id phy_meson_gxl_usb3_of_match[] = {
-+	{ .compatible = "amlogic,meson-gxl-usb3-phy", },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match);
-+
-+static struct platform_driver phy_meson_gxl_usb3_driver = {
-+	.probe	= phy_meson_gxl_usb3_probe,
-+	.driver	= {
-+		.name		= "phy-meson-gxl-usb3",
-+		.of_match_table	= phy_meson_gxl_usb3_of_match,
-+	},
-+};
-+module_platform_driver(phy_meson_gxl_usb3_driver);
-+
-+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
-+MODULE_DESCRIPTION("Meson GXL USB3 PHY driver");
-+MODULE_LICENSE("GPL");
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0005-usb-host-add-a-generic-platform-USB-roothub-driver.patch

@@ -1,293 +0,0 @@
-From 8dca632003156c7a4f2eb6238b6e299f3df03c55 Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Tue, 10 Jan 2017 18:59:43 +0100
-Subject: [PATCH 05/39] usb: host: add a generic platform USB roothub driver
-
-Many SoC platforms have separate devices for the USB PHY which are
-registered through the generic PHY framework. These PHYs have to be
-enabled to make the USB controller actually work. They also have to be
-disabled again on shutdown/suspend.
-
-Currently (at least) the following HCI platform drivers are using custom
-code to obtain all PHYs via devicetree for the roothub/controller and
-disable/enable them when required:
-- ehci-platform.c has ehci_platform_power_{on,off}
-- xhci-mtk.c has xhci_mtk_phy_{init,exit,power_on,power_off}
-- ohci-platform.c has ohci_platform_power_{on,off}
-
-These drivers are not using the generic devicetree USB device bindings
-yet which were only introduced recently (documentation is available in
-devicetree/bindings/usb/usb-device.txt).
-With this new driver the usb2-phy and usb3-phy can be specified directly
-in the child-node of the corresponding port of the roothub via
-devicetree. This can be extended by not just parsing PHYs (some of the
-other drivers listed above are for example also parsing a list of clocks
-as well) when required.
-
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- .../devicetree/bindings/usb/usb-roothub.txt        |  46 +++++++
- drivers/usb/host/Kconfig                           |   3 +
- drivers/usb/host/Makefile                          |   2 +
- drivers/usb/host/platform-roothub.c                | 146 +++++++++++++++++++++
- drivers/usb/host/platform-roothub.h                |  14 ++
- 5 files changed, 211 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/usb/usb-roothub.txt
- create mode 100644 drivers/usb/host/platform-roothub.c
- create mode 100644 drivers/usb/host/platform-roothub.h
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-roothub.txt b/Documentation/devicetree/bindings/usb/usb-roothub.txt
-new file mode 100644
-index 0000000..23b24b6
---- /dev/null
-+++ b/Documentation/devicetree/bindings/usb/usb-roothub.txt
-@@ -0,0 +1,46 @@
-+Generic USB root-hub Properties
-+
-+similar to the USB device bindings (documented in usb-device.txt from the
-+current directory) this provides support for configuring the root-hub.
-+
-+Required properties:
-+- compatible: should be at least one of "usb1d6b,3", "usb1d6b,2"
-+- reg: must be 0.
-+- address-cells: must be 1
-+- size-cells: must be 0
-+
-+Required sub-nodes:
-+a sub-node per actual USB port is required. each sub-node supports the
-+following properties:
-+  Required properties:
-+    - reg: the port number on the root-hub (mandatory)
-+  Optional properties:
-+    - phys: optional, from the *Generic PHY* bindings (mandatory needed
-+      when phy-names is given)
-+    - phy-names: optional, from the *Generic PHY* bindings; supported names
-+      are "usb2-phy" or "usb3-phy"
-+
-+Example:
-+	&usb1 {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		roothub@0 {
-+			compatible = "usb1d6b,3", "usb1d6b,2";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0>;
-+
-+			port@1 {
-+				reg = <1>;
-+				usb-phy = <&usb2_phy1>, <&usb3_phy1>;
-+				phy-names = "usb2-phy", "usb3-phy";
-+			};
-+
-+			port@2 {
-+				reg = <2>;
-+				usb-phy = <&usb2_phy2>, <&usb3_phy2>;
-+				phy-names = "usb2-phy", "usb3-phy";
-+			};
-+		};
-+	}
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index 92b1972..598ca56 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -797,6 +797,9 @@ config USB_HCD_SSB
- 
- 	  If unsure, say N.
- 
-+config USB_PLATFORM_ROOTHUB
-+	bool
-+
- config USB_HCD_TEST_MODE
- 	bool "HCD test mode support"
- 	---help---
-diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
-index 4ab2689..873ebd9 100644
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -30,6 +30,8 @@ obj-$(CONFIG_USB_WHCI_HCD)	+= whci/
- 
- obj-$(CONFIG_USB_PCI)	+= pci-quirks.o
- 
-+obj-$(CONFIG_USB_PLATFORM_ROOTHUB)	+= platform-roothub.o
-+
- obj-$(CONFIG_USB_EHCI_HCD)	+= ehci-hcd.o
- obj-$(CONFIG_USB_EHCI_PCI)	+= ehci-pci.o
- obj-$(CONFIG_USB_EHCI_HCD_PLATFORM)	+= ehci-platform.o
-diff --git a/drivers/usb/host/platform-roothub.c b/drivers/usb/host/platform-roothub.c
-new file mode 100644
-index 0000000..84837e4
---- /dev/null
-+++ b/drivers/usb/host/platform-roothub.c
-@@ -0,0 +1,146 @@
-+/*
-+ * platform roothub driver - a virtual PHY device which passes all phy_*
-+ * function calls to multiple (actual) PHY devices. This is comes handy when
-+ * initializing all PHYs on a root-hub (to keep them all in the same state).
-+ *
-+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/list.h>
-+#include <linux/phy/phy.h>
-+#include <linux/of.h>
-+#include <linux/usb/of.h>
-+
-+#include "platform-roothub.h"
-+
-+#define ROOTHUB_PORTNUM		0
-+
-+struct platform_roothub {
-+	struct phy		*phy;
-+	struct list_head	list;
-+};
-+
-+static struct platform_roothub *platform_roothub_alloc(struct device *dev)
-+{
-+	struct platform_roothub *roothub_entry;
-+
-+	roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
-+	if (!roothub_entry)
-+		return ERR_PTR(-ENOMEM);
-+
-+	INIT_LIST_HEAD(&roothub_entry->list);
-+
-+	return roothub_entry;
-+}
-+
-+static int platform_roothub_add_phy(struct device *dev,
-+				    struct device_node *port_np,
-+				    const char *con_id, struct list_head *list)
-+{
-+	struct platform_roothub *roothub_entry;
-+	struct phy *phy = devm_of_phy_get(dev, port_np, con_id);
-+
-+	if (IS_ERR_OR_NULL(phy)) {
-+		if (!phy || PTR_ERR(phy) == -ENODEV)
-+			return 0;
-+		else
-+			return PTR_ERR(phy);
-+	}
-+
-+	roothub_entry = platform_roothub_alloc(dev);
-+	if (IS_ERR(roothub_entry))
-+		return PTR_ERR(roothub_entry);
-+
-+	roothub_entry->phy = phy;
-+
-+	list_add_tail(&roothub_entry->list, list);
-+
-+	return 0;
-+}
-+
-+struct platform_roothub *platform_roothub_init(struct device *dev)
-+{
-+	struct device_node *roothub_np, *port_np;
-+	struct platform_roothub *plat_roothub;
-+	int err;
-+
-+	roothub_np = usb_of_get_child_node(dev->of_node, ROOTHUB_PORTNUM);
-+	if (!of_device_is_available(roothub_np))
-+		return NULL;
-+
-+	plat_roothub = platform_roothub_alloc(dev);
-+	if (IS_ERR(plat_roothub))
-+		return plat_roothub;
-+
-+	for_each_available_child_of_node(roothub_np, port_np) {
-+		err = platform_roothub_add_phy(dev, port_np, "usb2-phy",
-+					       &plat_roothub->list);
-+		if (err)
-+			return ERR_PTR(err);
-+
-+		err = platform_roothub_add_phy(dev, port_np, "usb3-phy",
-+					       &plat_roothub->list);
-+		if (err)
-+			return ERR_PTR(err);
-+	}
-+
-+	return plat_roothub;
-+}
-+EXPORT_SYMBOL_GPL(platform_roothub_init);
-+
-+int platform_roothub_power_on(struct platform_roothub *plat_roothub)
-+{
-+	struct platform_roothub *roothub_entry;
-+	struct list_head *head;
-+	int err;
-+
-+	if (!plat_roothub)
-+		return 0;
-+
-+	head = &plat_roothub->list;
-+
-+	list_for_each_entry(roothub_entry, head, list) {
-+		err = phy_init(roothub_entry->phy);
-+		if (err)
-+			goto err_out;
-+
-+		err = phy_power_on(roothub_entry->phy);
-+		if (err) {
-+			phy_exit(roothub_entry->phy);
-+			goto err_out;
-+		}
-+	}
-+
-+	return 0;
-+
-+err_out:
-+	list_for_each_entry_continue_reverse(roothub_entry, head, list) {
-+		phy_power_off(roothub_entry->phy);
-+		phy_exit(roothub_entry->phy);
-+	}
-+
-+	return err;
-+}
-+EXPORT_SYMBOL_GPL(platform_roothub_power_on);
-+
-+void platform_roothub_power_off(struct platform_roothub *plat_roothub)
-+{
-+	struct platform_roothub *roothub_entry;
-+
-+	if (!plat_roothub)
-+		return;
-+
-+	list_for_each_entry_reverse(roothub_entry, &plat_roothub->list, list) {
-+		phy_power_off(roothub_entry->phy);
-+		phy_exit(roothub_entry->phy);
-+	}
-+}
-+EXPORT_SYMBOL_GPL(platform_roothub_power_off);
-diff --git a/drivers/usb/host/platform-roothub.h b/drivers/usb/host/platform-roothub.h
-new file mode 100644
-index 0000000..bde0bf2
---- /dev/null
-+++ b/drivers/usb/host/platform-roothub.h
-@@ -0,0 +1,14 @@
-+#ifndef USB_HOST_PLATFORM_ROOTHUB_H
-+#define USB_HOST_PLATFORM_ROOTHUB_H
-+
-+struct phy;
-+struct device_node;
-+
-+struct platform_roothub;
-+
-+struct platform_roothub *platform_roothub_init(struct device *dev);
-+
-+int platform_roothub_power_on(struct platform_roothub *plat_roothub);
-+void platform_roothub_power_off(struct platform_roothub *plat_roothub);
-+
-+#endif /* USB_HOST_PLATFORM_ROOTHUB_H */
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0006-usb-host-xhci-plat-integrate-the-platform-roothub.patch

@@ -1,146 +0,0 @@
-From 55ba20ef5868e2a1fc3cefe264539affe55ef6b7 Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Wed, 11 Jan 2017 11:34:59 +0100
-Subject: [PATCH 06/39] usb: host: xhci: plat: integrate the platform-roothub
-
-This enables the platform-roothub for the xhci-plat driver. This allows
-specifying a PHY for each port via devicetree. All PHYs will then be
-enabled/disabled by the platform-roothub driver.
-
-One example where this is required is the Amlogic GXL and GXM SoCs:
-They are using a dwc3 USB controller with up to three ports enabled on
-the internal roothub. Using only the top-level "phy" properties does not
-work here since one can only specify one "usb2-phy" and one "usb3-phy",
-while actually at least two "usb2-phy" have to be specified.
-
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- Documentation/devicetree/bindings/usb/usb-xhci.txt |  7 ++++++
- drivers/usb/host/Kconfig                           |  1 +
- drivers/usb/host/xhci-plat.c                       | 26 +++++++++++++++++++++-
- drivers/usb/host/xhci.h                            |  3 +++
- 4 files changed, 36 insertions(+), 1 deletion(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-index 7a69b8b..d0d8a67c 100644
---- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-@@ -30,6 +30,13 @@ Optional properties:
-   - usb3-lpm-capable: determines if platform is USB3 LPM capable
-   - quirk-broken-port-ped: set if the controller has broken port disable mechanism
- 
-+sub-nodes:
-+- optionally there can be a node for the root-hub, see usb-roothub.txt in the
-+  current directory
-+- one or more nodes with reg 1-31 for each port to which a device is connected.
-+  See usb-device.txt in the current directory for more information.
-+
-+
- Example:
- 	usb@f0931000 {
- 		compatible = "generic-xhci";
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index 598ca56..8c3b11f 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -36,6 +36,7 @@ config USB_XHCI_PCI
- config USB_XHCI_PLATFORM
- 	tristate "Generic xHCI driver for a platform device"
- 	select USB_XHCI_RCAR if ARCH_RENESAS
-+	select USB_PLATFORM_ROOTHUB
- 	---help---
- 	  Adds an xHCI host driver for a generic platform device, which
- 	  provides a memory space and an irq.
-diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
-index 1cb6eae..a80d585 100644
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -281,10 +281,20 @@ static int xhci_plat_probe(struct platform_device *pdev)
- 			goto put_usb3_hcd;
- 	}
- 
--	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
-+	xhci->platform_roothub = platform_roothub_init(sysdev);
-+	if (IS_ERR(xhci->platform_roothub)) {
-+		ret = PTR_ERR(xhci->platform_roothub);
-+		goto disable_clk;
-+	}
-+
-+	ret = platform_roothub_power_on(xhci->platform_roothub);
- 	if (ret)
- 		goto disable_usb_phy;
- 
-+	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
-+	if (ret)
-+		goto disable_platform_roothub;
-+
- 	if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
- 		xhci->shared_hcd->can_do_streams = 1;
- 
-@@ -307,6 +317,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
- dealloc_usb2_hcd:
- 	usb_remove_hcd(hcd);
- 
-+disable_platform_roothub:
-+	platform_roothub_power_off(xhci->platform_roothub);
-+
- disable_usb_phy:
- 	usb_phy_shutdown(hcd->usb_phy);
- 
-@@ -338,6 +351,8 @@ static int xhci_plat_remove(struct platform_device *dev)
- 	usb_remove_hcd(xhci->shared_hcd);
- 	usb_phy_shutdown(hcd->usb_phy);
- 
-+	platform_roothub_power_off(xhci->platform_roothub);
-+
- 	usb_remove_hcd(hcd);
- 	usb_put_hcd(xhci->shared_hcd);
- 
-@@ -370,6 +385,11 @@ static int __maybe_unused xhci_plat_suspend(struct device *dev)
- 	if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk))
- 		clk_disable_unprepare(xhci->clk);
- 
-+	if (ret)
-+		return ret;
-+
-+	platform_roothub_power_off(xhci->platform_roothub);
-+
- 	return ret;
- }
- 
-@@ -382,6 +402,10 @@ static int __maybe_unused xhci_plat_resume(struct device *dev)
- 	if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk))
- 		clk_prepare_enable(xhci->clk);
- 
-+	ret = platform_roothub_power_on(xhci->platform_roothub);
-+	if (ret)
-+		return ret;
-+
- 	ret = xhci_priv_resume_quirk(hcd);
- 	if (ret)
- 		return ret;
-diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
-index 2eaf6e1..552834c 100644
---- a/drivers/usb/host/xhci.h
-+++ b/drivers/usb/host/xhci.h
-@@ -34,6 +34,8 @@
- #include	"xhci-ext-caps.h"
- #include "pci-quirks.h"
- 
-+#include "platform-roothub.h"
-+
- /* xHCI PCI Configuration Registers */
- #define XHCI_SBRN_OFFSET	(0x60)
- 
-@@ -1735,6 +1737,7 @@ struct xhci_hcd {
- 	int		msix_count;
- 	/* optional clock */
- 	struct clk		*clk;
-+	struct platform_roothub	*platform_roothub;
- 	/* data structures */
- 	struct xhci_device_context_array *dcbaa;
- 	struct xhci_ring	*cmd_ring;
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0007-ARM64-dts-meson-gxl-add-USB-host-support.patch

@@ -1,99 +0,0 @@
-From 547f8ce14bfc3d315dc8b64d0e2eff0c7be897d2 Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Sun, 20 Nov 2016 00:23:52 +0100
-Subject: [PATCH 07/39] ARM64: dts: meson-gxl: add USB host support
-
-This adds USB host support to the Meson GXL SoC. A dwc3 controller is
-used for host-mode, while a dwc2 controller is used for device-mode only.
-The dwc3 controller's internal roothub has two USB2 ports enabled but no
-USB3 port. Each of the ports is supplied by a separate PHY. The USB pins
-are connected to the SoC's USBHOST_A and USBOTG_B pins.
-Due to the way the roothub works internally the USB PHYs are left
-enabled. When the dwc3 controller is disabled the PHY is never powered on
-so it does not draw any extra power. However, when the dwc3 host
-controller is enabled then all PHYs also have to be enabled, otherwise
-USB devices will not be detected (regardless of whether they are plugged
-into an enabled port or not). This means that only the dwc3 controller
-has to be enabled on boards with USB support (instead of requiring all
-boards to enable the PHYs additionally with the chance of forgetting to
-enable one and breaking all other ports with that as well).
-
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 59 ++++++++++++++++++++++++++++++
- 1 file changed, 59 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-index fb8d76a..68ea67a 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-@@ -57,6 +57,65 @@
- 			no-map;
- 		};
- 	};
-+
-+	soc {
-+
-+		usb0: usb@c9000000 {
-+			compatible = "snps,dwc3";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x0 0xc9000000 0x0 0x100000>;
-+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-+			dr_mode = "host";
-+			maximum-speed = "high-speed";
-+			snps,dis_u2_susphy_quirk;
-+			phys = <&usb3_phy0>;
-+			phy-names = "usb3-phy";
-+			status = "disabled";
-+
-+			dwc3_roothub: roothub@0 {
-+				compatible = "usb1d6b,3", "usb1d6b,2";
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				reg = <0>;
-+
-+				port@1 {
-+					reg = <1>;
-+					phys = <&usb2_phy0>;
-+					phy-names = "usb2-phy";
-+				};
-+
-+				port@2 {
-+					reg = <2>;
-+					phys = <&usb2_phy1>;
-+					phy-names = "usb2-phy";
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&apb {
-+	usb2_phy0: phy@78000 {
-+		compatible = "amlogic,meson-gxl-usb2-phy";
-+		#phy-cells = <0>;
-+		reg = <0x0 0x78000 0x0 0x20>;
-+		status = "okay";
-+	};
-+
-+	usb2_phy1: phy@78020 {
-+		compatible = "amlogic,meson-gxl-usb2-phy";
-+		#phy-cells = <0>;
-+		reg = <0x0 0x78020 0x0 0x20>;
-+		status = "okay";
-+	};
-+
-+	usb3_phy0: phy@78080 {
-+		compatible = "amlogic,meson-gxl-usb3-phy";
-+		#phy-cells = <0>;
-+		reg = <0x0 0x78080 0x0 0x20>;
-+		status = "okay";
-+	};
- };
- 
- &ethmac {
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0008-ARM64-dts-meson-gxm-add-GXM-specific-USB-host-config.patch

@@ -1,49 +0,0 @@
-From 48d4988f2b3b93a6f17c0d1d5e6d932664bc0c74 Mon Sep 17 00:00:00 2001
-From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Date: Sat, 26 Nov 2016 00:17:22 +0100
-Subject: [PATCH 08/39] ARM64: dts: meson-gxm: add GXM specific USB host
- configuration
-
-The USB configuration on GXM is slightly different than on GXL. The dwc3
-controller's internal hub has three USB2 ports (instead of 2 on GXL)
-along with a dedicated USB2 PHY for this port. However, it seems that
-there are no pins on GXM which would allow connecting the third port to
-a physical USB port.
-
-Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
-index 19a798d..5e4cb90 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
-@@ -121,6 +121,23 @@
- 	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
- };
- 
-+&apb {
-+	usb2_phy2: phy@78040 {
-+		compatible = "amlogic,meson-gxl-usb2-phy";
-+		#phy-cells = <0>;
-+		reg = <0x0 0x78040 0x0 0x20>;
-+		status = "disabled";
-+	};
-+};
-+
-+&dwc3_roothub {
-+	port@3 {
-+		reg = <3>;
-+		phys = <&usb2_phy2>;
-+		phy-names = "usb2-phy";
-+	};
-+};
-+
- &saradc {
- 	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
- };
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0009-ARM64-dts-meson-gx-Enable-USB-on-GXL-and-GXM-boards.patch

@@ -1,129 +0,0 @@
-From 1e5a4ee949281c47a03f5cee31226d803d396f48 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Thu, 13 Jul 2017 15:02:33 +0200
-Subject: [PATCH 09/39] ARM64: dts: meson-gx: Enable USB on GXL and GXM boards
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi            | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts     | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts   | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts    | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi          | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts          | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts            | 4 ++++
- arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts             | 4 ++++
- 9 files changed, 36 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-index 4157987..7ce9a62 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-@@ -236,3 +236,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+	status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
-index 977b424..6f2cd8e 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
-@@ -163,3 +163,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+       status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-index edc512a..89a5fd9 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-@@ -198,3 +198,7 @@
- 	pinctrl-0 = <&uart_ao_b_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+       status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-index 64c54c9..4035891 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-@@ -242,3 +242,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+       status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-index 1b8f328..6338e6c 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-@@ -251,3 +251,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+	status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-index 129af90..7a1c20e 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-@@ -173,3 +173,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+	status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-index 32c138e..103575a 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-@@ -397,3 +397,7 @@
- 	status = "okay";
- 	vref-supply = <&vddio_ao18>;
- };
-+
-+&usb0 {
-+       status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-index 22c6977..cfde246 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-@@ -215,3 +215,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+	status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
-index 470f72b..9837a48 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
-@@ -237,3 +237,7 @@
- 	pinctrl-0 = <&uart_ao_a_pins>;
- 	pinctrl-names = "default";
- };
-+
-+&usb0 {
-+       status = "okay";
-+};
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0010-ARM64-defconfig-add-CONFIG_MESON_EFUSE.patch

@@ -1,28 +0,0 @@
-From eb29dbaf90e217978d8abfab1912b11020825e28 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Mon, 13 Nov 2017 12:02:59 +0100
-Subject: [PATCH 10/39] ARM64: defconfig: add CONFIG_MESON_EFUSE
-
-Turn on CONFIG_MESON_EFUSE as module
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/configs/defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index 34480e9..3cdfc74 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -541,6 +541,7 @@ CONFIG_PHY_XGENE=y
- CONFIG_PHY_TEGRA_XUSB=y
- CONFIG_QCOM_L2_PMU=y
- CONFIG_QCOM_L3_PMU=y
-+CONFIG_MESON_EFUSE=m
- CONFIG_TEE=y
- CONFIG_OPTEE=y
- CONFIG_ARM_SCPI_PROTOCOL=y
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0011-ARM64-defconfig-enable-CEC-support.patch

@@ -1,36 +0,0 @@
-From 175366cb9e77fe54e6949f6599c0900cf0980b26 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Mon, 13 Nov 2017 12:09:40 +0100
-Subject: [PATCH 11/39] ARM64: defconfig: enable CEC support
-
-Turn on CONFIG_CEC_SUPPORT and CONFIG_CEC_PLATFORM_DRIVERS
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/configs/defconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index 3cdfc74..944b93b 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -350,6 +350,7 @@ CONFIG_MEDIA_SUPPORT=m
- CONFIG_MEDIA_CAMERA_SUPPORT=y
- CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
- CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_CEC_SUPPORT=y
- CONFIG_MEDIA_CONTROLLER=y
- CONFIG_MEDIA_RC_SUPPORT=y
- CONFIG_RC_CORE=m
-@@ -364,6 +365,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
- CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
- CONFIG_VIDEO_RENESAS_FCP=m
- CONFIG_VIDEO_RENESAS_VSP1=m
-+CONFIG_CEC_PLATFORM_DRIVERS=y
- CONFIG_DRM=m
- CONFIG_DRM_NOUVEAU=m
- CONFIG_DRM_EXYNOS=m
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0012-ARM64-defconfig-enable-CONFIG_VIDEO_MESON_AO_CEC.patch

@@ -1,28 +0,0 @@
-From c71be51a7778a6aa6b784dd0edc57951acf63ef2 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Mon, 13 Nov 2017 12:11:41 +0100
-Subject: [PATCH 12/39] ARM64: defconfig: enable CONFIG_VIDEO_MESON_AO_CEC
-
-Turn on CONFIG_VIDEO_MESON_AO_CEC as module
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/configs/defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index 944b93b..fdf94cb 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -366,6 +366,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
- CONFIG_VIDEO_RENESAS_FCP=m
- CONFIG_VIDEO_RENESAS_VSP1=m
- CONFIG_CEC_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_MESON_AO_CEC=m
- CONFIG_DRM=m
- CONFIG_DRM_NOUVEAU=m
- CONFIG_DRM_EXYNOS=m
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0013-ARM64-defconfig-enable-CONFIG_DRM_DW_HDMI_CEC.patch

@@ -1,28 +0,0 @@
-From 94fb1910e76e39cc910fb5b5a528712f4135891e Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Mon, 13 Nov 2017 12:15:18 +0100
-Subject: [PATCH 13/39] ARM64: defconfig: enable CONFIG_DRM_DW_HDMI_CEC
-
-Turn on CONFIG_DRM_DW_HDMI_CEC as module
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/configs/defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index fdf94cb..dcf1090 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -388,6 +388,7 @@ CONFIG_DRM_RCAR_VSP=y
- CONFIG_DRM_TEGRA=m
- CONFIG_DRM_PANEL_SIMPLE=m
- CONFIG_DRM_I2C_ADV7511=m
-+CONFIG_DRM_DW_HDMI_CEC=m
- CONFIG_DRM_VC4=m
- CONFIG_DRM_HISI_KIRIN=m
- CONFIG_DRM_MESON=m
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0014-clk-meson-gxbb-Add-VPU-and-VAPB-clockids.patch

@@ -1,55 +0,0 @@
-From 9bc414d9e18f8c9d39be44165b4926e2b2cdc1d9 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 16 Oct 2017 17:29:33 +0200
-Subject: [PATCH 14/39] clk: meson: gxbb: Add VPU and VAPB clockids
-
-Add the clkids for the clocks feeding the Video Processing Unit.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/clk/meson/gxbb.h              |  6 +++++-
- include/dt-bindings/clock/gxbb-clkc.h | 11 +++++++++++
- 2 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
-index 5b1d4b3..aee6fbb 100644
---- a/drivers/clk/meson/gxbb.h
-+++ b/drivers/clk/meson/gxbb.h
-@@ -190,8 +190,12 @@
- #define CLKID_SD_EMMC_B_CLK0_DIV  121
- #define CLKID_SD_EMMC_C_CLK0_SEL  123
- #define CLKID_SD_EMMC_C_CLK0_DIV  124
-+#define CLKID_VPU_0_DIV		  127
-+#define CLKID_VPU_1_DIV		  130
-+#define CLKID_VAPB_0_DIV	  134
-+#define CLKID_VAPB_1_DIV	  137
- 
--#define NR_CLKS			  126
-+#define NR_CLKS			  141
- 
- /* include the CLKIDs that have been made part of the DT binding */
- #include <dt-bindings/clock/gxbb-clkc.h>
-diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
-index 8c92528..8ba99a5 100644
---- a/include/dt-bindings/clock/gxbb-clkc.h
-+++ b/include/dt-bindings/clock/gxbb-clkc.h
-@@ -114,5 +114,16 @@
- #define CLKID_SD_EMMC_A_CLK0	119
- #define CLKID_SD_EMMC_B_CLK0	122
- #define CLKID_SD_EMMC_C_CLK0	125
-+#define CLKID_VPU_0_SEL		126
-+#define CLKID_VPU_0		128
-+#define CLKID_VPU_1_SEL		129
-+#define CLKID_VPU_1		131
-+#define CLKID_VPU		132
-+#define CLKID_VAPB_0_SEL	133
-+#define CLKID_VAPB_0		135
-+#define CLKID_VAPB_1_SEL	136
-+#define CLKID_VAPB_1		138
-+#define CLKID_VAPB_SEL		139
-+#define CLKID_VAPB		140
- 
- #endif /* __GXBB_CLKC_H */
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0015-clk-meson-gxbb-Add-VPU-and-VAPB-clocks-data.patch

@@ -1,357 +0,0 @@
-From a3b8b7bfd775fa521425c72856b4394fb6fec518 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Fri, 13 Oct 2017 14:38:37 +0200
-Subject: [PATCH 15/39] clk: meson: gxbb: Add VPU and VAPB clocks data
-
-The Amlogic Meson GX SoCs needs these two clocks to power up the
-VPU power domain.
-
-These two clocks are similar to the MALI clocks by having a glitch-free
-mux and two similar clocks with gate, divider and muxes.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/clk/meson/gxbb.c | 292 +++++++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 292 insertions(+)
-
-diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
-index 92168348..86cb5af 100644
---- a/drivers/clk/meson/gxbb.c
-+++ b/drivers/clk/meson/gxbb.c
-@@ -1131,6 +1131,253 @@ static struct clk_gate gxbb_sd_emmc_c_clk0 = {
- 	},
- };
- 
-+/* VPU Clock */
-+
-+static u32 mux_table_vpu[] = {0, 1, 2, 3};
-+static const char * const gxbb_vpu_parent_names[] = {
-+	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
-+};
-+
-+static struct clk_mux gxbb_vpu_0_sel = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.mask = 0x3,
-+	.shift = 9,
-+	.lock = &clk_lock,
-+	.table = mux_table_vpu,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vpu_0_sel",
-+		.ops = &clk_mux_ops,
-+		/*
-+		 * bits 9:10 selects from 4 possible parents:
-+		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
-+		 */
-+		.parent_names = gxbb_vpu_parent_names,
-+		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
-+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_divider gxbb_vpu_0_div = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.shift = 0,
-+	.width = 7,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vpu_0_div",
-+		.ops = &clk_divider_ops,
-+		.parent_names = (const char *[]){ "vpu_0_sel" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_gate gxbb_vpu_0 = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.bit_idx = 8,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data) {
-+		.name = "vpu_0",
-+		.ops = &clk_gate_ops,
-+		.parent_names = (const char *[]){ "vpu_0_div" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_mux gxbb_vpu_1_sel = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.mask = 0x3,
-+	.shift = 25,
-+	.lock = &clk_lock,
-+	.table = mux_table_vpu,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vpu_1_sel",
-+		.ops = &clk_mux_ops,
-+		/*
-+		 * bits 25:26 selects from 4 possible parents:
-+		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
-+		 */
-+		.parent_names = gxbb_vpu_parent_names,
-+		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
-+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_divider gxbb_vpu_1_div = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.shift = 16,
-+	.width = 7,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vpu_1_div",
-+		.ops = &clk_divider_ops,
-+		.parent_names = (const char *[]){ "vpu_1_sel" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_gate gxbb_vpu_1 = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.bit_idx = 24,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data) {
-+		.name = "vpu_1",
-+		.ops = &clk_gate_ops,
-+		.parent_names = (const char *[]){ "vpu_1_div" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_mux gxbb_vpu = {
-+	.reg = (void *)HHI_VPU_CLK_CNTL,
-+	.mask = 1,
-+	.shift = 31,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vpu",
-+		.ops = &clk_mux_ops,
-+		/*
-+		 * bit 31 selects from 2 possible parents:
-+		 * vpu_0 or vpu_1
-+		 */
-+		.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
-+		.num_parents = 2,
-+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+/* VAPB Clock */
-+
-+static u32 mux_table_vapb[] = {0, 1, 2, 3};
-+static const char * const gxbb_vapb_parent_names[] = {
-+	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
-+};
-+
-+static struct clk_mux gxbb_vapb_0_sel = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.mask = 0x3,
-+	.shift = 9,
-+	.lock = &clk_lock,
-+	.table = mux_table_vapb,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vapb_0_sel",
-+		.ops = &clk_mux_ops,
-+		/*
-+		 * bits 9:10 selects from 4 possible parents:
-+		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
-+		 */
-+		.parent_names = gxbb_vapb_parent_names,
-+		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
-+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_divider gxbb_vapb_0_div = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.shift = 0,
-+	.width = 7,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vapb_0_div",
-+		.ops = &clk_divider_ops,
-+		.parent_names = (const char *[]){ "vapb_0_sel" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_gate gxbb_vapb_0 = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.bit_idx = 8,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data) {
-+		.name = "vapb_0",
-+		.ops = &clk_gate_ops,
-+		.parent_names = (const char *[]){ "vapb_0_div" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_mux gxbb_vapb_1_sel = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.mask = 0x3,
-+	.shift = 25,
-+	.lock = &clk_lock,
-+	.table = mux_table_vapb,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vapb_1_sel",
-+		.ops = &clk_mux_ops,
-+		/*
-+		 * bits 25:26 selects from 4 possible parents:
-+		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
-+		 */
-+		.parent_names = gxbb_vapb_parent_names,
-+		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
-+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_divider gxbb_vapb_1_div = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.shift = 16,
-+	.width = 7,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vapb_1_div",
-+		.ops = &clk_divider_ops,
-+		.parent_names = (const char *[]){ "vapb_1_sel" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_gate gxbb_vapb_1 = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.bit_idx = 24,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data) {
-+		.name = "vapb_1",
-+		.ops = &clk_gate_ops,
-+		.parent_names = (const char *[]){ "vapb_1_div" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_mux gxbb_vapb_sel = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.mask = 1,
-+	.shift = 31,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data){
-+		.name = "vapb_sel",
-+		.ops = &clk_mux_ops,
-+		/*
-+		 * bit 31 selects from 2 possible parents:
-+		 * vapb_0 or vapb_1
-+		 */
-+		.parent_names = (const char *[]){ "vapb_0", "vapb_1" },
-+		.num_parents = 2,
-+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
-+static struct clk_gate gxbb_vapb = {
-+	.reg = (void *)HHI_VAPBCLK_CNTL,
-+	.bit_idx = 30,
-+	.lock = &clk_lock,
-+	.hw.init = &(struct clk_init_data) {
-+		.name = "vapb",
-+		.ops = &clk_gate_ops,
-+		.parent_names = (const char *[]){ "vapb_sel" },
-+		.num_parents = 1,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-+	},
-+};
-+
- /* Everything Else (EE) domain gates */
- static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
- static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
-@@ -1349,6 +1596,21 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
- 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
- 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
- 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
-+		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
-+		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
-+		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
-+		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
-+		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
-+		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
-+		[CLKID_VPU]		    = &gxbb_vpu.hw,
-+		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
-+		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
-+		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
-+		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
-+		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
-+		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
-+		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
-+		[CLKID_VAPB]		    = &gxbb_vapb.hw,
- 		[NR_CLKS]		    = NULL,
- 	},
- 	.num = NR_CLKS,
-@@ -1481,6 +1743,21 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
- 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
- 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
- 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
-+		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
-+		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
-+		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
-+		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
-+		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
-+		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
-+		[CLKID_VPU]		    = &gxbb_vpu.hw,
-+		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
-+		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
-+		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
-+		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
-+		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
-+		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
-+		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
-+		[CLKID_VAPB]		    = &gxbb_vapb.hw,
- 		[NR_CLKS]		    = NULL,
- 	},
- 	.num = NR_CLKS,
-@@ -1600,6 +1877,11 @@ static struct clk_gate *const gxbb_clk_gates[] = {
- 	&gxbb_sd_emmc_a_clk0,
- 	&gxbb_sd_emmc_b_clk0,
- 	&gxbb_sd_emmc_c_clk0,
-+	&gxbb_vpu_0,
-+	&gxbb_vpu_1,
-+	&gxbb_vapb_0,
-+	&gxbb_vapb_1,
-+	&gxbb_vapb,
- };
- 
- static struct clk_mux *const gxbb_clk_muxes[] = {
-@@ -1615,6 +1897,12 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
- 	&gxbb_sd_emmc_a_clk0_sel,
- 	&gxbb_sd_emmc_b_clk0_sel,
- 	&gxbb_sd_emmc_c_clk0_sel,
-+	&gxbb_vpu_0_sel,
-+	&gxbb_vpu_1_sel,
-+	&gxbb_vpu,
-+	&gxbb_vapb_0_sel,
-+	&gxbb_vapb_1_sel,
-+	&gxbb_vapb_sel,
- };
- 
- static struct clk_divider *const gxbb_clk_dividers[] = {
-@@ -1627,6 +1915,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
- 	&gxbb_sd_emmc_a_clk0_div,
- 	&gxbb_sd_emmc_b_clk0_div,
- 	&gxbb_sd_emmc_c_clk0_div,
-+	&gxbb_vpu_0_div,
-+	&gxbb_vpu_1_div,
-+	&gxbb_vapb_0_div,
-+	&gxbb_vapb_1_div,
- };
- 
- static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0016-drm-meson-dw_hdmi-Add-support-for-an-optional-extern.patch

@@ -1,56 +0,0 @@
-From fc742b3d9f1b79f9e3e695f0e4bfc6a35c7ed7e3 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 16 Oct 2017 15:35:00 +0200
-Subject: [PATCH 16/39] drm/meson: dw_hdmi: Add support for an optional
- external 5V regulator
-
-On reference boards and derivatives, the HDMI Logic is powered by an external
-5V regulator.
-This regulator was set by the Vendor U-Boot, add optional support for it.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/meson/meson_dw_hdmi.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-index cef4144..17de3af 100644
---- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
-+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-@@ -23,6 +23,7 @@
- #include <linux/of_graph.h>
- #include <linux/reset.h>
- #include <linux/clk.h>
-+#include <linux/regulator/consumer.h>
- 
- #include <drm/drmP.h>
- #include <drm/drm_edid.h>
-@@ -137,6 +138,7 @@ struct meson_dw_hdmi {
- 	struct reset_control *hdmitx_phy;
- 	struct clk *hdmi_pclk;
- 	struct clk *venci_clk;
-+	struct regulator *hdmi_supply;
- 	u32 irq_stat;
- };
- #define encoder_to_meson_dw_hdmi(x) \
-@@ -751,6 +753,17 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
- 	dw_plat_data = &meson_dw_hdmi->dw_plat_data;
- 	encoder = &meson_dw_hdmi->encoder;
- 
-+	meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi");
-+	if (IS_ERR(meson_dw_hdmi->hdmi_supply)) {
-+		if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER)
-+			return -EPROBE_DEFER;
-+		meson_dw_hdmi->hdmi_supply = NULL;
-+	} else {
-+		ret = regulator_enable(meson_dw_hdmi->hdmi_supply);
-+		if (ret)
-+			return ret;
-+	}
-+
- 	meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev,
- 						"hdmitx_apb");
- 	if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) {
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0017-drm-meson-Add-missing-VPU-init.patch

@@ -1,58 +0,0 @@
-From 253dbcb48f94e172873878262d19338bcc9aa108 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 16 Oct 2017 15:34:21 +0200
-Subject: [PATCH 17/39] drm/meson: Add missing VPU init
-
-The VPU init misses these configurations values.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/meson/meson_drv.c       | 9 +++++++++
- drivers/gpu/drm/meson/meson_registers.h | 4 ++++
- 2 files changed, 13 insertions(+)
-
-diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
-index 7742c7d..19a0d8d 100644
---- a/drivers/gpu/drm/meson/meson_drv.c
-+++ b/drivers/gpu/drm/meson/meson_drv.c
-@@ -150,6 +150,14 @@ static struct regmap_config meson_regmap_config = {
- 	.max_register   = 0x1000,
- };
- 
-+static void meson_vpu_init(struct meson_drm *priv)
-+{
-+	writel_relaxed(0x210000, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
-+	writel_relaxed(0x10000, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
-+	writel_relaxed(0x900000, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
-+	writel_relaxed(0x20000, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
-+}
-+
- static int meson_drv_bind_master(struct device *dev, bool has_components)
- {
- 	struct platform_device *pdev = to_platform_device(dev);
-@@ -221,6 +229,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
- 
- 	/* Hardware Initialization */
- 
-+	meson_vpu_init(priv);
- 	meson_venc_init(priv);
- 	meson_vpp_init(priv);
- 	meson_viu_init(priv);
-diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
-index 2847381..bca8714 100644
---- a/drivers/gpu/drm/meson/meson_registers.h
-+++ b/drivers/gpu/drm/meson/meson_registers.h
-@@ -1363,6 +1363,10 @@
- #define VPU_PROT3_STAT_1 0x277a
- #define VPU_PROT3_STAT_2 0x277b
- #define VPU_PROT3_REQ_ONOFF 0x277c
-+#define VPU_RDARB_MODE_L1C1 0x2790
-+#define VPU_RDARB_MODE_L1C2 0x2799
-+#define VPU_RDARB_MODE_L2C1 0x279d
-+#define VPU_WRARB_MODE_L2C1 0x27a2
- 
- /* osd super scale */
- #define OSDSR_HV_SIZEIN 0x3130
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0018-reset-meson-add-level-reset-support-for-GX-SoC-famil.patch

@@ -1,132 +0,0 @@
-From 0689a4eaecae2831fe2cb614e102bb4ef43484a4 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Fri, 13 Oct 2017 14:05:01 +0200
-Subject: [PATCH 18/39] reset: meson: add level reset support for GX SoC family
-
-The Amlogic GX SoC family embeds alternate registers to drive the reset
-levels next to the pulse registers.
-
-This patch adds support for level reset handling on the GX family only.
-
-The Meson8 family has an alternate way to handle level reset.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/reset/reset-meson.c | 62 ++++++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 58 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
-index a8b915e..f3b9d69 100644
---- a/drivers/reset/reset-meson.c
-+++ b/drivers/reset/reset-meson.c
-@@ -62,13 +62,16 @@
- #include <linux/reset-controller.h>
- #include <linux/slab.h>
- #include <linux/types.h>
-+#include <linux/of_device.h>
- 
- #define REG_COUNT	8
- #define BITS_PER_REG	32
-+#define LEVEL_OFFSET	0x7c
- 
- struct meson_reset {
- 	void __iomem *reg_base;
- 	struct reset_controller_dev rcdev;
-+	spinlock_t lock;
- };
- 
- static int meson_reset_reset(struct reset_controller_dev *rcdev,
-@@ -88,18 +91,63 @@ static int meson_reset_reset(struct reset_controller_dev *rcdev,
- 	return 0;
- }
- 
--static const struct reset_control_ops meson_reset_ops = {
-+static int meson_reset_level(struct reset_controller_dev *rcdev,
-+			    unsigned long id, bool assert)
-+{
-+	struct meson_reset *data =
-+		container_of(rcdev, struct meson_reset, rcdev);
-+	unsigned int bank = id / BITS_PER_REG;
-+	unsigned int offset = id % BITS_PER_REG;
-+	void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
-+	unsigned long flags;
-+	u32 reg;
-+
-+	spin_lock_irqsave(&data->lock, flags);
-+
-+	reg = readl(reg_addr);
-+	if (assert)
-+		writel(reg & ~BIT(offset), reg_addr);
-+	else
-+		writel(reg | BIT(offset), reg_addr);
-+
-+	spin_unlock_irqrestore(&data->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int meson_reset_assert(struct reset_controller_dev *rcdev,
-+			      unsigned long id)
-+{
-+	return meson_reset_level(rcdev, id, true);
-+}
-+
-+static int meson_reset_deassert(struct reset_controller_dev *rcdev,
-+				unsigned long id)
-+{
-+	return meson_reset_level(rcdev, id, false);
-+}
-+
-+static const struct reset_control_ops meson_reset_meson8_ops = {
- 	.reset		= meson_reset_reset,
- };
- 
-+static const struct reset_control_ops meson_reset_gx_ops = {
-+	.reset		= meson_reset_reset,
-+	.assert		= meson_reset_assert,
-+	.deassert	= meson_reset_deassert,
-+};
-+
- static const struct of_device_id meson_reset_dt_ids[] = {
--	 { .compatible = "amlogic,meson8b-reset", },
--	 { .compatible = "amlogic,meson-gxbb-reset", },
-+	 { .compatible = "amlogic,meson8b-reset",
-+	   .data = &meson_reset_meson8_ops, },
-+	 { .compatible = "amlogic,meson-gxbb-reset",
-+	   .data = &meson_reset_gx_ops, },
- 	 { /* sentinel */ },
- };
- 
- static int meson_reset_probe(struct platform_device *pdev)
- {
-+	const struct reset_control_ops *ops;
- 	struct meson_reset *data;
- 	struct resource *res;
- 
-@@ -107,6 +155,10 @@ static int meson_reset_probe(struct platform_device *pdev)
- 	if (!data)
- 		return -ENOMEM;
- 
-+	ops = of_device_get_match_data(&pdev->dev);
-+	if (!ops)
-+		return -EINVAL;
-+
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	data->reg_base = devm_ioremap_resource(&pdev->dev, res);
- 	if (IS_ERR(data->reg_base))
-@@ -114,9 +166,11 @@ static int meson_reset_probe(struct platform_device *pdev)
- 
- 	platform_set_drvdata(pdev, data);
- 
-+	spin_lock_init(&data->lock);
-+
- 	data->rcdev.owner = THIS_MODULE;
- 	data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
--	data->rcdev.ops = &meson_reset_ops;
-+	data->rcdev.ops = ops;
- 	data->rcdev.of_node = pdev->dev.of_node;
- 
- 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0019-soc-amlogic-add-Meson-GX-VPU-Domains-driver.patch

@@ -1,286 +0,0 @@
-From 58d5e73046ca5c28eb835c1a98f936193de5d4d0 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Fri, 13 Oct 2017 17:05:00 +0200
-Subject: [PATCH 19/39] soc: amlogic: add Meson GX VPU Domains driver
-
-The Video Processing Unit needs a specific Power Domain powering scheme
-this driver handles this as a PM Power Domain driver.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/soc/amlogic/Kconfig             |  10 ++
- drivers/soc/amlogic/Makefile            |   1 +
- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 234 ++++++++++++++++++++++++++++++++
- 3 files changed, 245 insertions(+)
- create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c
-
-diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
-index 22acf06..c2c0513 100644
---- a/drivers/soc/amlogic/Kconfig
-+++ b/drivers/soc/amlogic/Kconfig
-@@ -8,5 +8,15 @@ config MESON_GX_SOCINFO
- 	help
- 	  Say yes to support decoding of Amlogic Meson GX SoC family
- 	  information about the type, package and version.
-+ 
-+config MESON_GX_PM_DOMAINS
-+	bool "Amlogic Meson GX Power Domains driver"
-+	depends on ARCH_MESON || COMPILE_TEST
-+	default ARCH_MESON
-+	select PM_GENERIC_DOMAINS
-+	select PM_GENERIC_DOMAINS_OF
-+	help
-+	  Say yes to expose Amlogic Meson GX Power Domains as
-+	  Generic Power Domains.
- 
- endmenu
-diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
-index 3e85fc4..3174e93 100644
---- a/drivers/soc/amlogic/Makefile
-+++ b/drivers/soc/amlogic/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
-+obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
-diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
-new file mode 100644
-index 0000000..bf5190b
---- /dev/null
-+++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
-@@ -0,0 +1,234 @@
-+/*
-+ * Copyright (c) 2017 BayLibre, SAS
-+ * Author: Neil Armstrong <narmstrong@baylibre.com>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <linux/of_address.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_domain.h>
-+#include <linux/bitfield.h>
-+#include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/reset.h>
-+#include <linux/clk.h>
-+
-+/* AO Offsets */
-+
-+#define AO_RTI_GEN_PWR_SLEEP0		(0x3a << 2)
-+
-+#define GEN_PWR_VPU_HDMI		BIT(8)
-+#define GEN_PWR_VPU_HDMI_ISO		BIT(9)
-+
-+/* HHI Offsets */
-+
-+#define HHI_MEM_PD_REG0			(0x40 << 2)
-+#define HHI_VPU_MEM_PD_REG0		(0x41 << 2)
-+#define HHI_VPU_MEM_PD_REG1		(0x42 << 2)
-+
-+struct meson_gx_pwrc_vpu {
-+	struct generic_pm_domain genpd;
-+	struct regmap *regmap_ao;
-+	struct regmap *regmap_hhi;
-+	struct reset_control *rstc;
-+	struct clk *vpu_clk;
-+	struct clk *vapb_clk;
-+	bool powered;
-+};
-+
-+static inline
-+struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
-+{
-+	return container_of(d, struct meson_gx_pwrc_vpu, genpd);
-+}
-+
-+static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
-+{
-+	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
-+	int i;
-+
-+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
-+			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
-+	udelay(20);
-+
-+	/* Power Down Memories */
-+	for (i = 0; i < 32; i += 2) {
-+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
-+				   0x2 << i, 0x3 << i);
-+		udelay(5);
-+	}
-+	for (i = 0; i < 32; i += 2) {
-+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
-+				   0x2 << i, 0x3 << i);
-+		udelay(5);
-+	}
-+	for (i = 8; i < 16; i++) {
-+		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
-+				   BIT(i), BIT(i));
-+		udelay(5);
-+	}
-+	udelay(20);
-+
-+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
-+			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
-+
-+	msleep(20);
-+
-+	clk_disable_unprepare(pd->vpu_clk);
-+	clk_disable_unprepare(pd->vapb_clk);
-+
-+	pd->powered = false;
-+
-+	return 0;
-+}
-+
-+static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
-+{
-+	int ret;
-+
-+	ret = clk_prepare_enable(pd->vpu_clk);
-+	if (ret)
-+		return ret;
-+
-+	return clk_prepare_enable(pd->vapb_clk);
-+}
-+
-+static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
-+{
-+	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
-+	int ret;
-+	int i;
-+
-+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
-+			   GEN_PWR_VPU_HDMI, 0);
-+	udelay(20);
-+
-+	/* Power Up Memories */
-+	for (i = 0; i < 32; i += 2) {
-+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
-+				   0x2 << i, 0);
-+		udelay(5);
-+	}
-+
-+	for (i = 0; i < 32; i += 2) {
-+		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
-+				   0x2 << i, 0);
-+		udelay(5);
-+	}
-+
-+	for (i = 8; i < 16; i++) {
-+		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
-+				   BIT(i), 0);
-+		udelay(5);
-+	}
-+	udelay(20);
-+
-+	ret = reset_control_assert(pd->rstc);
-+	if (ret)
-+		return ret;
-+
-+	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
-+			   GEN_PWR_VPU_HDMI_ISO, 0);
-+
-+	ret = reset_control_deassert(pd->rstc);
-+	if (ret)
-+		return ret;
-+
-+	ret = meson_gx_pwrc_vpu_setup_clk(pd);
-+	if (ret)
-+		return ret;
-+
-+	pd->powered = true;
-+
-+	return 0;
-+}
-+
-+static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
-+{
-+	u32 reg;
-+
-+	regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, &reg);
-+
-+	return (reg & GEN_PWR_VPU_HDMI);
-+}
-+
-+static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
-+	.genpd = {
-+		.name = "vpu_hdmi",
-+		.power_off = meson_gx_pwrc_vpu_power_off,
-+		.power_on = meson_gx_pwrc_vpu_power_on,
-+	},
-+};
-+
-+static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
-+{
-+	struct regmap *regmap_ao, *regmap_hhi;
-+	struct reset_control *rstc;
-+	struct clk *vpu_clk;
-+	struct clk *vapb_clk;
-+
-+	regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
-+	if (IS_ERR(regmap_ao)) {
-+		dev_err(&pdev->dev, "failed to get regmap\n");
-+		return PTR_ERR(regmap_ao);
-+	}
-+
-+	regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
-+						     "amlogic,hhi-sysctrl");
-+	if (IS_ERR(regmap_hhi)) {
-+		dev_err(&pdev->dev, "failed to get HHI regmap\n");
-+		return PTR_ERR(regmap_hhi);
-+	}
-+
-+	rstc = devm_reset_control_array_get(&pdev->dev, false, false);
-+	if (IS_ERR(rstc)) {
-+		dev_err(&pdev->dev, "failed to get reset lines\n");
-+		return PTR_ERR(rstc);
-+	}
-+
-+	vpu_clk = devm_clk_get(&pdev->dev, "vpu");
-+	if (IS_ERR(vpu_clk)) {
-+		dev_err(&pdev->dev, "vpu clock request failed\n");
-+		return PTR_ERR(vpu_clk);
-+	}
-+
-+	vapb_clk = devm_clk_get(&pdev->dev, "vapb");
-+	if (IS_ERR(vapb_clk)) {
-+		dev_err(&pdev->dev, "vapb clock request failed\n");
-+		return PTR_ERR(vapb_clk);
-+	}
-+
-+	vpu_hdmi_pd.regmap_ao = regmap_ao;
-+	vpu_hdmi_pd.regmap_hhi = regmap_hhi;
-+	vpu_hdmi_pd.rstc = rstc;
-+	vpu_hdmi_pd.vpu_clk = vpu_clk;
-+	vpu_hdmi_pd.vapb_clk = vapb_clk;
-+
-+	pm_genpd_init(&vpu_hdmi_pd.genpd, &simple_qos_governor,
-+		      meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd));
-+
-+	return of_genpd_add_provider_simple(pdev->dev.of_node,
-+					    &vpu_hdmi_pd.genpd);
-+}
-+
-+static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
-+{
-+	if (vpu_hdmi_pd.powered)
-+		meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
-+}
-+
-+static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
-+	{ .compatible = "amlogic,meson-gx-pwrc-vpu" },
-+	{ /* sentinel */ }
-+};
-+
-+static struct platform_driver meson_gx_pwrc_vpu_driver = {
-+	.probe	= meson_gx_pwrc_vpu_probe,
-+	.shutdown = meson_gx_pwrc_vpu_shutdown,
-+	.driver = {
-+		.name		= "meson_gx_pwrc_vpu",
-+		.of_match_table	= meson_gx_pwrc_vpu_match_table,
-+	},
-+};
-+builtin_platform_driver(meson_gx_pwrc_vpu_driver);
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0020-soc-amlogic-meson-gx-pwrc-vpu-fix-power-off-when-pow.patch

@@ -1,105 +0,0 @@
-From a2ae223bac1ad40a5bd7ee124b3af735ff445eb9 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Fri, 3 Nov 2017 16:43:24 +0100
-Subject: [PATCH 20/39] soc: amlogic: meson-gx-pwrc-vpu: fix power-off when
- powered by bootloader
-
-In the case the VPU power domain has been powered on by the bootloader
-and no driver are attached to this power domain, the genpd will power it
-off after a certain amount of time, but the clocks hasn't been enabled
-by the kernel itself and the power-off will trigger some faults.
-This patch enable the clocks to have a coherent state for an eventual
-poweroff and switches to the pm_domain_always_on_gov governor.
-
-Fixes: 75fcb5ca4b46 ("soc: amlogic: add Meson GX VPU Domains driver")
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
-Tested-by: Kevin Hilman <khilman@baylibre.com>
----
- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 29 +++++++++++++++++++----------
- 1 file changed, 19 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
-index bf5190b..2bdeebc 100644
---- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
-+++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
-@@ -34,7 +34,6 @@ struct meson_gx_pwrc_vpu {
- 	struct reset_control *rstc;
- 	struct clk *vpu_clk;
- 	struct clk *vapb_clk;
--	bool powered;
- };
- 
- static inline
-@@ -78,8 +77,6 @@ static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
- 	clk_disable_unprepare(pd->vpu_clk);
- 	clk_disable_unprepare(pd->vapb_clk);
- 
--	pd->powered = false;
--
- 	return 0;
- }
- 
-@@ -91,7 +88,11 @@ static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
- 	if (ret)
- 		return ret;
- 
--	return clk_prepare_enable(pd->vapb_clk);
-+	ret = clk_prepare_enable(pd->vapb_clk);
-+	if (ret)
-+		clk_disable_unprepare(pd->vpu_clk);
-+
-+	return ret;
- }
- 
- static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
-@@ -139,8 +140,6 @@ static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
- 	if (ret)
- 		return ret;
- 
--	pd->powered = true;
--
- 	return 0;
- }
- 
-@@ -167,6 +166,8 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
- 	struct reset_control *rstc;
- 	struct clk *vpu_clk;
- 	struct clk *vapb_clk;
-+	bool powered_off;
-+	int ret;
- 
- 	regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
- 	if (IS_ERR(regmap_ao)) {
-@@ -205,8 +206,17 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
- 	vpu_hdmi_pd.vpu_clk = vpu_clk;
- 	vpu_hdmi_pd.vapb_clk = vapb_clk;
- 
--	pm_genpd_init(&vpu_hdmi_pd.genpd, &simple_qos_governor,
--		      meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd));
-+	powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
-+
-+	/* If already powered, sync the clock states */
-+	if (!powered_off) {
-+		ret = meson_gx_pwrc_vpu_setup_clk(&vpu_hdmi_pd);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	pm_genpd_init(&vpu_hdmi_pd.genpd, &pm_domain_always_on_gov,
-+		      powered_off);
- 
- 	return of_genpd_add_provider_simple(pdev->dev.of_node,
- 					    &vpu_hdmi_pd.genpd);
-@@ -214,8 +224,7 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
- 
- static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
- {
--	if (vpu_hdmi_pd.powered)
--		meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
-+	meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
- }
- 
- static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0021-ASoC-meson-add-meson-audio-core-driver.patch

@@ -1,312 +0,0 @@
-From f9b447452943415a12055c0fca279281cd28d923 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Thu, 30 Mar 2017 11:49:55 +0200
-Subject: [PATCH 21/39] ASoC: meson: add meson audio core driver
-
-This patch adds support for the audio core driver for the Amlogic Meson SoC
-family. The purpose of this driver is to properly reset the audio block and
-provide register access for the different devices scattered in this address
-space. This includes output and input DMAs, pcm, i2s and spdif dai, card
-level routing, internal codec for the gxl variant
-
-For more information, please refer to the section 5 of the public datasheet
-of the S905 (gxbb). This datasheet is available here: [0].
-
-[0]: http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- sound/soc/Kconfig            |   1 +
- sound/soc/Makefile           |   1 +
- sound/soc/meson/Kconfig      |   9 ++
- sound/soc/meson/Makefile     |   3 +
- sound/soc/meson/audio-core.c | 190 +++++++++++++++++++++++++++++++++++++++++++
- sound/soc/meson/audio-core.h |  28 +++++++
- 6 files changed, 232 insertions(+)
- create mode 100644 sound/soc/meson/Kconfig
- create mode 100644 sound/soc/meson/Makefile
- create mode 100644 sound/soc/meson/audio-core.c
- create mode 100644 sound/soc/meson/audio-core.h
-
-diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
-index c0abad2..7db316f 100644
---- a/sound/soc/Kconfig
-+++ b/sound/soc/Kconfig
-@@ -55,6 +55,7 @@ source "sound/soc/kirkwood/Kconfig"
- source "sound/soc/img/Kconfig"
- source "sound/soc/intel/Kconfig"
- source "sound/soc/mediatek/Kconfig"
-+source "sound/soc/meson/Kconfig"
- source "sound/soc/mxs/Kconfig"
- source "sound/soc/pxa/Kconfig"
- source "sound/soc/qcom/Kconfig"
-diff --git a/sound/soc/Makefile b/sound/soc/Makefile
-index bf8c1e2..d4c0a51 100644
---- a/sound/soc/Makefile
-+++ b/sound/soc/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_SND_SOC)	+= jz4740/
- obj-$(CONFIG_SND_SOC)	+= img/
- obj-$(CONFIG_SND_SOC)	+= intel/
- obj-$(CONFIG_SND_SOC)	+= mediatek/
-+obj-$(CONFIG_SND_SOC)	+= meson/
- obj-$(CONFIG_SND_SOC)	+= mxs/
- obj-$(CONFIG_SND_SOC)	+= nuc900/
- obj-$(CONFIG_SND_SOC)	+= omap/
-diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
-new file mode 100644
-index 0000000..216c850
---- /dev/null
-+++ b/sound/soc/meson/Kconfig
-@@ -0,0 +1,9 @@
-+menuconfig SND_SOC_MESON
-+	tristate "ASoC support for Amlogic Meson SoCs"
-+	depends on ARCH_MESON || COMPILE_TEST
-+	select MFD_CORE
-+	select REGMAP_MMIO
-+	help
-+	  Say Y or M if you want to add support for codecs attached to
-+	  the Amlogic Meson SoCs Audio interfaces. You will also need to
-+	  select the audio interfaces to support below.
-diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
-new file mode 100644
-index 0000000..22028ab
---- /dev/null
-+++ b/sound/soc/meson/Makefile
-@@ -0,0 +1,3 @@
-+snd-soc-meson-audio-core-objs	 := audio-core.o
-+
-+obj-$(CONFIG_SND_SOC_MESON)		+= snd-soc-meson-audio-core.o
-diff --git a/sound/soc/meson/audio-core.c b/sound/soc/meson/audio-core.c
-new file mode 100644
-index 0000000..99993ec
---- /dev/null
-+++ b/sound/soc/meson/audio-core.c
-@@ -0,0 +1,190 @@
-+/*
-+ * Copyright (C) 2017 BayLibre, SAS
-+ * Author: Jerome Brunet <jbrunet@baylibre.com>
-+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/mfd/core.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+
-+#include "audio-core.h"
-+
-+#define DRV_NAME "meson-audio-core"
-+
-+static const char * const acore_clock_names[] = { "aiu_top",
-+						  "aiu_glue",
-+						  "audin" };
-+
-+static int meson_acore_init_clocks(struct device *dev)
-+{
-+	struct clk *clock;
-+	int i, ret;
-+
-+	for (i = 0; i < ARRAY_SIZE(acore_clock_names); i++) {
-+		clock = devm_clk_get(dev, acore_clock_names[i]);
-+		if (IS_ERR(clock)) {
-+			if (PTR_ERR(clock) != -EPROBE_DEFER)
-+				dev_err(dev, "Failed to get %s clock\n",
-+					acore_clock_names[i]);
-+			return PTR_ERR(clock);
-+		}
-+
-+		ret = clk_prepare_enable(clock);
-+		if (ret) {
-+			dev_err(dev, "Failed to enable %s clock\n",
-+				acore_clock_names[i]);
-+			return ret;
-+		}
-+
-+		ret = devm_add_action_or_reset(dev,
-+				(void(*)(void *))clk_disable_unprepare,
-+				clock);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static const char * const acore_reset_names[] = { "aiu",
-+						  "audin" };
-+
-+static int meson_acore_init_resets(struct device *dev)
-+{
-+	struct reset_control *reset;
-+	int i, ret;
-+
-+	for (i = 0; i < ARRAY_SIZE(acore_reset_names); i++) {
-+		reset = devm_reset_control_get_exclusive(dev,
-+							 acore_reset_names[i]);
-+		if (IS_ERR(reset)) {
-+			if (PTR_ERR(reset) != -EPROBE_DEFER)
-+				dev_err(dev, "Failed to get %s reset\n",
-+					acore_reset_names[i]);
-+			return PTR_ERR(reset);
-+		}
-+
-+		ret = reset_control_reset(reset);
-+		if (ret) {
-+			dev_err(dev, "Failed to pulse %s reset\n",
-+				acore_reset_names[i]);
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct regmap_config meson_acore_regmap_config = {
-+	.reg_bits       = 32,
-+	.val_bits       = 32,
-+	.reg_stride     = 4,
-+};
-+
-+static const struct mfd_cell meson_acore_devs[] = {
-+	{
-+		.name = "meson-i2s-dai",
-+		.of_compatible = "amlogic,meson-i2s-dai",
-+	},
-+	{
-+		.name = "meson-spdif-dai",
-+		.of_compatible = "amlogic,meson-spdif-dai",
-+	},
-+	{
-+		.name = "meson-aiu-i2s-dma",
-+		.of_compatible = "amlogic,meson-aiu-i2s-dma",
-+	},
-+	{
-+		.name = "meson-aiu-spdif-dma",
-+		.of_compatible = "amlogic,meson-aiu-spdif-dma",
-+	},
-+};
-+
-+static int meson_acore_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct meson_audio_core_data *data;
-+	struct resource *res;
-+	void __iomem *regs;
-+	int ret;
-+
-+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+	if (!data)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, data);
-+
-+	ret = meson_acore_init_clocks(dev);
-+	if (ret)
-+		return ret;
-+
-+	ret = meson_acore_init_resets(dev);
-+	if (ret)
-+		return ret;
-+
-+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aiu");
-+	regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(regs))
-+		return PTR_ERR(regs);
-+
-+	data->aiu = devm_regmap_init_mmio(dev, regs,
-+					  &meson_acore_regmap_config);
-+	if (IS_ERR(data->aiu)) {
-+		dev_err(dev, "Couldn't create the AIU regmap\n");
-+		return PTR_ERR(data->aiu);
-+	}
-+
-+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audin");
-+	regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(regs))
-+		return PTR_ERR(regs);
-+
-+	data->audin = devm_regmap_init_mmio(dev, regs,
-+					    &meson_acore_regmap_config);
-+	if (IS_ERR(data->audin)) {
-+		dev_err(dev, "Couldn't create the AUDIN regmap\n");
-+		return PTR_ERR(data->audin);
-+	}
-+
-+	return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, meson_acore_devs,
-+				    ARRAY_SIZE(meson_acore_devs), NULL, 0,
-+				    NULL);
-+}
-+
-+static const struct of_device_id meson_acore_of_match[] = {
-+	{ .compatible = "amlogic,meson-audio-core", },
-+	{ .compatible = "amlogic,meson-gxbb-audio-core", },
-+	{ .compatible = "amlogic,meson-gxl-audio-core", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, meson_acore_of_match);
-+
-+static struct platform_driver meson_acore_pdrv = {
-+	.probe = meson_acore_probe,
-+	.driver = {
-+		.name = DRV_NAME,
-+		.of_match_table = meson_acore_of_match,
-+	},
-+};
-+module_platform_driver(meson_acore_pdrv);
-+
-+MODULE_DESCRIPTION("Meson Audio Core Driver");
-+MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
-+MODULE_LICENSE("GPL v2");
-diff --git a/sound/soc/meson/audio-core.h b/sound/soc/meson/audio-core.h
-new file mode 100644
-index 0000000..6e7a24c
---- /dev/null
-+++ b/sound/soc/meson/audio-core.h
-@@ -0,0 +1,28 @@
-+/*
-+ * Copyright (C) 2017 BayLibre, SAS
-+ * Author: Jerome Brunet <jbrunet@baylibre.com>
-+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _MESON_AUDIO_CORE_H_
-+#define _MESON_AUDIO_CORE_H_
-+
-+struct meson_audio_core_data {
-+	struct regmap *aiu;
-+	struct regmap *audin;
-+};
-+
-+#endif /* _MESON_AUDIO_CORE_H_ */
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0022-ASoC-meson-add-register-definitions.patch

@@ -1,361 +0,0 @@
-From 71e89b9513f114d45fd43233039a73f678702815 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Thu, 30 Mar 2017 12:00:10 +0200
-Subject: [PATCH 22/39] ASoC: meson: add register definitions
-
-Add the register definition for the AIU and AUDIN blocks
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- sound/soc/meson/aiu-regs.h   | 182 +++++++++++++++++++++++++++++++++++++++++++
- sound/soc/meson/audin-regs.h | 148 +++++++++++++++++++++++++++++++++++
- 2 files changed, 330 insertions(+)
- create mode 100644 sound/soc/meson/aiu-regs.h
- create mode 100644 sound/soc/meson/audin-regs.h
-
-diff --git a/sound/soc/meson/aiu-regs.h b/sound/soc/meson/aiu-regs.h
-new file mode 100644
-index 0000000..67391e6
---- /dev/null
-+++ b/sound/soc/meson/aiu-regs.h
-@@ -0,0 +1,182 @@
-+/*
-+ * Copyright (C) 2017 BayLibre, SAS
-+ * Author: Jerome Brunet <jbrunet@baylibre.com>
-+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _AIU_REGS_H_
-+#define _AIU_REGS_H_
-+
-+#define AIU_958_BPF			0x000
-+#define AIU_958_BRST			0x004
-+#define AIU_958_LENGTH			0x008
-+#define AIU_958_PADDSIZE		0x00C
-+#define AIU_958_MISC			0x010
-+#define AIU_958_FORCE_LEFT		0x014	/* Unknown */
-+#define AIU_958_DISCARD_NUM		0x018
-+#define AIU_958_DCU_FF_CTRL		0x01C
-+#define AIU_958_CHSTAT_L0		0x020
-+#define AIU_958_CHSTAT_L1		0x024
-+#define AIU_958_CTRL			0x028
-+#define AIU_958_RPT			0x02C
-+#define AIU_I2S_MUTE_SWAP		0x030
-+#define AIU_I2S_SOURCE_DESC		0x034
-+#define AIU_I2S_MED_CTRL		0x038
-+#define AIU_I2S_MED_THRESH		0x03C
-+#define AIU_I2S_DAC_CFG			0x040
-+#define AIU_I2S_SYNC			0x044	/* Unknown */
-+#define AIU_I2S_MISC			0x048
-+#define AIU_I2S_OUT_CFG			0x04C
-+#define AIU_I2S_FF_CTRL			0x050	/* Unknown */
-+#define AIU_RST_SOFT			0x054
-+#define AIU_CLK_CTRL			0x058
-+#define AIU_MIX_ADCCFG			0x05C
-+#define AIU_MIX_CTRL			0x060
-+#define AIU_CLK_CTRL_MORE		0x064
-+#define AIU_958_POP			0x068
-+#define AIU_MIX_GAIN			0x06C
-+#define AIU_958_SYNWORD1		0x070
-+#define AIU_958_SYNWORD2		0x074
-+#define AIU_958_SYNWORD3		0x078
-+#define AIU_958_SYNWORD1_MASK		0x07C
-+#define AIU_958_SYNWORD2_MASK		0x080
-+#define AIU_958_SYNWORD3_MASK		0x084
-+#define AIU_958_FFRDOUT_THD		0x088
-+#define AIU_958_LENGTH_PER_PAUSE	0x08C
-+#define AIU_958_PAUSE_NUM		0x090
-+#define AIU_958_PAUSE_PAYLOAD		0x094
-+#define AIU_958_AUTO_PAUSE		0x098
-+#define AIU_958_PAUSE_PD_LENGTH		0x09C
-+#define AIU_CODEC_DAC_LRCLK_CTRL	0x0A0
-+#define AIU_CODEC_ADC_LRCLK_CTRL	0x0A4
-+#define AIU_HDMI_CLK_DATA_CTRL		0x0A8
-+#define AIU_CODEC_CLK_DATA_CTRL		0x0AC
-+#define AIU_ACODEC_CTRL			0x0B0
-+#define AIU_958_CHSTAT_R0		0x0C0
-+#define AIU_958_CHSTAT_R1		0x0C4
-+#define AIU_958_VALID_CTRL		0x0C8
-+#define AIU_AUDIO_AMP_REG0		0x0F0	/* Unknown */
-+#define AIU_AUDIO_AMP_REG1		0x0F4	/* Unknown */
-+#define AIU_AUDIO_AMP_REG2		0x0F8	/* Unknown */
-+#define AIU_AUDIO_AMP_REG3		0x0FC	/* Unknown */
-+#define AIU_AIFIFO2_CTRL		0x100
-+#define AIU_AIFIFO2_STATUS		0x104
-+#define AIU_AIFIFO2_GBIT		0x108
-+#define AIU_AIFIFO2_CLB			0x10C
-+#define AIU_CRC_CTRL			0x110
-+#define AIU_CRC_STATUS			0x114
-+#define AIU_CRC_SHIFT_REG		0x118
-+#define AIU_CRC_IREG			0x11C
-+#define AIU_CRC_CAL_REG1		0x120
-+#define AIU_CRC_CAL_REG0		0x124
-+#define AIU_CRC_POLY_COEF1		0x128
-+#define AIU_CRC_POLY_COEF0		0x12C
-+#define AIU_CRC_BIT_SIZE1		0x130
-+#define AIU_CRC_BIT_SIZE0		0x134
-+#define AIU_CRC_BIT_CNT1		0x138
-+#define AIU_CRC_BIT_CNT0		0x13C
-+#define AIU_AMCLK_GATE_HI		0x140
-+#define AIU_AMCLK_GATE_LO		0x144
-+#define AIU_AMCLK_MSR			0x148
-+#define AIU_AUDAC_CTRL0			0x14C	/* Unknown */
-+#define AIU_DELTA_SIGMA0		0x154	/* Unknown */
-+#define AIU_DELTA_SIGMA1		0x158	/* Unknown */
-+#define AIU_DELTA_SIGMA2		0x15C	/* Unknown */
-+#define AIU_DELTA_SIGMA3		0x160	/* Unknown */
-+#define AIU_DELTA_SIGMA4		0x164	/* Unknown */
-+#define AIU_DELTA_SIGMA5		0x168	/* Unknown */
-+#define AIU_DELTA_SIGMA6		0x16C	/* Unknown */
-+#define AIU_DELTA_SIGMA7		0x170	/* Unknown */
-+#define AIU_DELTA_SIGMA_LCNTS		0x174	/* Unknown */
-+#define AIU_DELTA_SIGMA_RCNTS		0x178	/* Unknown */
-+#define AIU_MEM_I2S_START_PTR		0x180
-+#define AIU_MEM_I2S_RD_PTR		0x184
-+#define AIU_MEM_I2S_END_PTR		0x188
-+#define AIU_MEM_I2S_MASKS		0x18C
-+#define AIU_MEM_I2S_CONTROL		0x190
-+#define AIU_MEM_IEC958_START_PTR	0x194
-+#define AIU_MEM_IEC958_RD_PTR		0x198
-+#define AIU_MEM_IEC958_END_PTR		0x19C
-+#define AIU_MEM_IEC958_MASKS		0x1A0
-+#define AIU_MEM_IEC958_CONTROL		0x1A4
-+#define AIU_MEM_AIFIFO2_START_PTR	0x1A8
-+#define AIU_MEM_AIFIFO2_CURR_PTR	0x1AC
-+#define AIU_MEM_AIFIFO2_END_PTR		0x1B0
-+#define AIU_MEM_AIFIFO2_BYTES_AVAIL	0x1B4
-+#define AIU_MEM_AIFIFO2_CONTROL		0x1B8
-+#define AIU_MEM_AIFIFO2_MAN_WP		0x1BC
-+#define AIU_MEM_AIFIFO2_MAN_RP		0x1C0
-+#define AIU_MEM_AIFIFO2_LEVEL		0x1C4
-+#define AIU_MEM_AIFIFO2_BUF_CNTL	0x1C8
-+#define AIU_MEM_I2S_MAN_WP		0x1CC
-+#define AIU_MEM_I2S_MAN_RP		0x1D0
-+#define AIU_MEM_I2S_LEVEL		0x1D4
-+#define AIU_MEM_I2S_BUF_CNTL		0x1D8
-+#define AIU_MEM_I2S_BUF_WRAP_COUNT	0x1DC
-+#define AIU_MEM_I2S_MEM_CTL		0x1E0
-+#define AIU_MEM_IEC958_MEM_CTL		0x1E4
-+#define AIU_MEM_IEC958_WRAP_COUNT	0x1E8
-+#define AIU_MEM_IEC958_IRQ_LEVEL	0x1EC
-+#define AIU_MEM_IEC958_MAN_WP		0x1F0
-+#define AIU_MEM_IEC958_MAN_RP		0x1F4
-+#define AIU_MEM_IEC958_LEVEL		0x1F8
-+#define AIU_MEM_IEC958_BUF_CNTL		0x1FC
-+#define AIU_AIFIFO_CTRL			0x200
-+#define AIU_AIFIFO_STATUS		0x204
-+#define AIU_AIFIFO_GBIT			0x208
-+#define AIU_AIFIFO_CLB			0x20C
-+#define AIU_MEM_AIFIFO_START_PTR	0x210
-+#define AIU_MEM_AIFIFO_CURR_PTR		0x214
-+#define AIU_MEM_AIFIFO_END_PTR		0x218
-+#define AIU_MEM_AIFIFO_BYTES_AVAIL	0x21C
-+#define AIU_MEM_AIFIFO_CONTROL		0x220
-+#define AIU_MEM_AIFIFO_MAN_WP		0x224
-+#define AIU_MEM_AIFIFO_MAN_RP		0x228
-+#define AIU_MEM_AIFIFO_LEVEL		0x22C
-+#define AIU_MEM_AIFIFO_BUF_CNTL		0x230
-+#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT	0x234
-+#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT	0x238
-+#define AIU_MEM_AIFIFO_MEM_CTL		0x23C
-+#define AIFIFO_TIME_STAMP_CNTL		0x240
-+#define AIFIFO_TIME_STAMP_SYNC_0	0x244
-+#define AIFIFO_TIME_STAMP_SYNC_1	0x248
-+#define AIFIFO_TIME_STAMP_0		0x24C
-+#define AIFIFO_TIME_STAMP_1		0x250
-+#define AIFIFO_TIME_STAMP_2		0x254
-+#define AIFIFO_TIME_STAMP_3		0x258
-+#define AIFIFO_TIME_STAMP_LENGTH	0x25C
-+#define AIFIFO2_TIME_STAMP_CNTL		0x260
-+#define AIFIFO2_TIME_STAMP_SYNC_0	0x264
-+#define AIFIFO2_TIME_STAMP_SYNC_1	0x268
-+#define AIFIFO2_TIME_STAMP_0		0x26C
-+#define AIFIFO2_TIME_STAMP_1		0x270
-+#define AIFIFO2_TIME_STAMP_2		0x274
-+#define AIFIFO2_TIME_STAMP_3		0x278
-+#define AIFIFO2_TIME_STAMP_LENGTH	0x27C
-+#define IEC958_TIME_STAMP_CNTL		0x280
-+#define IEC958_TIME_STAMP_SYNC_0	0x284
-+#define IEC958_TIME_STAMP_SYNC_1	0x288
-+#define IEC958_TIME_STAMP_0		0x28C
-+#define IEC958_TIME_STAMP_1		0x290
-+#define IEC958_TIME_STAMP_2		0x294
-+#define IEC958_TIME_STAMP_3		0x298
-+#define IEC958_TIME_STAMP_LENGTH	0x29C
-+#define AIU_MEM_AIFIFO2_MEM_CTL		0x2A0
-+#define AIU_I2S_CBUS_DDR_CNTL		0x2A4
-+#define AIU_I2S_CBUS_DDR_WDATA		0x2A8
-+#define AIU_I2S_CBUS_DDR_ADDR		0x2AC
-+
-+#endif /* _AIU_REGS_H_ */
-diff --git a/sound/soc/meson/audin-regs.h b/sound/soc/meson/audin-regs.h
-new file mode 100644
-index 0000000..f224610
---- /dev/null
-+++ b/sound/soc/meson/audin-regs.h
-@@ -0,0 +1,148 @@
-+/*
-+ * Copyright (C) 2017 BayLibre, SAS
-+ * Author: Jerome Brunet <jbrunet@baylibre.com>
-+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef _AUDIN_REGS_H_
-+#define _AUDIN_REGS_H_
-+
-+/*
-+ * Note :
-+ * Datasheet issue page 196
-+ * AUDIN_MUTE_VAL 0x35 => impossible: Already assigned to AUDIN_FIFO1_PTR
-+ * AUDIN_FIFO1_PTR is more likely to be correct here since surrounding registers
-+ * also deal with AUDIN_FIFO1
-+ *
-+ * Clarification needed from Amlogic
-+ */
-+
-+#define AUDIN_SPDIF_MODE		0x000
-+#define AUDIN_SPDIF_FS_CLK_RLTN		0x004
-+#define AUDIN_SPDIF_CHNL_STS_A		0x008
-+#define AUDIN_SPDIF_CHNL_STS_B		0x00C
-+#define AUDIN_SPDIF_MISC		0x010
-+#define AUDIN_SPDIF_NPCM_PCPD		0x014
-+#define AUDIN_SPDIF_END			0x03C	/* Unknown */
-+#define AUDIN_I2SIN_CTRL		0x040
-+#define AUDIN_SOURCE_SEL		0x044
-+#define AUDIN_DECODE_FORMAT		0x048
-+#define AUDIN_DECODE_CONTROL_STATUS	0x04C
-+#define AUDIN_DECODE_CHANNEL_STATUS_A_0	0x050
-+#define AUDIN_DECODE_CHANNEL_STATUS_A_1	0x054
-+#define AUDIN_DECODE_CHANNEL_STATUS_A_2	0x058
-+#define AUDIN_DECODE_CHANNEL_STATUS_A_3	0x05C
-+#define AUDIN_DECODE_CHANNEL_STATUS_A_4	0x060
-+#define AUDIN_DECODE_CHANNEL_STATUS_A_5	0x064
-+#define AUDIN_FIFO0_START		0x080
-+#define AUDIN_FIFO0_END			0x084
-+#define AUDIN_FIFO0_PTR			0x088
-+#define AUDIN_FIFO0_INTR		0x08C
-+#define AUDIN_FIFO0_RDPTR		0x090
-+#define AUDIN_FIFO0_CTRL		0x094
-+#define AUDIN_FIFO0_CTRL1		0x098
-+#define AUDIN_FIFO0_LVL0		0x09C
-+#define AUDIN_FIFO0_LVL1		0x0A0
-+#define AUDIN_FIFO0_LVL2		0x0A4
-+#define AUDIN_FIFO0_REQID		0x0C0
-+#define AUDIN_FIFO0_WRAP		0x0C4
-+#define AUDIN_FIFO1_START		0x0CC
-+#define AUDIN_FIFO1_END			0x0D0
-+#define AUDIN_FIFO1_PTR			0x0D4
-+#define AUDIN_FIFO1_INTR		0x0D8
-+#define AUDIN_FIFO1_RDPTR		0x0DC
-+#define AUDIN_FIFO1_CTRL		0x0E0
-+#define AUDIN_FIFO1_CTRL1		0x0E4
-+#define AUDIN_FIFO1_LVL0		0x100
-+#define AUDIN_FIFO1_LVL1		0x104
-+#define AUDIN_FIFO1_LVL2		0x108
-+#define AUDIN_FIFO1_REQID		0x10C
-+#define AUDIN_FIFO1_WRAP		0x110
-+#define AUDIN_FIFO2_START		0x114
-+#define AUDIN_FIFO2_END			0x118
-+#define AUDIN_FIFO2_PTR			0x11C
-+#define AUDIN_FIFO2_INTR		0x120
-+#define AUDIN_FIFO2_RDPTR		0x124
-+#define AUDIN_FIFO2_CTRL		0x128
-+#define AUDIN_FIFO2_CTRL1		0x12C
-+#define AUDIN_FIFO2_LVL0		0x130
-+#define AUDIN_FIFO2_LVL1		0x134
-+#define AUDIN_FIFO2_LVL2		0x138
-+#define AUDIN_FIFO2_REQID		0x13C
-+#define AUDIN_FIFO2_WRAP		0x140
-+#define AUDIN_INT_CTRL			0x144
-+#define AUDIN_FIFO_INT			0x148
-+#define PCMIN_CTRL0			0x180
-+#define PCMIN_CTRL1			0x184
-+#define PCMIN1_CTRL0			0x188
-+#define PCMIN1_CTRL1			0x18C
-+#define PCMOUT_CTRL0			0x1C0
-+#define PCMOUT_CTRL1			0x1C4
-+#define PCMOUT_CTRL2			0x1C8
-+#define PCMOUT_CTRL3			0x1CC
-+#define PCMOUT1_CTRL0			0x1D0
-+#define PCMOUT1_CTRL1			0x1D4
-+#define PCMOUT1_CTRL2			0x1D8
-+#define PCMOUT1_CTRL3			0x1DC
-+#define AUDOUT_CTRL			0x200
-+#define AUDOUT_CTRL1			0x204
-+#define AUDOUT_BUF0_STA			0x208
-+#define AUDOUT_BUF0_EDA			0x20C
-+#define AUDOUT_BUF0_WPTR		0x210
-+#define AUDOUT_BUF1_STA			0x214
-+#define AUDOUT_BUF1_EDA			0x218
-+#define AUDOUT_BUF1_WPTR		0x21C
-+#define AUDOUT_FIFO_RPTR		0x220
-+#define AUDOUT_INTR_PTR			0x224
-+#define AUDOUT_FIFO_STS			0x228
-+#define AUDOUT1_CTRL			0x240
-+#define AUDOUT1_CTRL1			0x244
-+#define AUDOUT1_BUF0_STA		0x248
-+#define AUDOUT1_BUF0_EDA		0x24C
-+#define AUDOUT1_BUF0_WPTR		0x250
-+#define AUDOUT1_BUF1_STA		0x254
-+#define AUDOUT1_BUF1_EDA		0x258
-+#define AUDOUT1_BUF1_WPTR		0x25C
-+#define AUDOUT1_FIFO_RPTR		0x260
-+#define AUDOUT1_INTR_PTR		0x264
-+#define AUDOUT1_FIFO_STS		0x268
-+#define AUDIN_HDMI_MEAS_CTRL		0x280
-+#define AUDIN_HDMI_MEAS_CYCLES_M1	0x284
-+#define AUDIN_HDMI_MEAS_INTR_MASKN	0x288
-+#define AUDIN_HDMI_MEAS_INTR_STAT	0x28C
-+#define AUDIN_HDMI_REF_CYCLES_STAT_0	0x290
-+#define AUDIN_HDMI_REF_CYCLES_STAT_1	0x294
-+#define AUDIN_HDMIRX_AFIFO_STAT		0x298
-+#define AUDIN_FIFO0_PIO_STS		0x2C0
-+#define AUDIN_FIFO0_PIO_RDL		0x2C4
-+#define AUDIN_FIFO0_PIO_RDH		0x2C8
-+#define AUDIN_FIFO1_PIO_STS		0x2CC
-+#define AUDIN_FIFO1_PIO_RDL		0x2D0
-+#define AUDIN_FIFO1_PIO_RDH		0x2D4
-+#define AUDIN_FIFO2_PIO_STS		0x2D8
-+#define AUDIN_FIFO2_PIO_RDL		0x2DC
-+#define AUDIN_FIFO2_PIO_RDH		0x2E0
-+#define AUDOUT_FIFO_PIO_STS		0x2E4
-+#define AUDOUT_FIFO_PIO_WRL		0x2E8
-+#define AUDOUT_FIFO_PIO_WRH		0x2EC
-+#define AUDOUT1_FIFO_PIO_STS		0x2F0	/* Unknown */
-+#define AUDOUT1_FIFO_PIO_WRL		0x2F4	/* Unknown */
-+#define AUDOUT1_FIFO_PIO_WRH		0x2F8	/* Unknown */
-+#define AUD_RESAMPLE_CTRL0		0x2FC
-+#define AUD_RESAMPLE_CTRL1		0x300
-+#define AUD_RESAMPLE_STATUS		0x304
-+
-+#endif /* _AUDIN_REGS_H_ */
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0023-ASoC-meson-add-aiu-i2s-dma-support.patch

@@ -1,417 +0,0 @@
-From 03285555d8cbb3eb1f4991b758e5804a3c19b4ce Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Thu, 30 Mar 2017 12:14:40 +0200
-Subject: [PATCH 23/39] ASoC: meson: add aiu i2s dma support
-
-Add support for the i2s output dma which is part of the AIU block
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- sound/soc/meson/Kconfig       |   7 +
- sound/soc/meson/Makefile      |   2 +
- sound/soc/meson/aiu-i2s-dma.c | 367 ++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 376 insertions(+)
- create mode 100644 sound/soc/meson/aiu-i2s-dma.c
-
-diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
-index 216c850..ad31a11 100644
---- a/sound/soc/meson/Kconfig
-+++ b/sound/soc/meson/Kconfig
-@@ -7,3 +7,10 @@ menuconfig SND_SOC_MESON
- 	  Say Y or M if you want to add support for codecs attached to
- 	  the Amlogic Meson SoCs Audio interfaces. You will also need to
- 	  select the audio interfaces to support below.
-+
-+config SND_SOC_MESON_I2S
-+	tristate "Meson i2s interface"
-+	depends on SND_SOC_MESON
-+	help
-+	  Say Y or M if you want to add support for i2s dma driver for Amlogic
-+	  Meson SoCs.
-diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
-index 22028ab..273f275 100644
---- a/sound/soc/meson/Makefile
-+++ b/sound/soc/meson/Makefile
-@@ -1,3 +1,5 @@
- snd-soc-meson-audio-core-objs	 := audio-core.o
-+snd-soc-meson-aiu-i2s-dma-objs	 := aiu-i2s-dma.o
- 
- obj-$(CONFIG_SND_SOC_MESON)		+= snd-soc-meson-audio-core.o
-+obj-$(CONFIG_SND_SOC_MESON_I2S)		+= snd-soc-meson-aiu-i2s-dma.o
-diff --git a/sound/soc/meson/aiu-i2s-dma.c b/sound/soc/meson/aiu-i2s-dma.c
-new file mode 100644
-index 0000000..bab950d
---- /dev/null
-+++ b/sound/soc/meson/aiu-i2s-dma.c
-@@ -0,0 +1,367 @@
-+/*
-+ * Copyright (C) 2017 BayLibre, SAS
-+ * Author: Jerome Brunet <jbrunet@baylibre.com>
-+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+#include "aiu-regs.h"
-+#include "audio-core.h"
-+
-+#define DRV_NAME "meson-aiu-i2s-dma"
-+
-+struct aiu_i2s_dma {
-+	struct meson_audio_core_data *core;
-+	struct clk *fast;
-+	int irq;
-+};
-+
-+#define AIU_MEM_I2S_BUF_CNTL_INIT		BIT(0)
-+#define AIU_MEM_I2S_CONTROL_INIT		BIT(0)
-+#define AIU_MEM_I2S_CONTROL_FILL_EN		BIT(1)
-+#define AIU_MEM_I2S_CONTROL_EMPTY_EN		BIT(2)
-+#define AIU_MEM_I2S_CONTROL_MODE_16BIT		BIT(6)
-+#define AIU_MEM_I2S_CONTROL_BUSY		BIT(7)
-+#define AIU_MEM_I2S_CONTROL_DATA_READY		BIT(8)
-+#define AIU_MEM_I2S_CONTROL_LEVEL_CNTL		BIT(9)
-+#define AIU_MEM_I2S_MASKS_IRQ_BLOCK_MASK	GENMASK(31, 16)
-+#define AIU_MEM_I2S_MASKS_IRQ_BLOCK(n)		((n) << 16)
-+#define AIU_MEM_I2S_MASKS_CH_MEM_MASK		GENMASK(15, 8)
-+#define AIU_MEM_I2S_MASKS_CH_MEM(ch)		((ch) << 8)
-+#define AIU_MEM_I2S_MASKS_CH_RD_MASK		GENMASK(7, 0)
-+#define AIU_MEM_I2S_MASKS_CH_RD(ch)		((ch) << 0)
-+#define AIU_RST_SOFT_I2S_FAST_DOMAIN		BIT(0)
-+#define AIU_RST_SOFT_I2S_SLOW_DOMAIN		BIT(1)
-+
-+/*
-+ * The DMA works by i2s "blocks" (or DMA burst). The burst size and the memory
-+ * layout expected depends on the mode of operation.
-+ *
-+ * - Normal mode: The channels are expected to be packed in 32 bytes groups
-+ *  interleaved the buffer. AIU_MEM_I2S_MASKS_CH_MEM is a bitfield representing
-+ *  the channels present in memory. AIU_MEM_I2S_MASKS_CH_MEM represents the
-+ *  channels read by the DMA. This is very flexible but the unsual memory layout
-+ *  makes it less easy to deal with. The burst size is 32 bytes times the number
-+ *  of channels read.
-+ *
-+ * - Split mode:
-+ * Classical channel interleaved frame organisation. In this mode,
-+ * AIU_MEM_I2S_MASKS_CH_MEM and AIU_MEM_I2S_MASKS_CH_MEM must be set to 0xff and
-+ * the burst size is fixed to 256 bytes. The input can be either 2 or 8
-+ * channels.
-+ *
-+ * The following driver implements the split mode.
-+ */
-+
-+#define AIU_I2S_DMA_BURST 256
-+
-+static struct snd_pcm_hardware aiu_i2s_dma_hw = {
-+	.info = (SNDRV_PCM_INFO_INTERLEAVED |
-+		 SNDRV_PCM_INFO_MMAP |
-+		 SNDRV_PCM_INFO_MMAP_VALID |
-+		 SNDRV_PCM_INFO_PAUSE),
-+
-+	.formats = (SNDRV_PCM_FMTBIT_S16_LE |
-+		    SNDRV_PCM_FMTBIT_S24_LE |
-+		    SNDRV_PCM_FMTBIT_S32_LE),
-+
-+	/*
-+	 * TODO: The DMA can change the endianness, the msb position
-+	 * and deal with unsigned - support this later on
-+	 */
-+
-+	.rate_min = 8000,
-+	.rate_max = 192000,
-+	.channels_min = 2,
-+	.channels_max = 8,
-+	.period_bytes_min = AIU_I2S_DMA_BURST,
-+	.period_bytes_max = AIU_I2S_DMA_BURST * 65535,
-+	.periods_min = 2,
-+	.periods_max = UINT_MAX,
-+	.buffer_bytes_max = 1 * 1024 * 1024,
-+	.fifo_size = 0,
-+};
-+
-+static struct aiu_i2s_dma *aiu_i2s_dma_priv(struct snd_pcm_substream *s)
-+{
-+	struct snd_soc_pcm_runtime *rtd = s->private_data;
-+
-+	return snd_soc_platform_get_drvdata(rtd->platform);
-+}
-+
-+static snd_pcm_uframes_t
-+aiu_i2s_dma_pointer(struct snd_pcm_substream *substream)
-+{
-+	struct snd_pcm_runtime *runtime = substream->runtime;
-+	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
-+	unsigned int addr;
-+	int ret;
-+
-+	ret = regmap_read(priv->core->aiu, AIU_MEM_I2S_RD_PTR,
-+			  &addr);
-+	if (ret)
-+		return 0;
-+
-+	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
-+}
-+
-+static void __dma_enable(struct aiu_i2s_dma *priv, bool enable)
-+{
-+	unsigned int en_mask = (AIU_MEM_I2S_CONTROL_FILL_EN |
-+				AIU_MEM_I2S_CONTROL_EMPTY_EN);
-+
-+	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL, en_mask,
-+			   enable ? en_mask : 0);
-+
-+}
-+
-+static int aiu_i2s_dma_trigger(struct snd_pcm_substream *substream, int cmd)
-+{
-+	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
-+
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+		__dma_enable(priv, true);
-+		break;
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+	case SNDRV_PCM_TRIGGER_STOP:
-+		__dma_enable(priv, false);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static void __dma_init_mem(struct aiu_i2s_dma *priv)
-+{
-+	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL,
-+			   AIU_MEM_I2S_CONTROL_INIT,
-+			   AIU_MEM_I2S_CONTROL_INIT);
-+	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_BUF_CNTL,
-+			   AIU_MEM_I2S_BUF_CNTL_INIT,
-+			   AIU_MEM_I2S_BUF_CNTL_INIT);
-+
-+	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL,
-+			   AIU_MEM_I2S_CONTROL_INIT,
-+			   0);
-+	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_BUF_CNTL,
-+			   AIU_MEM_I2S_BUF_CNTL_INIT,
-+			   0);
-+}
-+
-+static int aiu_i2s_dma_prepare(struct snd_pcm_substream *substream)
-+{
-+	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
-+
-+	__dma_init_mem(priv);
-+
-+	return 0;
-+}
-+
-+static int aiu_i2s_dma_hw_params(struct snd_pcm_substream *substream,
-+				 struct snd_pcm_hw_params *params)
-+{
-+	struct snd_pcm_runtime *runtime = substream->runtime;
-+	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
-+	int ret;
-+	u32 burst_num, mem_ctl;
-+	dma_addr_t end_ptr;
-+
-+	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Setup memory layout */
-+	if (params_physical_width(params) == 16)
-+		mem_ctl = AIU_MEM_I2S_CONTROL_MODE_16BIT;
-+	else
-+		mem_ctl = 0;
-+
-+	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL,
-+			   AIU_MEM_I2S_CONTROL_MODE_16BIT,
-+			   mem_ctl);
-+
-+	/* Initialize memory pointers */
-+	regmap_write(priv->core->aiu, AIU_MEM_I2S_START_PTR, runtime->dma_addr);
-+	regmap_write(priv->core->aiu, AIU_MEM_I2S_RD_PTR, runtime->dma_addr);
-+
-+	/* The end pointer is the address of the last valid block */
-+	end_ptr = runtime->dma_addr + runtime->dma_bytes - AIU_I2S_DMA_BURST;
-+	regmap_write(priv->core->aiu, AIU_MEM_I2S_END_PTR, end_ptr);
-+
-+	/* Memory masks */
-+	burst_num = params_period_bytes(params) / AIU_I2S_DMA_BURST;
-+	regmap_write(priv->core->aiu, AIU_MEM_I2S_MASKS,
-+		     AIU_MEM_I2S_MASKS_CH_RD(0xff) |
-+		     AIU_MEM_I2S_MASKS_CH_MEM(0xff) |
-+		     AIU_MEM_I2S_MASKS_IRQ_BLOCK(burst_num));
-+
-+	return 0;
-+}
-+
-+static int aiu_i2s_dma_hw_free(struct snd_pcm_substream *substream)
-+{
-+	return snd_pcm_lib_free_pages(substream);
-+}
-+
-+
-+static irqreturn_t aiu_i2s_dma_irq_block(int irq, void *dev_id)
-+{
-+	struct snd_pcm_substream *playback = dev_id;
-+
-+	snd_pcm_period_elapsed(playback);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int aiu_i2s_dma_open(struct snd_pcm_substream *substream)
-+{
-+	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
-+	int ret;
-+
-+	snd_soc_set_runtime_hwparams(substream, &aiu_i2s_dma_hw);
-+
-+	/*
-+	 * Make sure the buffer and period size are multiple of the DMA burst
-+	 * size
-+	 */
-+	ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
-+					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
-+					 AIU_I2S_DMA_BURST);
-+	if (ret)
-+		return ret;
-+
-+	ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
-+					 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
-+					 AIU_I2S_DMA_BURST);
-+	if (ret)
-+		return ret;
-+
-+	/* Request the I2S DDR irq */
-+	ret = request_irq(priv->irq, aiu_i2s_dma_irq_block, 0,
-+			  DRV_NAME, substream);
-+	if (ret)
-+		return ret;
-+
-+	/* Power up the i2s fast domain - can't write the registers w/o it */
-+	ret = clk_prepare_enable(priv->fast);
-+	if (ret)
-+		return ret;
-+
-+	/* Make sure the dma is initially disabled */
-+	__dma_enable(priv, false);
-+
-+	return 0;
-+}
-+
-+static int aiu_i2s_dma_close(struct snd_pcm_substream *substream)
-+{
-+	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
-+
-+	clk_disable_unprepare(priv->fast);
-+	free_irq(priv->irq, substream);
-+
-+	return 0;
-+}
-+
-+static const struct snd_pcm_ops aiu_i2s_dma_ops = {
-+	.open =		aiu_i2s_dma_open,
-+	.close =        aiu_i2s_dma_close,
-+	.ioctl =	snd_pcm_lib_ioctl,
-+	.hw_params =	aiu_i2s_dma_hw_params,
-+	.hw_free =      aiu_i2s_dma_hw_free,
-+	.prepare =      aiu_i2s_dma_prepare,
-+	.pointer =	aiu_i2s_dma_pointer,
-+	.trigger =	aiu_i2s_dma_trigger,
-+};
-+
-+static int aiu_i2s_dma_new(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_card *card = rtd->card->snd_card;
-+	size_t size = aiu_i2s_dma_hw.buffer_bytes_max;
-+
-+	return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
-+						     SNDRV_DMA_TYPE_DEV,
-+						     card->dev, size, size);
-+}
-+
-+struct snd_soc_platform_driver aiu_i2s_platform = {
-+	.ops		= &aiu_i2s_dma_ops,
-+	.pcm_new	= aiu_i2s_dma_new,
-+};
-+
-+static int aiu_i2s_dma_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct aiu_i2s_dma *priv;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, priv);
-+	priv->core = dev_get_drvdata(dev->parent);
-+
-+	priv->fast = devm_clk_get(dev, "fast");
-+	if (IS_ERR(priv->fast)) {
-+		if (PTR_ERR(priv->fast) != -EPROBE_DEFER)
-+			dev_err(dev, "Can't get i2s fast domain clock\n");
-+		return PTR_ERR(priv->fast);
-+	}
-+
-+	priv->irq = platform_get_irq(pdev, 0);
-+	if (priv->irq <= 0) {
-+		dev_err(dev, "Can't get i2s ddr irq\n");
-+		return priv->irq;
-+	}
-+
-+	return snd_soc_register_platform(dev, &aiu_i2s_platform);
-+}
-+
-+static const struct of_device_id aiu_i2s_dma_of_match[] = {
-+	{ .compatible = "amlogic,meson-aiu-i2s-dma", },
-+	{ .compatible = "amlogic,meson-gxbb-aiu-i2s-dma", },
-+	{ .compatible = "amlogic,meson-gxl-aiu-i2s-dma", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, aiu_i2s_dma_of_match);
-+
-+static struct platform_driver aiu_i2s_dma_pdrv = {
-+	.probe = aiu_i2s_dma_probe,
-+	.driver = {
-+		.name = DRV_NAME,
-+		.of_match_table = aiu_i2s_dma_of_match,
-+	},
-+};
-+module_platform_driver(aiu_i2s_dma_pdrv);
-+
-+MODULE_DESCRIPTION("Meson AIU i2s DMA ASoC Driver");
-+MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
-+MODULE_LICENSE("GPL v2");
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0024-ASoC-meson-add-initial-i2s-dai-support.patch

@@ -1,515 +0,0 @@
-From e273b0687bfb891ca4962dfe96e174371853ae89 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Thu, 30 Mar 2017 12:17:27 +0200
-Subject: [PATCH 24/39] ASoC: meson: add initial i2s dai support
-
-Add support for the i2s dai found on Amlogic Meson SoC family.
-With this initial implementation, only playback is supported.
-Capture will be part of furture work.
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- sound/soc/meson/Kconfig   |   2 +-
- sound/soc/meson/Makefile  |   2 +
- sound/soc/meson/i2s-dai.c | 465 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 468 insertions(+), 1 deletion(-)
- create mode 100644 sound/soc/meson/i2s-dai.c
-
-diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
-index ad31a11..604c9e2 100644
---- a/sound/soc/meson/Kconfig
-+++ b/sound/soc/meson/Kconfig
-@@ -12,5 +12,5 @@ config SND_SOC_MESON_I2S
- 	tristate "Meson i2s interface"
- 	depends on SND_SOC_MESON
- 	help
--	  Say Y or M if you want to add support for i2s dma driver for Amlogic
-+	  Say Y or M if you want to add support for i2s driver for Amlogic
- 	  Meson SoCs.
-diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
-index 273f275..ea06dde 100644
---- a/sound/soc/meson/Makefile
-+++ b/sound/soc/meson/Makefile
-@@ -1,5 +1,7 @@
- snd-soc-meson-audio-core-objs	 := audio-core.o
- snd-soc-meson-aiu-i2s-dma-objs	 := aiu-i2s-dma.o
-+snd-soc-meson-i2s-dai-objs	 := i2s-dai.o
- 
- obj-$(CONFIG_SND_SOC_MESON)		+= snd-soc-meson-audio-core.o
- obj-$(CONFIG_SND_SOC_MESON_I2S)		+= snd-soc-meson-aiu-i2s-dma.o
-+obj-$(CONFIG_SND_SOC_MESON_I2S)		+= snd-soc-meson-i2s-dai.o
-diff --git a/sound/soc/meson/i2s-dai.c b/sound/soc/meson/i2s-dai.c
-new file mode 100644
-index 0000000..1008af8
---- /dev/null
-+++ b/sound/soc/meson/i2s-dai.c
-@@ -0,0 +1,465 @@
-+/*
-+ * Copyright (C) 2017 BayLibre, SAS
-+ * Author: Jerome Brunet <jbrunet@baylibre.com>
-+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dai.h>
-+
-+#include "aiu-regs.h"
-+#include "audio-core.h"
-+
-+#define DRV_NAME "meson-i2s-dai"
-+
-+struct meson_i2s_dai {
-+	struct meson_audio_core_data *core;
-+	struct clk *mclk;
-+	struct clk *bclks;
-+	struct clk *iface;
-+	struct clk *fast;
-+	bool bclks_idle;
-+};
-+
-+#define AIU_CLK_CTRL_I2S_DIV_EN			BIT(0)
-+#define AIU_CLK_CTRL_I2S_DIV_MASK		GENMASK(3, 2)
-+#define AIU_CLK_CTRL_AOCLK_POLARITY_MASK	BIT(6)
-+#define AIU_CLK_CTRL_AOCLK_POLARITY_NORMAL	(0 << 6)
-+#define AIU_CLK_CTRL_AOCLK_POLARITY_INVERTED	(1 << 6)
-+#define AIU_CLK_CTRL_ALRCLK_POLARITY_MASK	BIT(7)
-+#define AIU_CLK_CTRL_ALRCLK_POLARITY_NORMAL	(0 << 7)
-+#define AIU_CLK_CTRL_ALRCLK_POLARITY_INVERTED	(1 << 7)
-+#define AIU_CLK_CTRL_ALRCLK_SKEW_MASK		GENMASK(9, 8)
-+#define AIU_CLK_CTRL_ALRCLK_LEFT_J		(0 << 8)
-+#define AIU_CLK_CTRL_ALRCLK_I2S			(1 << 8)
-+#define AIU_CLK_CTRL_ALRCLK_RIGHT_J		(2 << 8)
-+#define AIU_CLK_CTRL_MORE_I2S_DIV_MASK		GENMASK(5, 0)
-+#define AIU_CLK_CTRL_MORE_I2S_DIV(div)		(((div) - 1) << 0)
-+#define AIU_CODEC_DAC_LRCLK_CTRL_DIV_MASK	GENMASK(11, 0)
-+#define AIU_CODEC_DAC_LRCLK_CTRL_DIV(div)	(((div) - 1) << 0)
-+#define AIU_I2S_DAC_CFG_PAYLOAD_SIZE_MASK	GENMASK(1, 0)
-+#define AIU_I2S_DAC_CFG_AOCLK_32		(0 << 0)
-+#define AIU_I2S_DAC_CFG_AOCLK_48		(2 << 0)
-+#define AIU_I2S_DAC_CFG_AOCLK_64		(3 << 0)
-+#define AIU_I2S_MISC_HOLD_EN			BIT(2)
-+#define AIU_I2S_SOURCE_DESC_MODE_8CH		BIT(0)
-+#define AIU_I2S_SOURCE_DESC_MODE_24BIT		BIT(5)
-+#define AIU_I2S_SOURCE_DESC_MODE_32BIT		BIT(9)
-+#define AIU_I2S_SOURCE_DESC_MODE_SPLIT		BIT(11)
-+
-+static void __hold(struct meson_i2s_dai *priv, bool enable)
-+{
-+	regmap_update_bits(priv->core->aiu, AIU_I2S_MISC,
-+			   AIU_I2S_MISC_HOLD_EN,
-+			   enable ? AIU_I2S_MISC_HOLD_EN : 0);
-+}
-+
-+static void __divider_enable(struct meson_i2s_dai *priv, bool enable)
-+{
-+	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
-+			   AIU_CLK_CTRL_I2S_DIV_EN,
-+			   enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
-+}
-+
-+static void __playback_start(struct meson_i2s_dai *priv)
-+{
-+	__divider_enable(priv, true);
-+	__hold(priv, false);
-+}
-+
-+static void __playback_stop(struct meson_i2s_dai *priv, bool clk_force)
-+{
-+	__hold(priv, true);
-+	/* Disable the bit clks if necessary */
-+	if (clk_force || !priv->bclks_idle)
-+		__divider_enable(priv, false);
-+}
-+
-+static int meson_i2s_dai_trigger(struct snd_pcm_substream *substream, int cmd,
-+				 struct snd_soc_dai *dai)
-+{
-+	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
-+	bool clk_force_stop = false;
-+
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+		__playback_start(priv);
-+		return 0;
-+
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+		clk_force_stop = true;
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+		__playback_stop(priv, clk_force_stop);
-+		return 0;
-+
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int __bclks_set_rate(struct meson_i2s_dai *priv, unsigned int srate,
-+			    unsigned int width)
-+{
-+	unsigned int fs;
-+
-+	/* Get the oversampling factor */
-+	fs = DIV_ROUND_CLOSEST(clk_get_rate(priv->mclk), srate);
-+
-+	/*
-+	 * This DAI is usually connected to the dw-hdmi which does not support
-+	 * bclk being 32 * lrclk or 48 * lrclk
-+	 * Restrict to blck = 64 * lrclk
-+	 */
-+	if (fs % 64)
-+		return -EINVAL;
-+
-+	/* Set the divider between lrclk and bclk */
-+	regmap_update_bits(priv->core->aiu, AIU_I2S_DAC_CFG,
-+			   AIU_I2S_DAC_CFG_PAYLOAD_SIZE_MASK,
-+			   AIU_I2S_DAC_CFG_AOCLK_64);
-+
-+	regmap_update_bits(priv->core->aiu, AIU_CODEC_DAC_LRCLK_CTRL,
-+			   AIU_CODEC_DAC_LRCLK_CTRL_DIV_MASK,
-+			   AIU_CODEC_DAC_LRCLK_CTRL_DIV(64));
-+
-+	/* Use CLK_MORE for the i2s divider */
-+	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
-+			   AIU_CLK_CTRL_I2S_DIV_MASK,
-+			   0);
-+
-+	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL_MORE,
-+			   AIU_CLK_CTRL_MORE_I2S_DIV_MASK,
-+			   AIU_CLK_CTRL_MORE_I2S_DIV(fs / 64));
-+
-+	return 0;
-+}
-+
-+static int __setup_desc(struct meson_i2s_dai *priv, unsigned int width,
-+			unsigned int channels)
-+{
-+	u32 desc = 0;
-+
-+	switch (width) {
-+	case 24:
-+		/*
-+		 * For some reason, 24 bits wide audio don't play well
-+		 * if the 32 bits mode is not set
-+		 */
-+		desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT |
-+			 AIU_I2S_SOURCE_DESC_MODE_32BIT);
-+		break;
-+	case 16:
-+		break;
-+
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (channels) {
-+	case 2: /* Nothing to do */
-+		break;
-+	case 8:
-+		/* TODO: Still requires testing ... */
-+		desc |= AIU_I2S_SOURCE_DESC_MODE_8CH;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	regmap_update_bits(priv->core->aiu, AIU_I2S_SOURCE_DESC,
-+			   AIU_I2S_SOURCE_DESC_MODE_8CH |
-+			   AIU_I2S_SOURCE_DESC_MODE_24BIT |
-+			   AIU_I2S_SOURCE_DESC_MODE_32BIT,
-+			   desc);
-+
-+	return 0;
-+}
-+
-+static int meson_i2s_dai_hw_params(struct snd_pcm_substream *substream,
-+				   struct snd_pcm_hw_params *params,
-+				   struct snd_soc_dai *dai)
-+{
-+	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
-+	unsigned int width = params_width(params);
-+	unsigned int channels = params_channels(params);
-+	unsigned int rate = params_rate(params);
-+	int ret;
-+
-+	ret = __setup_desc(priv, width, channels);
-+	if (ret) {
-+		dev_err(dai->dev, "Unable set to set i2s description\n");
-+		return ret;
-+	}
-+
-+	ret = __bclks_set_rate(priv, rate, width);
-+	if (ret) {
-+		dev_err(dai->dev, "Unable set to the i2s clock rates\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int meson_i2s_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
-+	u32 val;
-+
-+	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
-+		return -EINVAL;
-+
-+	/* DAI output mode */
-+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+	case SND_SOC_DAIFMT_I2S:
-+		val = AIU_CLK_CTRL_ALRCLK_I2S;
-+		break;
-+	case SND_SOC_DAIFMT_LEFT_J:
-+		val = AIU_CLK_CTRL_ALRCLK_LEFT_J;
-+		break;
-+	case SND_SOC_DAIFMT_RIGHT_J:
-+		val = AIU_CLK_CTRL_ALRCLK_RIGHT_J;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
-+			   AIU_CLK_CTRL_ALRCLK_SKEW_MASK,
-+			   val);
-+
-+	/* DAI clock polarity */
-+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+	case SND_SOC_DAIFMT_IB_IF:
-+		/* Invert both clocks */
-+		val = AIU_CLK_CTRL_ALRCLK_POLARITY_INVERTED |
-+			AIU_CLK_CTRL_AOCLK_POLARITY_INVERTED;
-+		break;
-+	case SND_SOC_DAIFMT_IB_NF:
-+		/* Invert bit clock */
-+		val = AIU_CLK_CTRL_ALRCLK_POLARITY_NORMAL |
-+			AIU_CLK_CTRL_AOCLK_POLARITY_INVERTED;
-+		break;
-+	case SND_SOC_DAIFMT_NB_IF:
-+		/* Invert frame clock */
-+		val = AIU_CLK_CTRL_ALRCLK_POLARITY_INVERTED |
-+			AIU_CLK_CTRL_AOCLK_POLARITY_NORMAL;
-+		break;
-+	case SND_SOC_DAIFMT_NB_NF:
-+		/* Normal clocks */
-+		val = AIU_CLK_CTRL_ALRCLK_POLARITY_NORMAL |
-+			AIU_CLK_CTRL_AOCLK_POLARITY_NORMAL;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
-+			   AIU_CLK_CTRL_ALRCLK_POLARITY_MASK |
-+			   AIU_CLK_CTRL_AOCLK_POLARITY_MASK,
-+			   val);
-+
-+	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
-+	case SND_SOC_DAIFMT_CONT:
-+		priv->bclks_idle = true;
-+		break;
-+	case SND_SOC_DAIFMT_GATED:
-+		priv->bclks_idle = false;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int meson_i2s_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
-+				    unsigned int freq, int dir)
-+{
-+	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
-+	int ret;
-+
-+	if (WARN_ON(clk_id != 0))
-+		return -EINVAL;
-+
-+	if (dir == SND_SOC_CLOCK_IN)
-+		return 0;
-+
-+	ret = clk_set_rate(priv->mclk, freq);
-+	if (ret) {
-+		dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int meson_i2s_dai_startup(struct snd_pcm_substream *substream,
-+				 struct snd_soc_dai *dai)
-+{
-+	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
-+	int ret;
-+
-+	/* Power up the i2s fast domain - can't write the registers w/o it */
-+	ret = clk_prepare_enable(priv->fast);
-+	if (ret)
-+		goto out_clk_fast;
-+
-+	/* Make sure nothing gets out of the DAI yet */
-+	__hold(priv, true);
-+
-+	/* I2S encoder needs the mixer interface gate */
-+	ret = clk_prepare_enable(priv->iface);
-+	if (ret)
-+		goto out_clk_iface;
-+
-+	/* Enable the i2s master clock */
-+	ret = clk_prepare_enable(priv->mclk);
-+	if (ret)
-+		goto out_mclk;
-+
-+	/* Enable the bit clock gate */
-+	ret = clk_prepare_enable(priv->bclks);
-+	if (ret)
-+		goto out_bclks;
-+
-+	/* Make sure the interface expect a memory layout we can work with */
-+	regmap_update_bits(priv->core->aiu, AIU_I2S_SOURCE_DESC,
-+			   AIU_I2S_SOURCE_DESC_MODE_SPLIT,
-+			   AIU_I2S_SOURCE_DESC_MODE_SPLIT);
-+
-+	return 0;
-+
-+out_bclks:
-+	clk_disable_unprepare(priv->mclk);
-+out_mclk:
-+	clk_disable_unprepare(priv->iface);
-+out_clk_iface:
-+	clk_disable_unprepare(priv->fast);
-+out_clk_fast:
-+	return ret;
-+}
-+
-+static void meson_i2s_dai_shutdown(struct snd_pcm_substream *substream,
-+				   struct snd_soc_dai *dai)
-+{
-+	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
-+
-+	clk_disable_unprepare(priv->bclks);
-+	clk_disable_unprepare(priv->mclk);
-+	clk_disable_unprepare(priv->iface);
-+	clk_disable_unprepare(priv->fast);
-+}
-+
-+static const struct snd_soc_dai_ops meson_i2s_dai_ops = {
-+	.startup    = meson_i2s_dai_startup,
-+	.shutdown   = meson_i2s_dai_shutdown,
-+	.trigger    = meson_i2s_dai_trigger,
-+	.hw_params  = meson_i2s_dai_hw_params,
-+	.set_fmt    = meson_i2s_dai_set_fmt,
-+	.set_sysclk = meson_i2s_dai_set_sysclk,
-+};
-+
-+static struct snd_soc_dai_driver meson_i2s_dai = {
-+	.playback = {
-+		.stream_name = "Playback",
-+		.channels_min = 2,
-+		.channels_max = 8,
-+		.rates = SNDRV_PCM_RATE_8000_192000,
-+		.formats = (SNDRV_PCM_FMTBIT_S16_LE |
-+			    SNDRV_PCM_FMTBIT_S24_LE)
-+	},
-+	.ops = &meson_i2s_dai_ops,
-+};
-+
-+static const struct snd_soc_component_driver meson_i2s_dai_component = {
-+	.name	= DRV_NAME,
-+};
-+
-+static int meson_i2s_dai_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct meson_i2s_dai *priv;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, priv);
-+	priv->core = dev_get_drvdata(dev->parent);
-+
-+	priv->fast = devm_clk_get(dev, "fast");
-+	if (IS_ERR(priv->fast)) {
-+		if (PTR_ERR(priv->fast) != -EPROBE_DEFER)
-+			dev_err(dev, "Can't get the i2s fast domain clock\n");
-+		return PTR_ERR(priv->fast);
-+	}
-+
-+	priv->iface = devm_clk_get(dev, "iface");
-+	if (IS_ERR(priv->iface)) {
-+		if (PTR_ERR(priv->iface) != -EPROBE_DEFER)
-+			dev_err(dev, "Can't get i2s dai clock gate\n");
-+		return PTR_ERR(priv->iface);
-+	}
-+
-+	priv->bclks = devm_clk_get(dev, "bclks");
-+	if (IS_ERR(priv->bclks)) {
-+		if (PTR_ERR(priv->bclks) != -EPROBE_DEFER)
-+			dev_err(dev, "Can't get bit clocks gate\n");
-+		return PTR_ERR(priv->bclks);
-+	}
-+
-+	priv->mclk = devm_clk_get(dev, "mclk");
-+	if (IS_ERR(priv->mclk)) {
-+		if (PTR_ERR(priv->mclk) != -EPROBE_DEFER)
-+			dev_err(dev, "failed to get the i2s master clock\n");
-+		return PTR_ERR(priv->mclk);
-+	}
-+
-+	return devm_snd_soc_register_component(dev, &meson_i2s_dai_component,
-+					       &meson_i2s_dai, 1);
-+}
-+
-+static const struct of_device_id meson_i2s_dai_of_match[] = {
-+	{ .compatible = "amlogic,meson-i2s-dai", },
-+	{ .compatible = "amlogic,meson-gxbb-i2s-dai", },
-+	{ .compatible = "amlogic,meson-gxl-i2s-dai", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, meson_i2s_dai_of_match);
-+
-+static struct platform_driver meson_i2s_dai_pdrv = {
-+	.probe = meson_i2s_dai_probe,
-+	.driver = {
-+		.name = DRV_NAME,
-+		.of_match_table = meson_i2s_dai_of_match,
-+	},
-+};
-+module_platform_driver(meson_i2s_dai_pdrv);
-+
-+MODULE_DESCRIPTION("Meson i2s DAI ASoC Driver");
-+MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
-+MODULE_LICENSE("GPL v2");
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0025-snd-meson-activate-HDMI-audio-path.patch

@@ -1,55 +0,0 @@
-From f40a0d725ebdad433383010d1c5ef92eb99e41a7 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Fri, 7 Jul 2017 17:39:21 +0200
-Subject: [PATCH 25/39] snd: meson: activate HDMI audio path
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- sound/soc/meson/i2s-dai.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
-diff --git a/sound/soc/meson/i2s-dai.c b/sound/soc/meson/i2s-dai.c
-index 1008af8..63fe098 100644
---- a/sound/soc/meson/i2s-dai.c
-+++ b/sound/soc/meson/i2s-dai.c
-@@ -56,8 +56,19 @@ struct meson_i2s_dai {
- #define AIU_CLK_CTRL_ALRCLK_RIGHT_J		(2 << 8)
- #define AIU_CLK_CTRL_MORE_I2S_DIV_MASK		GENMASK(5, 0)
- #define AIU_CLK_CTRL_MORE_I2S_DIV(div)		(((div) - 1) << 0)
-+#define AIU_CLK_CTRL_MORE_HDMI_TX_SEL_MASK	BIT(6)
-+#define AIU_CLK_CTRL_MORE_HDMI_TX_I958_CLK	(0 << 6)
-+#define AIU_CLK_CTRL_MORE_HDMI_TX_INT_CLK	(1 << 6)
- #define AIU_CODEC_DAC_LRCLK_CTRL_DIV_MASK	GENMASK(11, 0)
- #define AIU_CODEC_DAC_LRCLK_CTRL_DIV(div)	(((div) - 1) << 0)
-+#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_MASK	GENMASK(1, 0)
-+#define AIU_HDMI_CLK_DATA_CTRL_CLK_DISABLE	(0 << 0)
-+#define AIU_HDMI_CLK_DATA_CTRL_CLK_PCM		(1 << 0)
-+#define AIU_HDMI_CLK_DATA_CTRL_CLK_I2S		(2 << 0)
-+#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_MASK	GENMASK(5, 4)
-+#define AIU_HDMI_CLK_DATA_CTRL_DATA_MUTE	(0 << 4)
-+#define AIU_HDMI_CLK_DATA_CTRL_DATA_PCM		(1 << 4)
-+#define AIU_HDMI_CLK_DATA_CTRL_DATA_I2S		(2 << 4)
- #define AIU_I2S_DAC_CFG_PAYLOAD_SIZE_MASK	GENMASK(1, 0)
- #define AIU_I2S_DAC_CFG_AOCLK_32		(0 << 0)
- #define AIU_I2S_DAC_CFG_AOCLK_48		(2 << 0)
-@@ -221,6 +232,17 @@ static int meson_i2s_dai_hw_params(struct snd_pcm_substream *substream,
- 		return ret;
- 	}
- 
-+	/* Quick and dirty hack for HDMI */
-+	regmap_update_bits(priv->core->aiu, AIU_HDMI_CLK_DATA_CTRL,
-+			   AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_MASK |
-+			   AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_MASK,
-+			   AIU_HDMI_CLK_DATA_CTRL_CLK_I2S |
-+			   AIU_HDMI_CLK_DATA_CTRL_DATA_I2S);
-+
-+	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL_MORE,
-+			   AIU_CLK_CTRL_MORE_HDMI_TX_SEL_MASK,
-+			   AIU_CLK_CTRL_MORE_HDMI_TX_INT_CLK);
-+
- 	return 0;
- }
- 
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0026-drm-meson-select-dw-hdmi-i2s-audio-for-meson-hdmi.patch

@@ -1,23 +0,0 @@
-From e5509c367852ca7a7b52c30fda3dfd2a763ee8f3 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Tue, 14 Feb 2017 19:18:04 +0100
-Subject: [PATCH 26/39] drm/meson: select dw-hdmi i2s audio for meson hdmi
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/meson/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
-index 3ce51d8..02d400b 100644
---- a/drivers/gpu/drm/meson/Kconfig
-+++ b/drivers/gpu/drm/meson/Kconfig
-@@ -13,3 +13,4 @@ config DRM_MESON_DW_HDMI
- 	depends on DRM_MESON
- 	default y if DRM_MESON
- 	select DRM_DW_HDMI
-+	select DRM_DW_HDMI_I2S_AUDIO
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0027-ARM64-defconfig-enable-audio-support-for-meson-SoCs-.patch

@@ -1,31 +0,0 @@
-From d74574d0836155eadde90e9ba12b8c4d18202d8e Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Fri, 31 Mar 2017 15:55:03 +0200
-Subject: [PATCH 27/39] ARM64: defconfig: enable audio support for meson SoCs
- as module
-
-Add audio support for meson SoCs. This includes the audio core
-driver and the i2s output interface
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/configs/defconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index dcf1090..beb5774 100644
---- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -405,6 +405,8 @@ CONFIG_SOUND=y
- CONFIG_SND=y
- CONFIG_SND_SOC=y
- CONFIG_SND_BCM2835_SOC_I2S=m
-+CONFIG_SND_SOC_MESON=m
-+CONFIG_SND_SOC_MESON_I2S=m
- CONFIG_SND_SOC_SAMSUNG=y
- CONFIG_SND_SOC_RCAR=m
- CONFIG_SND_SOC_AK4613=m
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0028-ARM64-dts-meson-gx-add-audio-controller-nodes.patch

@@ -1,89 +0,0 @@
-From 7bd8dcbb1f840fe6d4ae6a1f5f2d3708f09110f9 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Wed, 20 Sep 2017 17:22:47 +0200
-Subject: [PATCH 28/39] ARM64: dts: meson-gx: add audio controller nodes
-
-Add audio controller nodes for Amlogic meson gxl.
-This includes the audio-core node, the i2s DAI and i2s
-aiu DMAs.
-
-Audio on this SoC family is still a work in progress. More nodes are likely
-to be added later on (pcm DAIs, input DMAs, SPDIF etc ...)
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 22 ++++++++++++++++++++++
- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 23 +++++++++++++++++++++++
- 2 files changed, 45 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-index f175db8..ff27ce0 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-@@ -224,6 +224,28 @@
- 				#reset-cells = <1>;
- 			};
- 
-+			audio: audio@5400 {
-+				compatible = "amlogic,meson-audio-core";
-+				reg = <0x0 0x5400 0x0 0x2ac>,
-+				      <0x0 0xa000 0x0 0x304>;
-+				reg-names = "aiu", "audin";
-+				status = "disabled";
-+
-+				aiu_i2s_dma: aiu_i2s_dma {
-+					#sound-dai-cells = <0>;
-+					compatible = "amlogic,meson-aiu-i2s-dma";
-+					interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
-+					status = "disabled";
-+				};
-+
-+				i2s_dai: i2s_dai {
-+					#sound-dai-cells = <0>;
-+					compatible = "amlogic,meson-i2s-dai";
-+					status = "disabled";
-+				};
-+
-+			};
-+
- 			uart_A: serial@84c0 {
- 				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
- 				reg = <0x0 0x84c0 0x0 0x14>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-index 68ea67a..9d2fb46 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-@@ -691,6 +691,29 @@
- 	};
- };
- 
-+&audio {
-+	clocks = <&clkc CLKID_AIU>,
-+		 <&clkc CLKID_AIU_GLUE>,
-+		 <&clkc CLKID_I2S_SPDIF>;
-+	clock-names = "aiu_top", "aiu_glue", "audin";
-+	resets = <&reset RESET_AIU>,
-+		 <&reset RESET_AUDIN>;
-+	reset-names = "aiu", "audin";
-+};
-+
-+&aiu_i2s_dma {
-+	clocks = <&clkc CLKID_I2S_OUT>;
-+	clock-names = "fast";
-+};
-+
-+&i2s_dai {
-+	clocks = <&clkc CLKID_I2S_OUT>,
-+		 <&clkc CLKID_MIXER_IFACE>,
-+		 <&clkc CLKID_AOCLK_GATE>,
-+		 <&clkc CLKID_CTS_AMCLK>;
-+	clock-names = "fast", "iface", "bclks", "mclk";
-+};
-+
- &saradc {
- 	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
- 	clocks = <&xtal>,
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0029-ARM64-dts-meson-gxl-add-sound-dai-cells-to-HDMI-node.patch

@@ -1,26 +0,0 @@
-From 071f66d1e34243f37f52e09dca13b50e8215a7ce Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Wed, 20 Sep 2017 18:01:26 +0200
-Subject: [PATCH 29/39] ARM64: dts: meson-gxl: add sound-dai-cells to HDMI node
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-index 9d2fb46..4a1bd89 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-@@ -294,6 +294,7 @@
- 		 <&clkc CLKID_CLK81>,
- 		 <&clkc CLKID_GCLK_VENCI_INT0>;
- 	clock-names = "isfr", "iahb", "venci";
-+	#sound-dai-cells = <0>;
- };
- 
- &hiubus {
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0030-ARM64-dts-meson-gxl-Take-eMMC-data-strobe-out-of-eMM.patch

@@ -1,228 +0,0 @@
-From 29e058408d62384dc3de4e0b63433d7dfdee068b Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 28 Aug 2017 12:01:09 +0200
-Subject: [PATCH 30/39] ARM64: dts: meson-gxl: Take eMMC data strobe out of
- eMMC pins
-
-Since the Data Strobe pin is optional, take it out of the default
-eMMC pins and add a separate entry.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi            |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts           |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts         |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts            |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi               |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi           |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi                    | 10 ++++++++--
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts   |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts    |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi          |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi                     | 10 ++++++++--
- arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts            |  2 +-
- arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts             |  2 +-
- 14 files changed, 28 insertions(+), 16 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-index 7ce9a62..7f59f30 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-@@ -213,7 +213,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
-index 4b17a76..a42c8f4 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
-@@ -302,7 +302,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "disabled";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
-index 38dfdde..9a77323 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
-@@ -272,7 +272,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-index c3a7b7f..4221e1f 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-@@ -271,7 +271,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
-index 23c08c3..932158a 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
-@@ -242,7 +242,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
-index f2bc6de..1fe8e24 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
-@@ -199,7 +199,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-index 7d38d55..ef12d67 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-@@ -390,8 +390,14 @@
- 			mux {
- 				groups = "emmc_nand_d07",
- 				       "emmc_cmd",
--				       "emmc_clk",
--				       "emmc_ds";
-+				       "emmc_clk";
-+				function = "emmc";
-+			};
-+		};
-+
-+		emmc_ds_pins: emmc-ds {
-+			mux {
-+				groups = "emmc_ds";
- 				function = "emmc";
- 			};
- 		};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
-index 6f2cd8e..5eaafa1 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
-@@ -141,7 +141,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-index 4035891..942fd70 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-@@ -221,7 +221,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-index 6338e6c..0fdebcc 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-@@ -229,7 +229,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-index 7a1c20e..0a2be82 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-@@ -135,7 +135,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-index 4a1bd89..02b52b6 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-@@ -343,8 +343,14 @@
- 			mux {
- 				groups = "emmc_nand_d07",
- 				       "emmc_cmd",
--				       "emmc_clk",
--				       "emmc_ds";
-+				       "emmc_clk";
-+				function = "emmc";
-+			};
-+		};
-+
-+		emmc_ds_pins: emmc-ds {
-+			mux {
-+				groups = "emmc_ds";
- 				function = "emmc";
- 			};
- 		};
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-index cfde246..e70b5e2 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-@@ -193,7 +193,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-1 = <&emmc_clk_gate_pins>;
- 	pinctrl-names = "default", "clk-gate";
- 
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
-index 9837a48..9593a28 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
-@@ -216,7 +216,7 @@
- /* eMMC */
- &sd_emmc_c {
- 	status = "okay";
--	pinctrl-0 = <&emmc_pins>;
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- 	pinctrl-names = "default";
- 
- 	bus-width = <8>;
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0031-ARM64-dts-meson-gx-add-VPU-power-domain.patch

@@ -1,165 +0,0 @@
-From 107e323a199087cfb84c22b31d769f0b2e623e4a Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Fri, 13 Oct 2017 14:47:23 +0200
-Subject: [PATCH 31/39] ARM64: dts: meson-gx: add VPU power domain
-
-This patch adds support for the VPU Power Domain nodes, and attaches the
-VPU power domain to the VPU node.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gx.dtsi   | 11 ++++++++
- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 +++++++++++++++++++++++++++++
- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 43 +++++++++++++++++++++++++++++
- 3 files changed, 97 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-index ff27ce0..ace0e4b 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-@@ -393,6 +393,12 @@
- 				compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
- 				reg =  <0x0 0x0 0x0 0x100>;
- 
-+				pwrc_vpu: power-controller-vpu {
-+					compatible = "amlogic,meson-gx-pwrc-vpu";
-+					#power-domain-cells = <0>;
-+					amlogic,hhi-sysctrl = <&sysctrl>;
-+				};
-+
- 				clkc_AO: clock-controller {
- 					compatible = "amlogic,meson-gx-aoclkc";
- 					#clock-cells = <1>;
-@@ -470,6 +476,11 @@
- 			#size-cells = <2>;
- 			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
- 
-+			sysctrl: system-controller@0 {
-+				compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
-+				reg = <0 0 0 0x400>;
-+			};
-+
- 			mailbox: mailbox@404 {
- 				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
- 				reg = <0 0x404 0 0x4c>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-index ef12d67..b5b6b33 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-@@ -692,6 +692,48 @@
- 	};
- };
- 
-+&pwrc_vpu {
-+	resets = <&reset RESET_VIU>,
-+		 <&reset RESET_VENC>,
-+		 <&reset RESET_VCBUS>,
-+		 <&reset RESET_BT656>,
-+		 <&reset RESET_DVIN_RESET>,
-+		 <&reset RESET_RDMA>,
-+		 <&reset RESET_VENCI>,
-+		 <&reset RESET_VENCP>,
-+		 <&reset RESET_VDAC>,
-+		 <&reset RESET_VDI6>,
-+		 <&reset RESET_VENCL>,
-+		 <&reset RESET_VID_LOCK>;
-+	clocks = <&clkc CLKID_VPU>,
-+	         <&clkc CLKID_VAPB>;
-+	clock-names = "vpu", "vapb";
-+	/*
-+	 * VPU clocking is provided by two identical clock paths
-+	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
-+	 * free mux to safely change frequency while running.
-+	 * Same for VAPB but with a final gate after the glitch free mux.
-+	 */
-+	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
-+			  <&clkc CLKID_VPU_0>,
-+			  <&clkc CLKID_VPU>, /* Glitch free mux */
-+			  <&clkc CLKID_VAPB_0_SEL>,
-+			  <&clkc CLKID_VAPB_0>,
-+			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
-+	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
-+				 <0>, /* Do Nothing */
-+				 <&clkc CLKID_VPU_0>,
-+				 <&clkc CLKID_FCLK_DIV4>,
-+				 <0>, /* Do Nothing */
-+				 <&clkc CLKID_VAPB_0>;
-+	assigned-clock-rates = <0>, /* Do Nothing */
-+			       <666666666>,
-+			       <0>, /* Do Nothing */
-+			       <0>, /* Do Nothing */
-+			       <250000000>,
-+			       <0>; /* Do Nothing */
-+};
-+
- &saradc {
- 	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
- 	clocks = <&xtal>,
-@@ -761,4 +803,5 @@
- 
- &vpu {
- 	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
-+	power-domains = <&pwrc_vpu>;
- };
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-index 02b52b6..d5c8952 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
-@@ -721,6 +721,48 @@
- 	clock-names = "fast", "iface", "bclks", "mclk";
- };
- 
-+&pwrc_vpu {
-+	resets = <&reset RESET_VIU>,
-+		 <&reset RESET_VENC>,
-+		 <&reset RESET_VCBUS>,
-+		 <&reset RESET_BT656>,
-+		 <&reset RESET_DVIN_RESET>,
-+		 <&reset RESET_RDMA>,
-+		 <&reset RESET_VENCI>,
-+		 <&reset RESET_VENCP>,
-+		 <&reset RESET_VDAC>,
-+		 <&reset RESET_VDI6>,
-+		 <&reset RESET_VENCL>,
-+		 <&reset RESET_VID_LOCK>;
-+	clocks = <&clkc CLKID_VPU>,
-+	         <&clkc CLKID_VAPB>;
-+	clock-names = "vpu", "vapb";
-+	/*
-+	 * VPU clocking is provided by two identical clock paths
-+	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
-+	 * free mux to safely change frequency while running.
-+	 * Same for VAPB but with a final gate after the glitch free mux.
-+	 */
-+	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
-+			  <&clkc CLKID_VPU_0>,
-+			  <&clkc CLKID_VPU>, /* Glitch free mux */
-+			  <&clkc CLKID_VAPB_0_SEL>,
-+			  <&clkc CLKID_VAPB_0>,
-+			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
-+	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
-+				 <0>, /* Do Nothing */
-+				 <&clkc CLKID_VPU_0>,
-+				 <&clkc CLKID_FCLK_DIV4>,
-+				 <0>, /* Do Nothing */
-+				 <&clkc CLKID_VAPB_0>;
-+	assigned-clock-rates = <0>, /* Do Nothing */
-+			       <666666666>,
-+			       <0>, /* Do Nothing */
-+			       <0>, /* Do Nothing */
-+			       <250000000>,
-+			       <0>; /* Do Nothing */
-+};
-+
- &saradc {
- 	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
- 	clocks = <&xtal>,
-@@ -790,4 +832,5 @@
- 
- &vpu {
- 	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
-+	power-domains = <&pwrc_vpu>;
- };
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0032-ARM64-dts-meson-gx-Add-HDMI_5V-regulator-on-selected.patch

@@ -1,173 +0,0 @@
-From 07b467abf6efad25e12ad4c09a008e9f1594e39d Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 16 Oct 2017 15:33:30 +0200
-Subject: [PATCH 32/39] ARM64: dts: meson-gx: Add HDMI_5V regulator on selected
- boards
-
-On reference boards and derivatives, the HDMI Logic is powered by an external
-5V regulator.
-This regulator was set by the Vendor U-Boot, add the regulator and phandle
-property to the HDMI node.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi          | 12 ++++++++++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts         |  1 +
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts   |  1 +
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 12 ++++++++++++
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts         |  1 +
- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi        | 11 +++++++++++
- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts        | 12 ++++++++++++
- 7 files changed, 50 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-index 7f59f30..979abaf 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-@@ -59,6 +59,17 @@
- 		reg = <0x0 0x0 0x0 0x80000000>;
- 	};
- 
-+	hdmi_5v: regulator-hdmi-5v {
-+		compatible = "regulator-fixed";
-+
-+		regulator-name = "HDMI_5V";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+
-+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
-+		enable-active-high;
-+	};
-+
- 	vddio_boot: regulator-vddio_boot {
- 		compatible = "regulator-fixed";
- 		regulator-name = "VDDIO_BOOT";
-@@ -142,6 +153,7 @@
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- 	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
- };
- 
- &hdmi_tx_tmds_port {
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
-index 6827f23..8bc540e 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
-@@ -135,6 +135,7 @@
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- 	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
- };
- 
- &hdmi_tx_tmds_port {
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-index 89a5fd9..f7b37de 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-@@ -78,6 +78,7 @@
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- 	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
- };
- 
- &hdmi_tx_tmds_port {
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-index 942fd70..0c4ed4e 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-@@ -72,6 +72,17 @@
- 		reg = <0x0 0x0 0x0 0x80000000>;
- 	};
- 
-+	hdmi_5v: regulator-hdmi-5v {
-+		compatible = "regulator-fixed";
-+
-+		regulator-name = "HDMI_5V";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+
-+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
-+		enable-active-high;
-+	};
-+
- 	vcc_3v3: regulator-vcc_3v3 {
- 		compatible = "regulator-fixed";
- 		regulator-name = "VCC_3V3";
-@@ -131,6 +142,7 @@
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- 	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
- };
- 
- &hdmi_tx_tmds_port {
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
-index 6e2bf85..4f6b1c9 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
-@@ -88,6 +88,7 @@
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- 	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
- };
- 
- &hdmi_tx_tmds_port {
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-index 0a2be82..1a5136a 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
-@@ -28,6 +28,17 @@
- 		reg = <0x0 0x0 0x0 0x80000000>;
- 	};
- 
-+	hdmi_5v: regulator-hdmi-5v {
-+		compatible = "regulator-fixed";
-+
-+		regulator-name = "HDMI_5V";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+
-+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
-+		enable-active-high;
-+	};
-+
- 	vddio_boot: regulator-vddio_boot {
- 		compatible = "regulator-fixed";
- 		regulator-name = "VDDIO_BOOT";
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-index 103575a..4537a81 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-@@ -153,6 +153,17 @@
- 		};
- 	};
- 
-+	hdmi_5v: regulator-hdmi-5v {
-+		compatible = "regulator-fixed";
-+
-+		regulator-name = "HDMI_5V";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+
-+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
-+		enable-active-high;
-+	};
-+
- 	vcc_3v3: regulator-vcc_3v3 {
- 		compatible = "regulator-fixed";
- 		regulator-name = "VCC_3V3";
-@@ -239,6 +250,7 @@
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- 	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
- };
- 
- &hdmi_tx_tmds_port {
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0033-ARM64-dts-meson-gx-grow-reset-controller-memory-zone.patch

@@ -1,29 +0,0 @@
-From 7c3d7dee433538e1450564582da535cac44a2361 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 16 Oct 2017 17:00:59 +0200
-Subject: [PATCH 33/39] ARM64: dts: meson-gx: grow reset controller memory zone
-
-Now the Amlogic Meson GX SoCs datasheet documents all the Reset registers,
-grow the memory in the node to allow usage of the level registers.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-index ace0e4b..2e0ee17 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
-@@ -220,7 +220,7 @@
- 
- 			reset: reset-controller@4404 {
- 				compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
--				reg = <0x0 0x04404 0x0 0x20>;
-+				reg = <0x0 0x04404 0x0 0x9c>;
- 				#reset-cells = <1>;
- 			};
- 
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0034-ARM64-dts-odroid-c2-Add-HDMI-and-CEC-Nodes.patch

@@ -1,64 +0,0 @@
-From a0cd1597b6b505c8d72406d31cf408933b2993e9 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Mon, 16 Oct 2017 17:00:26 +0200
-Subject: [PATCH 34/39] ARM64: dts: odroid-c2: Add HDMI and CEC Nodes
-
-Now the VPU Power Domain has been fixed while boothing from Mainline U-Boot,
-VPU and HDMI nodes can finally be added to the Odroid-C2 DTS.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 30 ++++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-index 4221e1f..dc3d1ba 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-@@ -135,6 +135,24 @@
- 		compatible = "mmc-pwrseq-emmc";
- 		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- 	};
-+
-+	hdmi-connector {
-+		compatible = "hdmi-connector";
-+		type = "a";
-+
-+		port {
-+			hdmi_connector_in: endpoint {
-+				remote-endpoint = <&hdmi_tx_tmds_out>;
-+			};
-+		};
-+	};
-+};
-+
-+&cec_AO {
-+	status = "okay";
-+	pinctrl-0 = <&ao_cec_pins>;
-+	pinctrl-names = "default";
-+	hdmi-phandle = <&hdmi_tx>;
- };
- 
- &ethmac {
-@@ -177,6 +195,18 @@
- 	};
- };
- 
-+&hdmi_tx {
-+	status = "okay";
-+	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&hdmi_tx_tmds_port {
-+	hdmi_tx_tmds_out: endpoint {
-+		remote-endpoint = <&hdmi_connector_in>;
-+	};
-+};
-+
- &i2c_A {
- 	status = "okay";
- 	pinctrl-0 = <&i2c_a_pins>;
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0035-ARM64-dts-meson-activate-hdmi-audio-HDMI-enabled-boa.patch

@@ -1,637 +0,0 @@
-From bc1416cbeb6fb588e8573c9904b691259d173093 Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Wed, 20 Sep 2017 18:10:08 +0200
-Subject: [PATCH 35/39] ARM64: dts: meson: activate hdmi audio HDMI enabled
- boards
-
-This patch activate audio over HDMI on selected boards
-
-Please note that this audio support is based on WIP changes
-This should be considered as preview and it does not reflect
-the audio I expect to see merged
-
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- .../arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 37 +++++++++++++++++++++
- .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts    | 38 ++++++++++++++++++++++
- .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 37 +++++++++++++++++++++
- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi   | 37 +++++++++++++++++++++
- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts    | 37 +++++++++++++++++++++
- .../dts/amlogic/meson-gxl-s905x-khadas-vim.dts     | 37 +++++++++++++++++++++
- .../dts/amlogic/meson-gxl-s905x-libretech-cc.dts   | 37 +++++++++++++++++++++
- .../dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts    | 37 +++++++++++++++++++++
- .../boot/dts/amlogic/meson-gxl-s905x-p212.dts      | 37 +++++++++++++++++++++
- .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts     | 37 +++++++++++++++++++++
- .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 37 +++++++++++++++++++++
- 11 files changed, 408 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-index 979abaf..91b7ac8 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
-@@ -130,6 +130,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -139,6 +164,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
-index 9a77323..2357a38 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
-@@ -143,6 +143,31 @@
- 		clock-names = "ext_clock";
- 	};
- 
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
-+
- 	cvbs-connector {
- 		compatible = "composite-video-connector";
- 
-@@ -178,6 +203,19 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &ethmac {
- 	status = "okay";
- 	pinctrl-0 = <&eth_rmii_pins>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-index dc3d1ba..4e0b3c7 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
-@@ -146,6 +146,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -155,6 +180,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &ethmac {
- 	status = "okay";
- 	pinctrl-0 = <&eth_rgmii_pins>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
-index 932158a..c9d4870 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
-@@ -149,6 +149,31 @@
- 			};
- 		};
- 	};
-+	
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -158,6 +183,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
-index f7144fd..58a0f51 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
-@@ -106,6 +106,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -115,6 +140,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-index f7b37de..ce92ca5 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
-@@ -65,6 +65,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -74,6 +99,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &hdmi_tx {
- 	status = "okay";
- 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-index 0c4ed4e..29d8e01 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
-@@ -83,6 +83,31 @@
- 		enable-active-high;
- 	};
- 
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
-+
- 	vcc_3v3: regulator-vcc_3v3 {
- 		compatible = "regulator-fixed";
- 		regulator-name = "VCC_3V3";
-@@ -122,6 +147,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-index 0fdebcc..dcb571a 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
-@@ -138,6 +138,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -147,6 +172,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
-index 4f6b1c9..f23f148 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
-@@ -69,6 +69,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -78,6 +103,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-index 4537a81..aed2a54 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
-@@ -88,6 +88,31 @@
- 		};
- 	};
- 
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
-+
- 	pwmleds {
- 		compatible = "pwm-leds";
- 
-@@ -207,6 +232,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cpu0 {
- 	cooling-min-level = <0>;
- 	cooling-max-level = <6>;
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-index e70b5e2..8444f79 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
-@@ -111,6 +111,31 @@
- 			};
- 		};
- 	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "meson-gx-preview";
-+		status = "okay";
-+
-+		simple-audio-card,dai-link@0 {
-+			/* HDMI Output */
-+			format = "i2s";
-+			mclk-fs = <256>;
-+			bitclock-master =  <&i2s_dai>;
-+			frame-master = <&i2s_dai>;
-+			plat {
-+				sound-dai = <&aiu_i2s_dma>;
-+			};
-+
-+			cpu {
-+				sound-dai = <&i2s_dai>;
-+			};
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
- };
- 
- &cec_AO {
-@@ -120,6 +145,18 @@
- 	hdmi-phandle = <&hdmi_tx>;
- };
- 
-+&audio {
-+	status = "okay";
-+};
-+
-+&aiu_i2s_dma {
-+	status = "okay";
-+};
-+
-+&i2s_dai {
-+	status = "okay";
-+};
-+
- &cvbs_vdac_port {
- 	cvbs_vdac_out: endpoint {
- 		remote-endpoint = <&cvbs_connector_in>;
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0036-net-phy-meson-gxl-detect-LPA-corruption.patch

@@ -1,132 +0,0 @@
-From 9afb9faf483008a1d16202818d895099e5c932bb Mon Sep 17 00:00:00 2001
-From: Jerome Brunet <jbrunet@baylibre.com>
-Date: Fri, 8 Dec 2017 12:08:11 +0100
-Subject: [PATCH 36/39] net: phy: meson-gxl: detect LPA corruption
-
-The purpose of this change is to fix the incorrect detection of the link
-partner (LP) advertised capabilities which sometimes happens with this PHY
-(roughly 1 time in a dozen)
-
-This issue may cause the link to be negotiated at 10Mbps/Full or
-10Mbps/Half when 100MBps/Full is actually possible. In some case, the link
-is even completely broken and no communication is possible.
-
-To detect the corruption, we must look for a magic undocumented bit in the
-WOL bank (hint given by the SoC vendor kernel) but this is not enough to
-cover all cases. We also have to look at the LPA ack. If the LP supports
-Aneg but did not ack our base code when aneg is completed, we assume
-something went wrong.
-
-The detection of a corrupted LPA triggers a restart of the aneg process.
-This solves the problem but may take up to 6 retries to complete.
-
-Fixes: 7334b3e47aee ("net: phy: Add Meson GXL Internal PHY driver")
-Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/net/phy/meson-gxl.c | 74 ++++++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 73 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
-index 7ddb709..b21f607 100644
---- a/drivers/net/phy/meson-gxl.c
-+++ b/drivers/net/phy/meson-gxl.c
-@@ -22,6 +22,7 @@
- #include <linux/ethtool.h>
- #include <linux/phy.h>
- #include <linux/netdevice.h>
-+#include <linux/bitfield.h>
- 
- static int meson_gxl_config_init(struct phy_device *phydev)
- {
-@@ -76,6 +77,77 @@ static int meson_gxl_config_init(struct phy_device *phydev)
- 	return 0;
- }
- 
-+/* This function is provided to cope with the possible failures of this phy
-+ * during aneg process. When aneg fails, the PHY reports that aneg is done
-+ * but the value found in MII_LPA is wrong:
-+ *  - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
-+ *    the link partner (LP) supports aneg but the LP never acked our base
-+ *    code word, it is likely that we never sent it to begin with.
-+ *  - Late failures: MII_LPA is filled with a value which seems to make sense
-+ *    but it actually is not what the LP is advertising. It seems that we
-+ *    can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
-+ *    If this particular bit is not set when aneg is reported being done,
-+ *    it means MII_LPA is likely to be wrong.
-+ *
-+ * In both case, forcing a restart of the aneg process solve the problem.
-+ * When this failure happens, the first retry is usually successful but,
-+ * in some cases, it may take up to 6 retries to get a decent result
-+ */
-+int meson_gxl_read_status(struct phy_device *phydev)
-+{
-+	int ret, wol, lpa, exp;
-+
-+	if (phydev->autoneg == AUTONEG_ENABLE) {
-+		ret = genphy_aneg_done(phydev);
-+		if (ret < 0)
-+			return ret;
-+		else if (!ret)
-+			goto read_status_continue;
-+
-+		/* Need to access WOL bank, make sure the access is open */
-+		ret = phy_write(phydev, 0x14, 0x0000);
-+		if (ret)
-+			return ret;
-+		ret = phy_write(phydev, 0x14, 0x0400);
-+		if (ret)
-+			return ret;
-+		ret = phy_write(phydev, 0x14, 0x0000);
-+		if (ret)
-+			return ret;
-+		ret = phy_write(phydev, 0x14, 0x0400);
-+		if (ret)
-+			return ret;
-+
-+		/* Request LPI_STATUS WOL register */
-+		ret = phy_write(phydev, 0x14, 0x8D80);
-+		if (ret)
-+			return ret;
-+
-+		/* Read LPI_STATUS value */
-+		wol = phy_read(phydev, 0x15);
-+		if (wol < 0)
-+			return wol;
-+
-+		lpa = phy_read(phydev, MII_LPA);
-+		if (lpa < 0)
-+			return lpa;
-+
-+		exp = phy_read(phydev, MII_EXPANSION);
-+		if (exp < 0)
-+			return exp;
-+
-+		if (!(wol & BIT(12)) ||
-+		    ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
-+			/* Looks like aneg failed after all */
-+			phydev_dbg(phydev, "LPA corruption - aneg restart\n");
-+			return genphy_restart_aneg(phydev);
-+		}
-+	}
-+
-+read_status_continue:
-+	return genphy_read_status(phydev);
-+}
-+
- static struct phy_driver meson_gxl_phy[] = {
- 	{
- 		.phy_id		= 0x01814400,
-@@ -86,7 +158,7 @@ static struct phy_driver meson_gxl_phy[] = {
- 		.config_init	= meson_gxl_config_init,
- 		.config_aneg	= genphy_config_aneg,
- 		.aneg_done      = genphy_aneg_done,
--		.read_status	= genphy_read_status,
-+		.read_status	= meson_gxl_read_status,
- 		.suspend        = genphy_suspend,
- 		.resume         = genphy_resume,
- 	},
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0037-drm-meson-fix-vsync-buffer-update.patch

@@ -1,71 +0,0 @@
-From 61ceaf782220a596ac845483d00d50752f7c6e14 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Thu, 15 Feb 2018 10:38:47 +0100
-Subject: [PATCH 37/39] drm/meson: fix vsync buffer update
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/meson/meson_crtc.c  | 6 ++++++
- drivers/gpu/drm/meson/meson_drv.h   | 3 +++
- drivers/gpu/drm/meson/meson_plane.c | 7 +++----
- 3 files changed, 12 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
-index 5155f01..0552020 100644
---- a/drivers/gpu/drm/meson/meson_crtc.c
-+++ b/drivers/gpu/drm/meson/meson_crtc.c
-@@ -36,6 +36,7 @@
- #include "meson_venc.h"
- #include "meson_vpp.h"
- #include "meson_viu.h"
-+#include "meson_canvas.h"
- #include "meson_registers.h"
- 
- /* CRTC definition */
-@@ -192,6 +193,11 @@ void meson_crtc_irq(struct meson_drm *priv)
- 		} else
- 			meson_vpp_disable_interlace_vscaler_osd1(priv);
- 
-+		meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
-+			   priv->viu.osd1_addr, priv->viu.osd1_stride,
-+			   priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
-+			   MESON_CANVAS_BLKMODE_LINEAR);
-+
- 		/* Enable OSD1 */
- 		writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
- 				    priv->io_base + _REG(VPP_MISC));
-diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
-index 5e8b392..8450d6ac 100644
---- a/drivers/gpu/drm/meson/meson_drv.h
-+++ b/drivers/gpu/drm/meson/meson_drv.h
-@@ -43,6 +43,9 @@ struct meson_drm {
- 		bool osd1_commit;
- 		uint32_t osd1_ctrl_stat;
- 		uint32_t osd1_blk0_cfg[5];
-+		uint32_t osd1_addr;
-+		uint32_t osd1_stride;
-+		uint32_t osd1_height;
- 	} viu;
- 
- 	struct {
-diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
-index 17e96fa..0b6011b 100644
---- a/drivers/gpu/drm/meson/meson_plane.c
-+++ b/drivers/gpu/drm/meson/meson_plane.c
-@@ -164,10 +164,9 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
- 	/* Update Canvas with buffer address */
- 	gem = drm_fb_cma_get_gem_obj(fb, 0);
- 
--	meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
--			   gem->paddr, fb->pitches[0],
--			   fb->height, MESON_CANVAS_WRAP_NONE,
--			   MESON_CANVAS_BLKMODE_LINEAR);
-+	priv->viu.osd1_addr = gem->paddr;
-+	priv->viu.osd1_stride = fb->pitches[0];
-+	priv->viu.osd1_height = fb->height;
- 
- 	spin_unlock_irqrestore(&priv->drm->event_lock, flags);
- }
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0038-ARM64-dts-meson-bump-mali450-clk-to-744MHz.patch

@@ -1,66 +0,0 @@
-From 63ffa5db0046106f6c3b8687e200e17599e14b9f Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Fri, 23 Feb 2018 11:18:11 +0100
-Subject: [PATCH 38/39] ARM64: dts: meson: bump mali450 clk to 744MHz
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi     | 11 +++++++----
- arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi | 11 +++++++----
- 2 files changed, 14 insertions(+), 8 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-index b5b6b33..d00a9f2 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
-@@ -288,14 +288,17 @@
- 		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
- 		 * free mux to safely change frequency while running.
- 		 */
--		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
-+		assigned-clocks = <&clkc CLKID_GP0_PLL>,
-+				  <&clkc CLKID_MALI_0_SEL>,
- 				  <&clkc CLKID_MALI_0>,
- 				  <&clkc CLKID_MALI>; /* Glitch free mux */
--		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
-+		assigned-clock-parents = <0>, /* Do Nothing */
-+					 <&clkc CLKID_GP0_PLL>,
- 					 <0>, /* Do Nothing */
- 					 <&clkc CLKID_MALI_0>;
--		assigned-clock-rates = <0>, /* Do Nothing */
--				       <666666666>,
-+		assigned-clock-rates = <744000000>,
-+				       <0>, /* Do Nothing */
-+				       <744000000>,
- 				       <0>; /* Do Nothing */
- 	};
- };
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
-index f06cc234..972df67 100644
---- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
-@@ -30,14 +30,17 @@
- 		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
- 		 * free mux to safely change frequency while running.
- 		 */
--		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
-+		assigned-clocks = <&clkc CLKID_GP0_PLL>,
-+				  <&clkc CLKID_MALI_0_SEL>,
- 				  <&clkc CLKID_MALI_0>,
- 				  <&clkc CLKID_MALI>; /* Glitch free mux */
--		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
-+		assigned-clock-parents = <0>, /* Do Nothing */
-+					 <&clkc CLKID_GP0_PLL>,
- 					 <0>, /* Do Nothing */
- 					 <&clkc CLKID_MALI_0>;
--		assigned-clock-rates = <0>, /* Do Nothing */
--				       <666666666>,
-+		assigned-clock-rates = <744000000>,
-+				       <0>, /* Do Nothing */
-+				       <744000000>,
- 				       <0>; /* Do Nothing */
- 	};
- };
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0039-drm-meson-Add-support-for-DMT-modes-on-HDMI.patch

@@ -1,773 +0,0 @@
-From 8da289631087c90a3b644cbdd124bee7f7b348f3 Mon Sep 17 00:00:00 2001
-From: Neil Armstrong <narmstrong@baylibre.com>
-Date: Thu, 8 Mar 2018 16:35:34 +0100
-Subject: [PATCH 39/39] drm/meson: Add support for DMT modes on HDMI
-
-This patch adds support for DMT display modes over HDMI.
-The modes timings configurations are from the Amlogic Vendor linux tree
-and tested over multiples monitors.
-Previously only a selected number of CEA modes were supported.
-
-Only these following modes are supported with these changes:
-- 640x480@60Hz
-- 800x600@60Hz
-- 1024x768@60Hz
-- 1152x864@75Hz
-- 1280x1024@60Hz
-- 1600x1200@60Hz
-- 1920x1080@60Hz
-
-The associated code to handle the clock rates is also added.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/meson/meson_dw_hdmi.c |  22 +--
- drivers/gpu/drm/meson/meson_vclk.c    | 219 ++++++++++++++++++++-
- drivers/gpu/drm/meson/meson_venc.c    | 347 +++++++++++++++++++++++++++++++++-
- drivers/gpu/drm/meson/meson_venc.h    |   1 +
- 4 files changed, 570 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-index 17de3af..9d70ed6 100644
---- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
-+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-@@ -537,7 +537,6 @@ static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id)
- 	return IRQ_HANDLED;
- }
- 
--/* TOFIX Enable support for non-vic modes */
- static enum drm_mode_status
- dw_hdmi_mode_valid(struct drm_connector *connector,
- 		   const struct drm_display_mode *mode)
-@@ -554,12 +553,12 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
- 		mode->vdisplay, mode->vsync_start,
- 		mode->vsync_end, mode->vtotal, mode->type, mode->flags);
- 
--	/* For now, only accept VIC modes */
--	if (!vic)
--		return MODE_BAD;
--
--	/* For now, filter by supported VIC modes */
--	if (!meson_venc_hdmi_supported_vic(vic))
-+	/* Check against non-VIC supported modes */
-+	if (!vic) {
-+		if (!meson_venc_hdmi_supported_mode(mode))
-+			return MODE_BAD;
-+	/* Check against supported VIC modes */
-+	} else if (!meson_venc_hdmi_supported_vic(vic))
- 		return MODE_BAD;
- 
- 	vclk_freq = mode->clock;
-@@ -585,9 +584,14 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
- 
- 	/* Finally filter by configurable vclk frequencies */
- 	switch (vclk_freq) {
-+	case 25175:
-+	case 40000:
- 	case 54000:
-+	case 65000:
- 	case 74250:
-+	case 108000:
- 	case 148500:
-+	case 162000:
- 	case 297000:
- 	case 594000:
- 		return MODE_OK;
-@@ -652,10 +656,6 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder,
- 	DRM_DEBUG_DRIVER("%d:\"%s\" vic %d\n",
- 			 mode->base.id, mode->name, vic);
- 
--	/* Should have been filtered */
--	if (!vic)
--		return;
--
- 	/* VENC + VENC-DVI Mode setup */
- 	meson_venc_hdmi_mode_set(priv, vic, mode);
- 
-diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
-index 4767704..f051122 100644
---- a/drivers/gpu/drm/meson/meson_vclk.c
-+++ b/drivers/gpu/drm/meson/meson_vclk.c
-@@ -328,14 +328,24 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
- #define MESON_VCLK_HDMI_DDR_54000	2
- /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
- #define MESON_VCLK_HDMI_DDR_148500	3
-+/* 4028 /4 /4 /1 /5 /2  => /1 /1 */
-+#define MESON_VCLK_HDMI_25175		4
-+/* 3200 /4 /2 /1 /5 /2  => /1 /1 */
-+#define MESON_VCLK_HDMI_40000		5
-+/* 5200 /4 /2 /1 /5 /2  => /1 /1 */
-+#define MESON_VCLK_HDMI_65000		6
- /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
--#define MESON_VCLK_HDMI_74250		4
-+#define MESON_VCLK_HDMI_74250		7
-+/* 4320 /4 /1 /1 /5 /2  => /1 /1 */
-+#define MESON_VCLK_HDMI_108000		8
- /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
--#define MESON_VCLK_HDMI_148500		5
-+#define MESON_VCLK_HDMI_148500		9
-+/* 3240 /2 /1 /1 /5 /2  => /1 /1 */
-+#define MESON_VCLK_HDMI_162000		10
- /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
--#define MESON_VCLK_HDMI_297000		6
-+#define MESON_VCLK_HDMI_297000		11
- /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
--#define MESON_VCLK_HDMI_594000		7
-+#define MESON_VCLK_HDMI_594000		12
- 
- struct meson_vclk_params {
- 	unsigned int pll_base_freq;
-@@ -401,6 +411,46 @@ struct meson_vclk_params {
- 		.vid_pll_div = VID_PLL_DIV_5,
- 		.vclk_div = 1,
- 	},
-+	[MESON_VCLK_HDMI_25175] = {
-+		.pll_base_freq = 4028000,
-+		.pll_od1 = 4,
-+		.pll_od2 = 4,
-+		.pll_od3 = 1,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 2,
-+	},
-+	[MESON_VCLK_HDMI_40000] = {
-+		.pll_base_freq = 3200000,
-+		.pll_od1 = 4,
-+		.pll_od2 = 2,
-+		.pll_od3 = 1,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 2,
-+	},
-+	[MESON_VCLK_HDMI_65000] = {
-+		.pll_base_freq = 5200000,
-+		.pll_od1 = 4,
-+		.pll_od2 = 2,
-+		.pll_od3 = 1,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 2,
-+	},
-+	[MESON_VCLK_HDMI_108000] = {
-+		.pll_base_freq = 4320000,
-+		.pll_od1 = 4,
-+		.pll_od2 = 1,
-+		.pll_od3 = 1,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 2,
-+	},
-+	[MESON_VCLK_HDMI_162000] = {
-+		.pll_base_freq = 3240000,
-+		.pll_od1 = 2,
-+		.pll_od2 = 1,
-+		.pll_od3 = 1,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 2,
-+	},
- };
- 
- static inline unsigned int pll_od_to_reg(unsigned int od)
-@@ -451,6 +501,90 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
- 						0xFFFF,  0x4e00);
- 			break;
- 
-+		case 3200000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000242);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
-+
-+			/* unreset */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-+						BIT(28), 0);
-+
-+			/* Poll for lock bit */
-+			regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
-+					val, (val & HDMI_PLL_LOCK), 10, 0);
-+
-+			/* div_frac */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-+						0xFFFF,  0x4aab);
-+			break;
-+
-+		case 3240000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000243);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
-+
-+			/* unreset */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-+						BIT(28), 0);
-+
-+			/* Poll for lock bit */
-+			regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
-+					val, (val & HDMI_PLL_LOCK), 10, 0);
-+
-+			/* div_frac */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-+						0xFFFF,  0x4800);
-+			break;
-+
-+		case 3865000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000250);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
-+
-+			/* unreset */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-+						BIT(28), 0);
-+
-+			/* Poll for lock bit */
-+			regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
-+					val, (val & HDMI_PLL_LOCK), 10, 0);
-+
-+			/* div_frac */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-+						0xFFFF,  0x4855);
-+			break;
-+
-+		case 4028000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000253);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
-+
-+			/* unreset */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-+						BIT(28), 0);
-+
-+			/* Poll for lock bit */
-+			regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
-+					val, (val & HDMI_PLL_LOCK), 10, 0);
-+
-+			/* div_frac */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
-+						0xFFFF,  0x4eab);
-+			break;
-+
- 		case 4320000:
- 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800025a);
- 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
-@@ -485,6 +619,23 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
- 			regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
- 					val, (val & HDMI_PLL_LOCK), 10, 0);
- 			break;
-+
-+		case 5200000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800026c);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x135c5091);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
-+
-+			/* unreset */
-+			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
-+						BIT(28), 0);
-+
-+			/* Poll for lock bit */
-+			regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
-+					val, (val & HDMI_PLL_LOCK), 10, 0);
-+			break;
- 		};
- 	} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
- 		   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
-@@ -498,6 +649,42 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
- 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
- 			break;
- 
-+		case 3200000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000285);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb155);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
-+			break;
-+
-+		case 3240000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000287);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
-+			break;
-+
-+		case 3865000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a1);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb02b);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
-+			break;
-+
-+		case 4028000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a7);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb355);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
-+			break;
-+
- 		case 4320000:
- 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002b4);
- 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000);
-@@ -516,6 +703,15 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
- 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
- 			break;
- 
-+		case 5200000:
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002d8);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb2ab);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
-+			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
-+			break;
-+
- 		};
- 
- 		/* Reset PLL */
-@@ -590,15 +786,30 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
- 		else
- 			freq = MESON_VCLK_HDMI_DDR_54000;
- 		break;
-+	case 25175:
-+		freq = MESON_VCLK_HDMI_25175;
-+		break;
-+	case 40000:
-+		freq = MESON_VCLK_HDMI_40000;
-+		break;
-+	case 65000:
-+		freq = MESON_VCLK_HDMI_65000;
-+		break;
- 	case 74250:
- 		freq = MESON_VCLK_HDMI_74250;
- 		break;
-+	case 108000:
-+		freq = MESON_VCLK_HDMI_108000;
-+		break;
- 	case 148500:
- 		if (dac_freq != 148500)
- 			freq = MESON_VCLK_HDMI_DDR_148500;
- 		else
- 			freq = MESON_VCLK_HDMI_148500;
- 		break;
-+	case 162000:
-+		freq = MESON_VCLK_HDMI_162000;
-+		break;
- 	case 297000:
- 		freq = MESON_VCLK_HDMI_297000;
- 		break;
-diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
-index 9509017..6e27013 100644
---- a/drivers/gpu/drm/meson/meson_venc.c
-+++ b/drivers/gpu/drm/meson/meson_venc.c
-@@ -697,6 +697,314 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
- 	},
- };
- 
-+union meson_hdmi_venc_mode meson_hdmi_encp_mode_640x480_60 = {
-+	.encp = {
-+		.dvi_settings = 0x21,
-+		.video_mode = 0x4040,
-+		.video_mode_adv = 0x18,
-+		/* video_prog_mode */
-+		/* video_sync_mode */
-+		/* video_yc_dly */
-+		/* video_rgb_ctrl */
-+		/* video_filt_ctrl */
-+		/* video_ofld_voav_ofst */
-+		/* yfp1_htime */
-+		/* yfp2_htime */
-+		.max_pxcnt = 0x31f,
-+		/* hspuls_begin */
-+		/* hspuls_end */
-+		/* hspuls_switch */
-+		/* vspuls_begin */
-+		/* vspuls_end */
-+		/* vspuls_bline */
-+		/* vspuls_eline */
-+		.havon_begin = 0x90,
-+		.havon_end = 0x30f,
-+		.vavon_bline = 0x23,
-+		.vavon_eline = 0x202,
-+		/* eqpuls_begin */
-+		/* eqpuls_end */
-+		/* eqpuls_bline */
-+		/* eqpuls_eline */
-+		.hso_begin = 0,
-+		.hso_end = 0x60,
-+		.vso_begin = 0x1e,
-+		.vso_end = 0x32,
-+		.vso_bline = 0,
-+		.vso_eline = 2,
-+		.vso_eline_present = true,
-+		/* sy_val */
-+		/* sy2_val */
-+		.max_lncnt = 0x20c,
-+	},
-+};
-+
-+union meson_hdmi_venc_mode meson_hdmi_encp_mode_800x600_60 = {
-+	.encp = {
-+		.dvi_settings = 0x21,
-+		.video_mode = 0x4040,
-+		.video_mode_adv = 0x18,
-+		/* video_prog_mode */
-+		/* video_sync_mode */
-+		/* video_yc_dly */
-+		/* video_rgb_ctrl */
-+		/* video_filt_ctrl */
-+		/* video_ofld_voav_ofst */
-+		/* yfp1_htime */
-+		/* yfp2_htime */
-+		.max_pxcnt = 0x41f,
-+		/* hspuls_begin */
-+		/* hspuls_end */
-+		/* hspuls_switch */
-+		/* vspuls_begin */
-+		/* vspuls_end */
-+		/* vspuls_bline */
-+		/* vspuls_eline */
-+		.havon_begin = 0xD8,
-+		.havon_end = 0x3f7,
-+		.vavon_bline = 0x1b,
-+		.vavon_eline = 0x272,
-+		/* eqpuls_begin */
-+		/* eqpuls_end */
-+		/* eqpuls_bline */
-+		/* eqpuls_eline */
-+		.hso_begin = 0,
-+		.hso_end = 0x80,
-+		.vso_begin = 0x1e,
-+		.vso_end = 0x32,
-+		.vso_bline = 0,
-+		.vso_eline = 4,
-+		.vso_eline_present = true,
-+		/* sy_val */
-+		/* sy2_val */
-+		.max_lncnt = 0x273,
-+	},
-+};
-+
-+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1024x768_60 = {
-+	.encp = {
-+		.dvi_settings = 0x21,
-+		.video_mode = 0x4040,
-+		.video_mode_adv = 0x18,
-+		/* video_prog_mode */
-+		/* video_sync_mode */
-+		/* video_yc_dly */
-+		/* video_rgb_ctrl */
-+		/* video_filt_ctrl */
-+		/* video_ofld_voav_ofst */
-+		/* yfp1_htime */
-+		/* yfp2_htime */
-+		.max_pxcnt = 1343,
-+		/* hspuls_begin */
-+		/* hspuls_end */
-+		/* hspuls_switch */
-+		/* vspuls_begin */
-+		/* vspuls_end */
-+		/* vspuls_bline */
-+		/* vspuls_eline */
-+		.havon_begin = 296,
-+		.havon_end = 1319,
-+		.vavon_bline = 35,
-+		.vavon_eline = 802,
-+		/* eqpuls_begin */
-+		/* eqpuls_end */
-+		/* eqpuls_bline */
-+		/* eqpuls_eline */
-+		.hso_begin = 0,
-+		.hso_end = 136,
-+		.vso_begin = 30,
-+		.vso_end = 50,
-+		.vso_bline = 0,
-+		.vso_eline = 6,
-+		.vso_eline_present = true,
-+		/* sy_val */
-+		/* sy2_val */
-+		.max_lncnt = 805,
-+	},
-+};
-+
-+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1152x864_75 = {
-+	.encp = {
-+		.dvi_settings = 0x21,
-+		.video_mode = 0x4040,
-+		.video_mode_adv = 0x18,
-+		/* video_prog_mode */
-+		/* video_sync_mode */
-+		/* video_yc_dly */
-+		/* video_rgb_ctrl */
-+		/* video_filt_ctrl */
-+		/* video_ofld_voav_ofst */
-+		/* yfp1_htime */
-+		/* yfp2_htime */
-+		.max_pxcnt = 0x63f,
-+		/* hspuls_begin */
-+		/* hspuls_end */
-+		/* hspuls_switch */
-+		/* vspuls_begin */
-+		/* vspuls_end */
-+		/* vspuls_bline */
-+		/* vspuls_eline */
-+		.havon_begin = 0x180,
-+		.havon_end = 0x5ff,
-+		.vavon_bline = 0x23,
-+		.vavon_eline = 0x382,
-+		/* eqpuls_begin */
-+		/* eqpuls_end */
-+		/* eqpuls_bline */
-+		/* eqpuls_eline */
-+		.hso_begin = 0,
-+		.hso_end = 0x80,
-+		.vso_begin = 0x1e,
-+		.vso_end = 0x32,
-+		.vso_bline = 0,
-+		.vso_eline = 3,
-+		.vso_eline_present = true,
-+		/* sy_val */
-+		/* sy2_val */
-+		.max_lncnt = 0x383,
-+	},
-+};
-+
-+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1280x1024_60 = {
-+	.encp = {
-+		.dvi_settings = 0x21,
-+		.video_mode = 0x4040,
-+		.video_mode_adv = 0x18,
-+		/* video_prog_mode */
-+		/* video_sync_mode */
-+		/* video_yc_dly */
-+		/* video_rgb_ctrl */
-+		/* video_filt_ctrl */
-+		/* video_ofld_voav_ofst */
-+		/* yfp1_htime */
-+		/* yfp2_htime */
-+		.max_pxcnt = 0x697,
-+		/* hspuls_begin */
-+		/* hspuls_end */
-+		/* hspuls_switch */
-+		/* vspuls_begin */
-+		/* vspuls_end */
-+		/* vspuls_bline */
-+		/* vspuls_eline */
-+		.havon_begin = 0x168,
-+		.havon_end = 0x667,
-+		.vavon_bline = 0x29,
-+		.vavon_eline = 0x428,
-+		/* eqpuls_begin */
-+		/* eqpuls_end */
-+		/* eqpuls_bline */
-+		/* eqpuls_eline */
-+		.hso_begin = 0,
-+		.hso_end = 0x70,
-+		.vso_begin = 0x1e,
-+		.vso_end = 0x32,
-+		.vso_bline = 0,
-+		.vso_eline = 3,
-+		.vso_eline_present = true,
-+		/* sy_val */
-+		/* sy2_val */
-+		.max_lncnt = 0x429,
-+	},
-+};
-+
-+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1600x1200_60 = {
-+	.encp = {
-+		.dvi_settings = 0x21,
-+		.video_mode = 0x4040,
-+		.video_mode_adv = 0x18,
-+		/* video_prog_mode */
-+		/* video_sync_mode */
-+		/* video_yc_dly */
-+		/* video_rgb_ctrl */
-+		/* video_filt_ctrl */
-+		/* video_ofld_voav_ofst */
-+		/* yfp1_htime */
-+		/* yfp2_htime */
-+		.max_pxcnt = 0x86f,
-+		/* hspuls_begin */
-+		/* hspuls_end */
-+		/* hspuls_switch */
-+		/* vspuls_begin */
-+		/* vspuls_end */
-+		/* vspuls_bline */
-+		/* vspuls_eline */
-+		.havon_begin = 0x1f0,
-+		.havon_end = 0x82f,
-+		.vavon_bline = 0x31,
-+		.vavon_eline = 0x4e0,
-+		/* eqpuls_begin */
-+		/* eqpuls_end */
-+		/* eqpuls_bline */
-+		/* eqpuls_eline */
-+		.hso_begin = 0,
-+		.hso_end = 0xc0,
-+		.vso_begin = 0x1e,
-+		.vso_end = 0x32,
-+		.vso_bline = 0,
-+		.vso_eline = 3,
-+		.vso_eline_present = true,
-+		/* sy_val */
-+		/* sy2_val */
-+		.max_lncnt = 0x4e1,
-+	},
-+};
-+
-+struct meson_hdmi_venc_dmt_mode {
-+	struct drm_display_mode drm_mode;
-+	union meson_hdmi_venc_mode *mode;
-+} meson_hdmi_venc_dmt_modes[] = {
-+	/* 640x480@60Hz */
-+	{
-+		{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
-+		  752, 800, 0, 480, 490, 492, 525, 0,
-+		  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
-+		&meson_hdmi_encp_mode_640x480_60,
-+	},
-+	/* 800x600@60Hz */
-+	{
-+		{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
-+		  968, 1056, 0, 600, 601, 605, 628, 0,
-+		  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
-+		&meson_hdmi_encp_mode_800x600_60,
-+	},
-+	/* 1024x768@60Hz */
-+	{
-+		{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024,
-+		  1048, 1184, 1344, 0, 768, 771, 777, 806, 0,
-+		  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
-+		&meson_hdmi_encp_mode_1024x768_60,
-+	},
-+	/* 1152x864@75Hz */
-+	{
-+		{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152,
-+		  1216, 1344, 1600, 0, 864, 865, 868, 900, 0,
-+		  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
-+		&meson_hdmi_encp_mode_1152x864_75,
-+	},
-+	/* 1280x1024@60Hz */
-+	{
-+		{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280,
-+		  1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
-+		  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
-+		&meson_hdmi_encp_mode_1280x1024_60,
-+	},
-+	/* 1600x1200@60Hz */
-+	{
-+		{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600,
-+		  1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
-+		  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
-+		&meson_hdmi_encp_mode_1600x1200_60,
-+	},
-+	/* 1920x1080@60Hz */
-+	{
-+		{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920,
-+		  2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
-+		  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
-+		&meson_hdmi_encp_mode_1080p60
-+	},
-+	{ }, /* sentinel */
-+};
-+
- struct meson_hdmi_venc_vic_mode {
- 	unsigned int vic;
- 	union meson_hdmi_venc_mode *mode;
-@@ -736,6 +1044,20 @@ static unsigned long modulo(unsigned long a, unsigned long b)
- 		return a;
- }
- 
-+bool meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
-+{
-+	struct meson_hdmi_venc_dmt_mode *vmode = meson_hdmi_venc_dmt_modes;
-+
-+	while (vmode->mode) {
-+		if (drm_mode_equal(&vmode->drm_mode, mode))
-+			return true;
-+		vmode++;
-+	}
-+
-+	return false;
-+}
-+EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
-+
- bool meson_venc_hdmi_supported_vic(int vic)
- {
- 	struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
-@@ -750,6 +1072,20 @@ bool meson_venc_hdmi_supported_vic(int vic)
- }
- EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
- 
-+static union meson_hdmi_venc_mode
-+*meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode)
-+{
-+	struct meson_hdmi_venc_dmt_mode *vmode = meson_hdmi_venc_dmt_modes;
-+
-+	while (vmode->mode) {
-+		if (drm_mode_equal(&vmode->drm_mode, mode))
-+			return vmode->mode;
-+		vmode++;
-+	}
-+
-+	return NULL;
-+}
-+
- static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
- {
- 	struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
-@@ -811,10 +1147,13 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
- 	unsigned int sof_lines;
- 	unsigned int vsync_lines;
- 
--	vmode = meson_venc_hdmi_get_vic_vmode(vic);
-+	if (meson_venc_hdmi_supported_vic(vic))
-+		vmode = meson_venc_hdmi_get_vic_vmode(vic);
-+	else
-+		vmode = meson_venc_hdmi_get_dmt_vmode(mode);
- 	if (!vmode) {
--		dev_err(priv->dev, "%s: Fatal Error, unsupported vic %d\n",
--			__func__, vic);
-+		dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
-+			DRM_MODE_FMT "\n", __func__, DRM_MODE_ARG(mode));
- 		return;
- 	}
- 
-@@ -864,7 +1203,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
- 		hsync_pixels_venc *= 2;
- 
- 	/* Disable VDACs */
--	writel_bits_relaxed(0x1f, 0x1f,
-+	writel_bits_relaxed(0xff, 0xff,
- 			priv->io_base + _REG(VENC_VDAC_SETTING));
- 
- 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
-diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
-index a1b96e8..7c18a36 100644
---- a/drivers/gpu/drm/meson/meson_venc.h
-+++ b/drivers/gpu/drm/meson/meson_venc.h
-@@ -58,6 +58,7 @@ struct meson_cvbs_enci_mode {
- };
- 
- /* HDMI Clock parameters */
-+bool meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
- bool meson_venc_hdmi_supported_vic(int vic);
- bool meson_venc_hdmi_venc_repeat(int vic);
- 
--- 
-2.7.4
-

buildroot-external/board/hardkernel/odroid-c2/uboot-boot.ush

@@ -3,15 +3,15 @@
 
 part start mmc ${devnum} 9 mmc_env
 mmc dev ${devnum}
-setenv loadbootstate "\
-echo 'loading env...';\
-mmc read ${ramdisk_addr_r} ${mmc_env} 0x10;\
-env import -c ${ramdisk_addr_r} 0x2000;"
+setenv loadbootstate " \
+    echo 'loading env...'; \
+    mmc read ${ramdisk_addr_r} ${mmc_env} 0x10; \
+    env import -c ${ramdisk_addr_r} 0x2000;"
 
-setenv storebootstate "\
-echo 'storing env...';\
-env export -c -s 0x2000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT;\
-mmc write ${ramdisk_addr_r} ${mmc_env} 0x10;"
+setenv storebootstate " \
+    echo 'storing env...'; \
+    env export -c -s 0x2000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT; \
+    mmc write ${ramdisk_addr_r} ${mmc_env} 0x10;"
 
 run loadbootstate
 test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"

buildroot-external/board/hardkernel/odroid-xu4/boot-env.txt

@@ -0,0 +1,41 @@
+
+macaddr=00:1e:06:61:7a:39
+vout=hdmi
+vout=hdmi
+# - DVI Mode (disables sound over HDMI as per DVI compat)
+# vout=dvi
+
+# --- HDMI CEC Configuration ---
+# ------------------------------------------
+cecenable=false
+# set to true to enable HDMI CEC
+
+# Enable/Disable ODROID-VU7 Touchsreen
+disable_vu7=false
+
+# DRAM Frequency
+# Sets the LPDDR3 memory frequency
+# Supported values: 933 825 728 633 (MHZ)
+ddr_freq 825
+
+# External watchdog board enable
+external_watchdog=false
+# debounce time set to 3 ~ 10 sec, default 3 sec
+external_watchdog_debounce=3
+
+
+#------------------------------------------------------------------------------
+#
+# HDMI Hot Plug detection
+#
+#------------------------------------------------------------------------------
+#
+# Forces the HDMI subsystem to ignore the check if the cable is connected or
+# not.
+# false : disable the detection and force it as connected.
+# true : let cable, board and monitor decide the connection status.
+#
+# default: true
+#
+#------------------------------------------------------------------------------
+HPD=true

buildroot-external/board/hardkernel/odroid-xu4/hassos-hook.sh

@@ -0,0 +1,31 @@
+#!/bin/bash
+# shellcheck disable=SC2155
+
+function hassos_pre_image() {
+    local BOOT_DATA="$(path_boot_dir)"
+    local BL1="${BINARIES_DIR}/bl1.bin.hardkernel"
+    local BL2="${BINARIES_DIR}/bl2.bin.hardkernel.720k_uboot"
+    local BLTZ="${BINARIES_DIR}/tzsw.bin.hardkernel"
+    local UBOOT="${BINARIES_DIR}/u-boot.bin"
+    local spl_img="$(path_spl_img)"
+
+    cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
+    cp "${BOARD_DIR}/boot-env.txt" "${BOOT_DATA}/config.txt"
+    cp "${BINARIES_DIR}/exynos5422-odroidxu4.dtb" "${BOOT_DATA}/exynos5422-odroidxu4.dtb"
+
+    echo "console=tty1 console=ttySAC2,115200" > "${BOOT_DATA}/cmdline.txt"
+
+    # SPL
+    create_spl_image
+
+    dd if="${BL1}" of="${spl_img}" conv=notrunc bs=512 seek=1
+    dd if="${BL2}" of="${spl_img}" conv=notrunc bs=512 seek=31
+    dd if="${UBOOT}" of="${spl_img}" conv=notrunc bs=512 seek=63
+    dd if="${BLTZ}" of="${spl_img}" conv=notrunc bs=512 seek=1503
+    dd if=/dev/zero of="${spl_img}" conv=notrunc bs=512 count=32 seek=2015
+}
+
+
+function hassos_post_image() {
+    convert_disk_image_gz
+}

buildroot-external/board/hardkernel/odroid-xu4/meta

@@ -0,0 +1,7 @@
+BOARD_ID=odroid-xu4
+BOARD_NAME="Hardkernel Odroid-XU4"
+CHASSIS=embedded
+BOOTLOADER=uboot
+KERNEL_FILE=zImage
+BOOT_SYS=mbr
+BOOT_ENV_SIZE=0x2000

buildroot-external/board/hardkernel/odroid-xu4/uboot-boot.ush

@@ -0,0 +1,98 @@
+
+###########################################
+
+part start mmc ${devnum} 9 mmc_env
+mmc dev ${devnum}
+setenv loadbootstate " \
+    echo 'loading env...'; \
+    mmc read ${ramdisk_addr_r} ${mmc_env} 0x10; \
+    env import -c ${ramdisk_addr_r} 0x2000;"
+
+setenv storebootstate " \
+    echo 'storing env...'; \
+    env export -c -s 0x2000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT; \
+    mmc write ${ramdisk_addr_r} ${mmc_env} 0x10;"
+
+run loadbootstate
+test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"
+test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3
+test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3
+
+if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
+  env import -t ${ramdisk_addr_r} ${filesize};
+fi
+
+# Board bootargs
+setenv hdmi_phy_control "HPD=${HPD} vout=${vout}"
+if test "${cecenable}" = "false"; then fdt rm /cec@101B0000; fi
+if test "${disable_vu7}" = "false"; then setenv hid_quirks "usbhid.quirks=0x0eef:0x0005:0x0004"; fi
+if test "${external_watchdog}" = "true"; then setenv external_watchdog "external_watchdog=${external_watchdog} external_watchdog_debounce=${external_watchdog_debounce}"; fi
+
+setenv bootargs_odroidxu4 "${videoconfig} ${hdmi_phy_control} ${hid_quirks} smsc95xx.macaddr=${macaddr} ${external_watchdog}"
+
+# HassOS bootargs
+setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor cgroup_enable=memory"
+
+# HassOS system A/B
+setenv bootargs_a "root=PARTUUID=48617373-06 rootfstype=squashfs ro rootwait"
+setenv bootargs_b "root=PARTUUID=48617373-08 rootfstype=squashfs ro rootwait"
+
+#usb start
+
+# Load extraargs
+fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
+fatload mmc ${devnum}:1 ${fdt_addr_r} exynos5422-odroidxu4.dtb
+fdt addr ${fdt_addr_r}
+
+
+# logical volumes get numbered after physical ones.
+# 1. boot
+# 2. Extended partition
+# 3. Overlay
+# 4. Data
+# 5. KernelA
+# 6. SystemA
+# 7. KernelB
+# 8. SystemB
+# 9. BootInfo
+setenv bootargs
+for BOOT_SLOT in "${BOOT_ORDER}"; do
+  if test "x${bootargs}" != "x"; then
+    # skip remaining slots
+  elif test "x${BOOT_SLOT}" = "xA"; then
+    if test ${BOOT_A_LEFT} -gt 0; then
+      setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
+      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
+      setenv load_kernel "ext4load mmc ${devnum}:5 ${kernel_addr_r} zImage"
+      setenv bootargs "${bootargs_hassos} ${bootargs_odroidxu4} ${bootargs_a} rauc.slot=A ${cmdline}"
+    fi
+  elif test "x${BOOT_SLOT}" = "xB"; then
+    if test ${BOOT_B_LEFT} -gt 0; then
+      setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
+      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
+      setenv load_kernel "ext4load mmc ${devnum}:7 ${kernel_addr_r} zImage"
+      setenv bootargs "${bootargs_hassos} ${bootargs_odroidxu4} ${bootargs_b} rauc.slot=B ${cmdline}"
+    fi
+  fi
+done
+
+if test -n "${bootargs}"; then
+  run storebootstate
+else
+  echo "No valid slot found, resetting tries to 3"
+  setenv BOOT_A_LEFT 3
+  setenv BOOT_B_LEFT 3
+  run storebootstate
+  reset
+fi
+
+echo "Loading kernel"
+run load_kernel
+echo " Starting kernel"
+printenv load_kernel
+printenv bootargs
+dmc ${ddr_freq}
+bootz ${kernel_addr_r} - ${fdt_addr_r}
+
+echo "Fails on boot"
+reset

buildroot-external/board/hardkernel/odroid-xu4/uboot.config

@@ -0,0 +1,6 @@
+# CONFIG_USB_STORAGE is not set
+CONFIG_DOS_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_CMD_FILEENV=y
+CONFIG_ENV_IS_NOWHERE=Y
+CONFIG_DISPLAY_BOARDINFO=y

buildroot-external/board/intel/nuc/hassos-hook.sh

@@ -0,0 +1,20 @@
+#!/bin/bash
+# shellcheck disable=SC2155
+
+function hassos_pre_image() {
+    local BOOT_DATA="$(path_boot_dir)"
+
+    mkdir -p "${BOOT_DATA}/EFI/BOOT"
+    mkdir -p "${BOOT_DATA}/EFI/barebox"
+
+    cp "${BINARIES_DIR}/barebox.bin" "${BOOT_DATA}/EFI/BOOT/BOOTx64.EFI"
+    cp "${BR2_EXTERNAL_HASSOS_PATH}/misc/barebox-state-efi.dtb" "${BOOT_DATA}/EFI/barebox/state.dtb"
+
+    echo "console=tty1" > "${BOOT_DATA}/cmdline.txt"
+}
+
+
+function hassos_post_image() {
+    convert_disk_image_gz
+}
+

buildroot-external/board/intel/nuc/kernel.config

@@ -0,0 +1,31 @@
+CONFIG_EFI_STUB=y
+
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_USB_XHCI_HCD=y
+
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+
+CONFIG_IGB=y
+
+CONFIG_IWLWIFI=m
+CONFIG_IWLMVM=m
+
+CONFIG_DRM_I915=m
+CONFIG_DRM_I915_CAPTURE_ERROR=y
+CONFIG_DRM_I915_COMPRESS_ERROR=y
+CONFIG_DRM_I915_USERPTR=y
+
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_I915=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1
+
+CONFIG_BT=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_LE=y
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_RTL=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTUSB_BCM=y
+CONFIG_BT_HCIBTUSB_RTL=y

buildroot-external/board/intel/nuc/meta

@@ -0,0 +1,7 @@
+BOARD_ID=intel-nuc
+BOARD_NAME="Intel NUC"
+CHASSIS=embedded
+BOOTLOADER=barebox
+KERNEL_FILE=bzImage
+BOOT_SYS=efi
+DISK_SIZE=6

buildroot-external/board/intel/ova/hassos-hook.sh

@@ -0,0 +1,24 @@
+#!/bin/bash
+# shellcheck disable=SC2155
+
+function hassos_pre_image() {
+    local BOOT_DATA="$(path_boot_dir)"
+
+    mkdir -p "${BOOT_DATA}/EFI/BOOT"
+    mkdir -p "${BOOT_DATA}/EFI/barebox"
+
+    cp "${BINARIES_DIR}/barebox.bin" "${BOOT_DATA}/EFI/BOOT/BOOTx64.EFI"
+    cp "${BR2_EXTERNAL_HASSOS_PATH}/misc/barebox-state-efi.dtb" "${BOOT_DATA}/EFI/barebox/state.dtb"
+
+    echo "console=tty1" > "${BOOT_DATA}/cmdline.txt"
+}
+
+
+function hassos_post_image() {
+    convert_disk_image_virtual
+
+    convert_disk_image_gz vmdk
+    convert_disk_image_gz vhdx
+    convert_disk_image_gz vdi
+}
+

buildroot-external/board/intel/ova/kernel.config

@@ -0,0 +1,24 @@
+CONFIG_EFI_STUB=y
+
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_BLK=y
+CONFIG_HW_RANDOM_VIRTIO=y
+
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_USB_XHCI_HCD=y
+
+CONFIG_PARAVIRT=y
+CONFIG_XEN=y
+
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_HYPERV=y
+CONFIG_HYPERV_UTILS=m
+CONFIG_HYPERV_BALLOON=m
+CONFIG_HYPERV_KEYBOARD=m
+CONFIG_HYPERV_STORAGE=y
+CONFIG_HYPERV_NET=y
+CONFIG_FB_HYPERV=y

buildroot-external/board/orangepi/hassos-hook.sh

@@ -0,0 +1,25 @@
+#!/bin/bash
+# shellcheck disable=SC2155
+
+function hassos_pre_image() {
+    local BOOT_DATA="$(path_boot_dir)"
+    local SPL="${BINARIES_DIR}/sunxi-spl.bin"
+    local UBOOT="${BINARIES_DIR}/u-boot.itb"
+    local spl_img="$(path_spl_img)"
+
+    cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr"
+    cp "${BINARIES_DIR}/sun50i-h5-orangepi-prime.dtb" "${BOOT_DATA}/sun50i-h5-orangepi-prime.dtb"
+    cp "${BOARD_DIR}/config.txt" "${BOOT_DATA}/config.txt"
+    touch "${BOOT_DATA}/cmdline.txt"
+
+    # SPL
+    create_spl_image
+
+    dd if="${SPL}" of="${spl_img}" conv=notrunc bs=512 seek=16
+    dd if="${UBOOT}" of="${spl_img}" conv=notrunc bs=512 seek=80
+}
+
+
+function hassos_post_image() {
+    convert_disk_image_gz
+}

buildroot-external/board/orangepi/kernel.config

@@ -0,0 +1,3 @@
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+

buildroot-external/board/orangepi/patches/README.md

@@ -0,0 +1,5 @@
+## Kernel
+https://github.com/armbian/build/tree/master/patch/kernel/sunxi-next
+
+## u-boot
+https://github.com/armbian/build/tree/master/patch/u-boot/u-boot-sunxi

buildroot-external/board/orangepi/patches/uboot/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch

@@ -0,0 +1,41 @@
+From 55d3cc28b37000d1a3d7224c0ba4a808274e0b33 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Fri, 27 Oct 2017 17:25:00 +0800
+Subject: [PATCH 20/20] sunxi: call fdt_fixup_ethernet again to set macaddr for
+ more aliases
+
+Sometimes some ethernet aliases do not exist in U-Boot FDT but they
+exist in the FDT used to boot the system. In this situation
+setup_environment is called again in ft_board_setup to generate macaddr
+environment variable for them. However now the call to
+fdt_fixup_ethernet is moved before the call of ft_board_setup.
+
+Call fdt_fixup_ethernet again to add MAC addresses for the extra
+ethernet aliases.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ board/sunxi/board.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/board/sunxi/board.c b/board/sunxi/board.c
+index 192cf8ca45..0fe70f47cb 100644
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -751,10 +751,12 @@ int ft_board_setup(void *blob, bd_t *bd)
+	int __maybe_unused r;
+
+	/*
+-	 * Call setup_environment again in case the boot fdt has
+-	 * ethernet aliases the u-boot copy does not have.
++	 * Call setup_environment and fdt_fixup_ethernet again
++	 * in case the boot fdt has ethernet aliases the u-boot
++	 * copy does not have.
+	 */
+	setup_environment(blob);
++	fdt_fixup_ethernet(blob);
+
+ #ifdef CONFIG_VIDEO_DT_SIMPLEFB
+	r = sunxi_simplefb_setup(blob);
+--
+2.13.6

buildroot-external/board/orangepi/patches/uboot/4kfix-limit-screen-to-full-hd.patch

@@ -0,0 +1,19 @@
+diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
+index 92c9d06054..cd16d69e30 100644
+--- a/drivers/video/sunxi/sunxi_display.c
++++ b/drivers/video/sunxi/sunxi_display.c
+@@ -1274,8 +1274,12 @@ void *video_hw_init(void)
+		ret = sunxi_hdmi_hpd_detect(hpd_delay);
+		if (ret) {
+			printf("HDMI connected: ");
+-			if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
+-				mode = &custom;
++			if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) {
++				if ((custom.xres <= 1920) && (custom.yres <= 1080))
++					mode = &custom;
++				else
++					mode = &res_mode_init[RES_MODE_1920x1080];
++			}
+		} else if (hpd) {
+			sunxi_hdmi_shutdown();
+			sunxi_display.monitor = sunxi_get_default_mon(false);

buildroot-external/board/orangepi/patches/uboot/adjust-default-dram-clockspeeds.patch

@@ -0,0 +1,13 @@
+diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
+index 103936d772..990cf2a8c0 100644
+--- a/configs/orangepi_prime_defconfig
++++ b/configs/orangepi_prime_defconfig
+@@ -1,7 +1,7 @@
+ CONFIG_ARM=y
+ CONFIG_ARCH_SUNXI=y
+ CONFIG_MACH_SUN50I_H5=y
+-CONFIG_DRAM_CLK=672
++CONFIG_DRAM_CLK=624
+ CONFIG_DRAM_ZQ=3881977
+ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

buildroot-external/board/orangepi/patches/uboot/do-not-relocate-initrd.patch

@@ -0,0 +1,27 @@
+diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
+index 64a190059a..bbec551cac 100644
+--- a/include/configs/sunxi-common.h
++++ b/include/configs/sunxi-common.h
+@@ -503,6 +503,12 @@ extern int soft_i2c_gpio_scl;
+ #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+ #endif
+
++#ifdef CONFIG_MACH_SUN8I_H3
++#define INITRD_HIGH_ENV "initrd_high=0xFFFFFFFF\0"
++#else
++#define INITRD_HIGH_ENV
++#endif
++
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONSOLE_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+@@ -512,7 +518,8 @@ extern int soft_i2c_gpio_scl;
+	SUNXI_MTDIDS_DEFAULT \
+	SUNXI_MTDPARTS_DEFAULT \
+	BOOTCMD_SUNXI_COMPAT \
+-	BOOTENV
++	BOOTENV \
++	INITRD_HIGH_ENV
+
+ #else /* ifndef CONFIG_SPL_BUILD */
+ #define CONFIG_EXTRA_ENV_SETTINGS

buildroot-external/board/orangepi/patches/uboot/enable-DT-overlays-support.patch

@@ -0,0 +1,13 @@
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 0ed36cded..822ebb812 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -578,6 +578,8 @@ config ARCH_SUNXI
+	select CMD_GPIO
+	select CMD_MMC if MMC
+	select CMD_USB if DISTRO_DEFAULTS
++	select OF_LIBFDT
++	select OF_LIBFDT_OVERLAY
+	select DM
+	select DM_ETH
+	select DM_GPIO

buildroot-external/board/orangepi/patches/uboot/enable-r_pio-gpio-access-h3-h5.patch

@@ -0,0 +1,24 @@
+diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
+index 7ac8360..0484e7a 100644
+--- a/arch/arm/mach-sunxi/board.c
++++ b/arch/arm/mach-sunxi/board.c
+@@ -23,6 +23,7 @@
+ #include <asm/arch/timer.h>
+ #include <asm/arch/tzpc.h>
+ #include <asm/arch/mmc.h>
++#include <asm/arch/prcm.h>
+
+ #include <linux/compiler.h>
+
+@@ -65,6 +66,11 @@ struct mm_region *mem_map = sunxi_mem_map;
+
+ static int gpio_init(void)
+ {
++#if defined(CONFIG_MACH_SUNXI_H3_H5)
++	/* enable R_PIO GPIO access */
++	prcm_apb0_enable(PRCM_APB0_GATE_PIO);
++#endif
++
+ #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+ #if defined(CONFIG_MACH_SUN4I) || \
+     defined(CONFIG_MACH_SUN7I) || \

buildroot-external/board/orangepi/patches/uboot/fdt-setprop-fix-unaligned-access.patch

@@ -0,0 +1,23 @@
+diff --git a/cmd/fdt.c b/cmd/fdt.c
+index d7654b2c4f..a71b7713a8 100644
+--- a/cmd/fdt.c
++++ b/cmd/fdt.c
+@@ -17,6 +17,7 @@
+ #include <fdt_support.h>
+ #include <mapmem.h>
+ #include <asm/io.h>
++#include <asm/unaligned.h>
+
+ #define MAX_LEVEL	32		/* how deeply nested we will go */
+ #define SCRATCHPAD	1024		/* bytes of scratchpad memory */
+@@ -781,7 +782,10 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len)
+			cp = newp;
+			tmp = simple_strtoul(cp, &newp, 0);
+			if (*cp != '?')
+-				*(fdt32_t *)data = cpu_to_fdt32(tmp);
++			{
++				tmp = cpu_to_fdt32(tmp);
++				put_unaligned(tmp, (fdt32_t *)data);
++			}
+			else
+				newp++;

buildroot-external/board/orangepi/patches/uboot/h3-Fix-PLL1-setup-to-never-use-dividers.patch

@@ -0,0 +1,32 @@
+From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megous@megous.com>
+Date: Tue, 20 Dec 2016 11:25:12 +0100
+Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
+
+Kernel would lower the divider on first CLK change and cause the
+lock up.
+---
+ arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
+index 50fb302a19..91aa2a0478 100644
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
+	int k = 1;
+	int m = 1;
+
+-	if (clk > 1152000000) {
+-		k = 2;
+-	} else if (clk > 768000000) {
++	if (clk >= 1368000000) {
+		k = 3;
+-		m = 2;
++	} else if (clk >= 768000000) {
++		k = 2;
+	}
+
+	/* Switch to 24MHz clock while changing PLL1 */
+--
+2.11.0

buildroot-external/board/orangepi/patches/uboot/h3-enable-power-led.patch

@@ -0,0 +1,16 @@
+diff --git a/board/sunxi/board.c b/board/sunxi/board.c
+index 3cf3614..89cf7f5 100644
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -478,6 +478,11 @@ void sunxi_board_init(void)
+	int power_failed = 0;
+	unsigned long ramsize;
+
++#ifdef CONFIG_MACH_SUN8I_H3
++	/* turn on power LED (PL10) on H3 boards */
++	gpio_direction_output(SUNXI_GPL(10), 1);
++#endif
++
+ #ifdef CONFIG_SY8106A_POWER
+	power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
+ #endif

buildroot-external/board/orangepi/patches/uboot/h3-set-safe-axi_apb-clock-dividers.patch

@@ -0,0 +1,42 @@
+diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
+index 15272c9..cedddc2 100644
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk)
+	sdelay(200);
+
+	/* Switch CPU to PLL1 */
+-	writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+-	       ATB_DIV_2 << ATB_DIV_SHIFT |
++	writel(AXI_DIV_4 << AXI_DIV_SHIFT |
++	       ATB_DIV_4 << ATB_DIV_SHIFT |
+	       CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+ }
+diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+index f2990db..b3a8575 100644
+--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
++++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+@@ -180,6 +180,7 @@ struct sunxi_ccm_reg {
+ #define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+ #define CCM_PLL1_CTRL_P(n)		(((n) & 0x3) << 16)
+ #define CCM_PLL1_CTRL_EN		(0x1 << 31)
++#define CCM_PLL1_CTRL_LOCK		(0x1 << 28)
+
+ #define CCM_PLL3_CTRL_M_SHIFT		0
+ #define CCM_PLL3_CTRL_M_MASK		(0xf << CCM_PLL3_CTRL_M_SHIFT)
+diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
+index cedddc2..3fe9305 100644
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk)
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
+	       CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
+	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+-	sdelay(200);
++
++	while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
++		;
+
+	/* Switch CPU to PLL1 */
+	writel(AXI_DIV_4 << AXI_DIV_SHIFT |

buildroot-external/board/orangepi/patches/uboot/lower-default-DRAM-freq-A64-H5.patch.disabled

@@ -0,0 +1,13 @@
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index 2309f59999..716e9c5e26 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -278,7 +278,7 @@ config DRAM_CLK
+	default 312 if MACH_SUN6I || MACH_SUN8I
+	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
+		       MACH_SUN8I_V3S
+-	default 672 if MACH_SUN50I
++	default 648 if MACH_SUN50I || MACH_SUN50I_H5
+	---help---
+	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
+	must be a multiple of 24. For the sun9i (A80), the tested values

buildroot-external/board/orangepi/patches/uboot/sun8i-set-machid.patch

@@ -0,0 +1,11 @@
+diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
+index a4c3fb69e..47ce2e9e6 100644
+--- a/include/configs/sun8i.h
++++ b/include/configs/sun8i.h
+@@ -30,4 +30,6 @@
+  */
+ #include <configs/sunxi-common.h>
+
++#define CONFIG_MACH_TYPE	(0x1029)
++
+ #endif /* __CONFIG_H */

buildroot-external/board/orangepi/patches/uboot/sunxi-boot-splash.patch

@@ -0,0 +1,62 @@
+diff --git a/cmd/Kconfig b/cmd/Kconfig
+index d6d130edfa..92795119ea 100644
+--- a/cmd/Kconfig
++++ b/cmd/Kconfig
+@@ -1029,6 +1029,7 @@ menu "Misc commands"
+ config CMD_BMP
+	bool "Enable 'bmp' command"
+	depends on LCD || DM_VIDEO || VIDEO
++	default y
+	help
+	  This provides a way to obtain information about a BMP-format iamge
+	  and to display it. BMP (which presumably stands for BitMaP) is a
+diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
+index 9ed6b9892c..75d5176edf 100644
+--- a/include/config_distro_bootcmd.h
++++ b/include/config_distro_bootcmd.h
+@@ -323,6 +323,15 @@
+	BOOTENV_SHARED_UBIFS \
+	BOOTENV_SHARED_EFI \
+	"boot_prefixes=/ /boot/\0" \
++	"splashpos=m,m\0" \
++	"splashimage=66000000\0" \
++	"loadsplash= " \
++		"for prefix in ${boot_prefixes}; do " \
++			"if test -e mmc 0 ${prefix}boot.bmp; then " \
++				"load mmc 0 ${splashimage} ${prefix}boot.bmp; " \
++				"bmp d ${splashimage}; " \
++			"fi; " \
++		"done\0" \
+	"boot_scripts=boot.scr.uimg boot.scr\0" \
+	"boot_script_dhcp=boot.scr.uimg\0" \
+	BOOTENV_BOOT_TARGETS \
+diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
+index 02d7be0849..cbdea20d08 100644
+--- a/include/configs/sunxi-common.h
++++ b/include/configs/sunxi-common.h
+@@ -284,6 +284,16 @@ extern int soft_i2c_gpio_scl;
+
+ #endif /* CONFIG_VIDEO */
+
++#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
++#define CONFIG_VIDEO_LOGO
++#define CONFIG_SPLASH_SCREEN
++#define CONFIG_SPLASH_SCREEN_ALIGN
++#define CONFIG_BMP_16BPP
++#define CONFIG_BMP_24BPP
++#define CONFIG_BMP_32BPP
++#define CONFIG_VIDEO_BMP_RLE8
++#endif
++
+ /* Ethernet support */
+ #ifdef CONFIG_SUNXI_EMAC
+ #define CONFIG_PHY_ADDR		1
+@@ -444,7 +454,7 @@ extern int soft_i2c_gpio_scl;
+
+ #ifdef CONFIG_USB_KEYBOARD
+ #define CONSOLE_STDIN_SETTINGS \
+-	"preboot=usb start\0" \
++	"preboot=run loadsplash; usb start\0" \
+	"stdin=serial,usbkbd\0"
+ #else
+ #define CONSOLE_STDIN_SETTINGS \

buildroot-external/board/orangepi/prime/config.txt

@@ -0,0 +1,3 @@
+i2c0_enable=true
+i2c1_enable=false
+i2c2_enable=false

buildroot-external/board/orangepi/prime/meta

@@ -0,0 +1,7 @@
+BOARD_ID=opi-prime
+BOARD_NAME="Orange Pi Prime"
+CHASSIS=embedded
+BOOTLOADER=uboot
+KERNEL_FILE=Image
+BOOT_SYS=spl
+BOOT_ENV_SIZE=0x8000

buildroot-external/board/orangepi/prime/uboot-boot.ush

@@ -0,0 +1,88 @@
+
+part start mmc ${devnum} 6 mmc_env
+mmc dev ${devnum}
+setenv loadbootstate " \
+    echo 'loading env...'; \
+    mmc read ${ramdisk_addr_r} ${mmc_env} 0x40; \
+    env import -c ${ramdisk_addr_r} 0x8000;"
+
+setenv storebootstate " \
+    echo 'storing env...'; \
+    env export -c -s 0x8000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT; \
+    mmc write ${ramdisk_addr_r} ${mmc_env} 0x40;"
+
+run loadbootstate
+test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"
+test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3
+test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3
+
+# HassOS bootargs
+setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 apparmor=1 security=apparmor cgroup_enable=memory rootwait"
+
+# HassOS system A/B
+setenv bootargs_a "root=PARTUUID=8d3d53e3-6d49-4c38-8349-aff6859e82fd rootfstype=squashfs ro"
+setenv bootargs_b "root=PARTUUID=a3ec664e-32ce-4665-95ea-7ae90ce9aa20 rootfstype=squashfs ro"
+
+# Load extraargs
+fileenv mmc ${devnum}:1 ${ramdisk_addr_r} cmdline.txt cmdline
+
+# Load device tree
+fatload mmc ${devnum}:1 ${fdt_addr_r} sun50i-h5-orangepi-prime.dtb
+fdt addr ${fdt_addr_r}
+
+if load mmc ${devnum}:1 ${ramdisk_addr_r} config.txt; then
+  env import -t ${ramdisk_addr_r} ${filesize};
+fi
+
+if test "${i2c0_enable}" != "false"; then
+  fdt set /soc/i2c@1c2ac00 status "okay"
+fi
+
+if test "${i2c1_enable}" != "false"; then
+  fdt set /soc/i2c@1c2b000 status "okay"
+fi
+
+if test "${i2c2_enable}" != "false"; then
+  fdt set /soc/i2c@1c2b400 status "okay"
+fi
+
+setenv bootargs
+for BOOT_SLOT in "${BOOT_ORDER}"; do
+  if test "x${bootargs}" != "x"; then
+    # skip remaining slots
+  elif test "x${BOOT_SLOT}" = "xA"; then
+    if test ${BOOT_A_LEFT} -gt 0; then
+      setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1
+      echo "Found valid slot A, ${BOOT_A_LEFT} attempts remaining"
+      setenv load_kernel "ext4load mmc ${devnum}:2 ${kernel_addr_r} Image"
+      setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}"
+    fi
+  elif test "x${BOOT_SLOT}" = "xB"; then
+    if test ${BOOT_B_LEFT} -gt 0; then
+      setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1
+      echo "Found valid slot B, ${BOOT_B_LEFT} attempts remaining"
+      setenv load_kernel "ext4load mmc ${devnum}:4 ${kernel_addr_r} Image"
+      setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}"
+    fi
+  fi
+done
+
+if test -n "${bootargs}"; then
+  run storebootstate
+else
+  echo "No valid slot found, resetting tries to 3"
+  setenv BOOT_A_LEFT 3
+  setenv BOOT_B_LEFT 3
+  run storebootstate
+  reset
+fi
+
+echo "Loading kernel"
+run load_kernel
+echo " Starting kernel"
+printenv load_kernel
+printenv bootargs
+booti ${kernel_addr_r} - ${fdt_addr_r}
+
+echo "Fails on boot"
+reset

buildroot-external/board/orangepi/prime/uboot.config

@@ -0,0 +1,8 @@
+# CONFIG_USB_STORAGE is not set
+# CONFIG_DOS_PARTITIONcs not set
+CONFIG_EFI_PARTITION is not set
+CONFIG_USB=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_CMD_FILEENV=y
+CONFIG_ENV_IS_NOWHERE=Y

buildroot-external/board/ova/hassos-hook.sh

@@ -1,20 +0,0 @@
-#!/bin/bash
-
-function hassos_pre_image() {
-    local BOOT_DATA="$(path_boot_dir)"
-
-    mkdir -p ${BOOT_DATA}/EFI/BOOT
-    mkdir -p ${BOOT_DATA}/EFI/barebox
-
-    cp ${BINARIES_DIR}/barebox.bin ${BOOT_DATA}/EFI/BOOT/BOOTx64.EFI
-    cp ${BR2_EXTERNAL_HASSOS_PATH}/misc/barebox-state-efi.dtb ${BOOT_DATA}/EFI/barebox/state.dtb
-
-    echo "console=tty1" > ${BOOT_DATA}/cmdline.txt
-}
-
-
-function hassos_post_image() {
-    convert_disk_image_vmdk
-    convert_disk_image_gz vmdk
-}
-

buildroot-external/board/ova/kernel.config

@@ -1,9 +0,0 @@
-CONFIG_EFI_STUB=y
-
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_BLK=m
-

buildroot-external/board/raspberrypi/hassos-hook.sh

@@ -1,25 +1,26 @@
 #!/bin/bash
+# shellcheck disable=SC2155
 
 function hassos_pre_image() {
     local BOOT_DATA="$(path_boot_dir)"
 
-    cp -t ${BOOT_DATA} \
-        ${BINARIES_DIR}/u-boot.bin \
-        ${BINARIES_DIR}/boot.scr
-    cp -t ${BOOT_DATA} \
-        ${BINARIES_DIR}/*.dtb \
-        ${BINARIES_DIR}/rpi-firmware/bootcode.bin \
-        ${BINARIES_DIR}/rpi-firmware/fixup.dat \
-        ${BINARIES_DIR}/rpi-firmware/start.elf
-    cp -r ${BINARIES_DIR}/rpi-firmware/overlays ${BOOT_DATA}/
-    cp -f ${BOARD_DIR}/../boot-env.txt ${BOOT_DATA}/config.txt
+    cp -t "${BOOT_DATA}" \
+        "${BINARIES_DIR}/u-boot.bin" \
+        "${BINARIES_DIR}/boot.scr"
+    cp -t "${BOOT_DATA}" \
+        "${BINARIES_DIR}"/*.dtb \
+        "${BINARIES_DIR}/rpi-firmware/bootcode.bin" \
+        "${BINARIES_DIR}/rpi-firmware/fixup.dat" \
+        "${BINARIES_DIR}/rpi-firmware/start.elf"
+    cp -r "${BINARIES_DIR}/rpi-firmware/overlays" "${BOOT_DATA}/"
+    cp -f "${BOARD_DIR}/../boot-env.txt" "${BOOT_DATA}/config.txt"
 
     # Set cmd options
-    echo "dwc_otg.lpm_enable=0 console=tty1" > ${BOOT_DATA}/cmdline.txt
+    echo "dwc_otg.lpm_enable=0 console=tty1" > "${BOOT_DATA}/cmdline.txt"
 
     # Enable 64bit support
     if [ "${BOARD_ID}" == "rpi3-64" ]; then
-        echo "arm_64bit=1" >> ${BOOT_DATA}/config.txt
+        echo "arm_64bit=1" >> "${BOOT_DATA}/config.txt"
     fi
 }