b0d9496595
* Add ODROID-M1 board support * Add Rockchip kernel config for ODROID-M1 Kernel defconfig for Rockchip is based on Armbian kernel defconfig from config/kernel/linux-rk3568-odroid-edge.config (git hash 95c829f9e664). * Add U-Boot/Kernel patches * Add Rockchip blob support Add package which provides Rockchip TPL and ATF firmware binaries. * Use latest U-Boot for ODROID-M1 * Fix Rockchip blob support * Update defconfig * Use GPT by default * Create uboot partition to support non-recovery boot * Enable eMMC boot in U-Boot SPL * Drop unnecessary mmc device selection Distro boot already activates the right mmc device. The extra selection seems to actually cause problems for eMMC boot. * Make sure driver for eMMC is built-in * Use odroid-m1 as Supervisor machine * Add ODROID-M1 to CI pipeline and issue template * Bump to Linux 6.1.16
81 lines
2.4 KiB
Diff
81 lines
2.4 KiB
Diff
From 1572a9c5d9fa9f654fbc1909528ae5940ad34aa3 Mon Sep 17 00:00:00 2001
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Message-Id: <1572a9c5d9fa9f654fbc1909528ae5940ad34aa3.1678107917.git.stefan@agner.ch>
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In-Reply-To: <d388735d551e09b00317a509859fca51776b9826.1678107917.git.stefan@agner.ch>
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References: <d388735d551e09b00317a509859fca51776b9826.1678107917.git.stefan@agner.ch>
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Fri, 30 Sep 2022 07:12:45 +0200
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Subject: [PATCH] arm64: dts: rockchip: Add PCIEe v3 nodes to ODROID-M1
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Add nodes to ODROID-M1 to support PCIe v3 on the M2 slot.
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Tested-by: Dan Johansen <strit@manjaro.org>
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Link: https://lore.kernel.org/r/20220930051246.391614-13-aurelien@aurel32.net
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3568-odroid-m1.dts | 34 +++++++++++++++++++
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1 file changed, 34 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
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index bd24ccf94e76..2f685c606bb9 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
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@@ -96,6 +96,19 @@ simple-audio-card,codec {
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};
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};
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+ vcc3v3_pcie: vcc3v3-pcie-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_pcie";
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc3v3_pcie_en_pin>;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <5000>;
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+ vin-supply = <&vcc3v3_sys>;
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+ };
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+
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vcc3v3_sys: vcc3v3-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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@@ -479,6 +492,18 @@ rgmii_phy0: ethernet-phy@0 {
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};
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};
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+&pcie30phy {
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+ status = "okay";
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+};
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+
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+&pcie3x2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_reset_pin>;
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+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie>;
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+ status = "okay";
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+};
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+
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&pinctrl {
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fspi {
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fspi_dual_io_pins: fspi-dual-io-pins {
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@@ -503,6 +528,15 @@ led_work_pin: led-work-pin {
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};
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};
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+ pcie {
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+ pcie_reset_pin: pcie-reset-pin {
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+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
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+ rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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pmic {
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pmic_int_l: pmic-int-l {
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rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
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--
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2.39.2
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