59 lines
1.6 KiB
Diff
59 lines
1.6 KiB
Diff
From f2a63a3b9c1b18a5917973fc57be353118905a66 Mon Sep 17 00:00:00 2001
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Message-Id: <f2a63a3b9c1b18a5917973fc57be353118905a66.1648505253.git.stefan@agner.ch>
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In-Reply-To: <017d6caf5d4e0b0963109633e191f49d7814165e.1648505253.git.stefan@agner.ch>
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References: <017d6caf5d4e0b0963109633e191f49d7814165e.1648505253.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Thu, 4 Mar 2021 14:33:09 +0100
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Subject: [PATCH 2/9] ARM: dts: bcm2711: yellow: Mux UART4 for SiLabs radio
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module
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Enable UART4 by default and mux pins including hardware flow control.
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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arch/arm/boot/dts/bcm2711-rpi-cm4-ha-yellow.dts | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-ha-yellow.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4-ha-yellow.dts
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index 9e7a66e70197..8aee09ac48d7 100644
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--- a/arch/arm/boot/dts/bcm2711-rpi-cm4-ha-yellow.dts
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+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4-ha-yellow.dts
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@@ -21,6 +21,7 @@ memory@0 {
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};
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aliases {
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+ serial4 = &uart4;
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emmc2bus = &emmc2bus;
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ethernet0 = &genet;
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pcie0 = &pcie0;
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@@ -322,6 +323,14 @@ &uart1 {
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status = "okay";
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};
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+/* uart4 for Zigbee */
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+&uart4 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart4_pins>;
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+ uart-has-rtscts;
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+ status = "okay";
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+};
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+
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&vchiq {
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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@@ -549,9 +558,9 @@ uart3_pins: uart3_pins {
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};
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uart4_pins: uart4_pins {
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- brcm,pins = <8 9>;
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+ brcm,pins = <8 9 10 11>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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- brcm,pull = <0 2>;
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+ brcm,pull = <0 2 2 0>;
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};
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uart5_pins: uart5_pins {
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--
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2.35.1
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