127 lines
4.2 KiB
Diff
127 lines
4.2 KiB
Diff
From fa6cb8f89a7f9387a0299f6b55bc0cd54233aefd Mon Sep 17 00:00:00 2001
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Thu, 22 Nov 2018 17:27:20 +0100
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Subject: [PATCH 51/53] drm/meson: Fix an Alpha Primary Plane bug on Meson
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GXL/GXM SoCs
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On the Amlogic GXL & GXM SoCs, a bug occurs in the OSD1 plane when
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alpha is used where the alpha is not aligned with the pixel content.
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The woraround Amlogic implemented is the reset the OSD1 plane hardware
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block each time the plane is updated, solving the issue.
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In the reset, we still need to save the content of 2 registers which
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depends on the status of the plane, in addition to reload the scaler
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conversion matrix in the same time.
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/gpu/drm/meson/meson_crtc.c | 1 +
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drivers/gpu/drm/meson/meson_plane.c | 12 ++++++++++++
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drivers/gpu/drm/meson/meson_viu.c | 27 +++++++++++++++++++++++++++
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drivers/gpu/drm/meson/meson_viu.h | 1 +
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4 files changed, 41 insertions(+)
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diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
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index 23df4abd95c9..f13e5b6b7a50 100644
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--- a/drivers/gpu/drm/meson/meson_crtc.c
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+++ b/drivers/gpu/drm/meson/meson_crtc.c
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@@ -183,6 +183,7 @@ void meson_crtc_irq(struct meson_drm *priv)
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/* Update the OSD registers */
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if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
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+
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writel_relaxed(priv->viu.osd1_ctrl_stat,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel_relaxed(priv->viu.osd1_blk0_cfg[0],
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diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
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index 12a47b4f65a5..837228847675 100644
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--- a/drivers/gpu/drm/meson/meson_plane.c
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+++ b/drivers/gpu/drm/meson/meson_plane.c
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@@ -79,6 +79,7 @@
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struct meson_plane {
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struct drm_plane base;
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struct meson_drm *priv;
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+ bool enabled;
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};
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#define to_meson_plane(x) container_of(x, struct meson_plane, base)
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@@ -303,6 +304,15 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
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priv->viu.osd1_stride = fb->pitches[0];
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priv->viu.osd1_height = fb->height;
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+ if (!meson_plane->enabled) {
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+ /* Reset OSD1 at updates on GXL+ SoCs */
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+ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
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+ meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
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+ meson_viu_reset(priv);
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+
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+ meson_plane->enabled = true;
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+ }
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+
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spin_unlock_irqrestore(&priv->drm->event_lock, flags);
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}
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@@ -316,6 +326,8 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
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writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
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priv->io_base + _REG(VPP_MISC));
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+ meson_plane->enabled = false;
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+
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}
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static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
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diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
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index 90d9ae3c2b81..366f7e523d15 100644
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--- a/drivers/gpu/drm/meson/meson_viu.c
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+++ b/drivers/gpu/drm/meson/meson_viu.c
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@@ -296,6 +296,33 @@ static void meson_viu_load_matrix(struct meson_drm *priv)
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true);
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}
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+/* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */
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+void meson_viu_reset(struct meson_drm *priv)
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+{
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+ uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2;
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+
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+ /* Save these 2 registers state */
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+ osd1_fifo_ctrl_stat = readl_relaxed(
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+ priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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+ osd1_ctrl_stat2 = readl_relaxed(
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+ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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+
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+ /* Reset OSD1 */
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+ writel_bits_relaxed(BIT(0), BIT(0),
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+ priv->io_base + _REG(VIU_SW_RESET));
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+ writel_bits_relaxed(BIT(0), 0,
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+ priv->io_base + _REG(VIU_SW_RESET));
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+
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+ /* Rewrite these registers state lost in the reset */
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+ writel_relaxed(osd1_fifo_ctrl_stat,
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+ priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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+ writel_relaxed(osd1_ctrl_stat2,
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+ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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+
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+ /* Reload the conversion matrix */
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+ meson_viu_load_matrix(priv);
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+}
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+
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void meson_viu_init(struct meson_drm *priv)
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{
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uint32_t reg;
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diff --git a/drivers/gpu/drm/meson/meson_viu.h b/drivers/gpu/drm/meson/meson_viu.h
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index 073b1910bd1b..e4a6e2fba8fb 100644
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--- a/drivers/gpu/drm/meson/meson_viu.h
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+++ b/drivers/gpu/drm/meson/meson_viu.h
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@@ -59,6 +59,7 @@
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#define OSD_REPLACE_EN BIT(14)
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#define OSD_REPLACE_SHIFT 6
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+void meson_viu_reset(struct meson_drm *priv);
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void meson_viu_init(struct meson_drm *priv);
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#endif /* __MESON_VIU_H */
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--
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2.17.1
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