45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
From 8bb24f445a3b532a06a1d5bde70daad0c4f3da4f Mon Sep 17 00:00:00 2001
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From: Christian Hewitt <christianshewitt@gmail.com>
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Date: Sat, 13 Oct 2018 14:04:46 +0400
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Subject: [PATCH 40/53] clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL
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On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
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with reboot; e.g. a ~60 second delay between issuing reboot and the
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board power cycling (and in some OS configurations reboot will fail
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and require manual power cycling).
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Similar to 'commit c987ac6f1f088663b6dad39281071aeb31d450a8 ("clk:
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meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL")' the SCPI Cortex-M4
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Co-Processor seems to depend on FCLK_DIV3 being operational.
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Bisect gives 'commit 05f814402d6174369b3b29832cbb5eb5ed287059 ("clk:
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meson: add fdiv clock gates") between 4.16 and 4.16-rc1 as the first
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bad commit. This added support for the missing clock gates before the
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fixed PLL fixed dividers (FCLK_DIVx) and the clock framework which
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disabled all the unused fixed dividers, thus it disabled a critical
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clock path for the SCPI Co-Processor.
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This change simply sets the FCLK_DIV3 gate as critical to ensure
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nothing can disable it.
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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
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---
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drivers/clk/meson/gxbb.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
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index 4d4f6d842c31..a6fae1c00df3 100644
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--- a/drivers/clk/meson/gxbb.c
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+++ b/drivers/clk/meson/gxbb.c
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@@ -513,6 +513,7 @@ static struct clk_fixed_factor gxbb_fclk_div3_div = {
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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+ .flags = CLK_IS_CRITICAL,
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},
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};
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--
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2.17.1
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