78152db78f
* Backport USB PCIe/XHCI patches to U-Boot 2020.07 Backport relevant patches required to make PCIe/USB XHCI work. * Backport/integrate PCIe device tree changes from upstream Linux U-Boot uses the device tree provided by upstream Linux. Make sure the device tree has the relevant chanages to make VL805 USB controller reset work. * Document RPi 4 USB mass storage support (#746)
86 lines
2.9 KiB
Diff
86 lines
2.9 KiB
Diff
From a8c492ef2a3a73d435765ce28944efebce5cfa17 Mon Sep 17 00:00:00 2001
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Message-Id: <a8c492ef2a3a73d435765ce28944efebce5cfa17.1595101389.git.stefan@agner.ch>
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In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
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References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
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From: Marek Szyprowski <m.szyprowski@samsung.com>
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Date: Wed, 3 Jun 2020 14:43:44 +0200
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Subject: [PATCH 19/20] rpi4: add a mapping for the PCIe XHCI controller MMIO
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registers (ARM 32bit)
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Create a non-cacheable mapping for the 0x600000000 physical memory region,
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where MMIO registers for the PCIe XHCI controller are instantiated by the
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PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
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32bit mode, this region is mapped at 0xff800000 CPU virtual address.
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Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
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---
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arch/arm/mach-bcm283x/Kconfig | 1 +
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arch/arm/mach-bcm283x/include/mach/base.h | 8 ++++++++
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arch/arm/mach-bcm283x/init.c | 21 +++++++++++++++++++++
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3 files changed, 30 insertions(+)
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diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
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index e6eb904e7f..b3287ce8bc 100644
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--- a/arch/arm/mach-bcm283x/Kconfig
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+++ b/arch/arm/mach-bcm283x/Kconfig
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@@ -36,6 +36,7 @@ config BCM2711_32B
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select BCM2711
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select ARMV7_LPAE
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select CPU_V7A
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+ select PHYS_64BIT
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config BCM2711_64B
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bool "Broadcom BCM2711 SoC 64-bit support"
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diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
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index c4ae39852f..4ccaf69693 100644
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--- a/arch/arm/mach-bcm283x/include/mach/base.h
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+++ b/arch/arm/mach-bcm283x/include/mach/base.h
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@@ -8,4 +8,12 @@
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extern unsigned long rpi_bcm283x_base;
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+#ifdef CONFIG_ARMV7_LPAE
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+#ifdef CONFIG_TARGET_RPI_4_32B
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+#include <addr_map.h>
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+#define phys_to_virt addrmap_phys_to_virt
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+#define virt_to_phys addrmap_virt_to_phys
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+#endif
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+#endif
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+
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#endif
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diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
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index cf4c5b245d..f2a5411623 100644
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--- a/arch/arm/mach-bcm283x/init.c
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+++ b/arch/arm/mach-bcm283x/init.c
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@@ -146,6 +146,27 @@ int mach_cpu_init(void)
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}
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#ifdef CONFIG_ARMV7_LPAE
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+#ifdef CONFIG_TARGET_RPI_4_32B
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+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
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+#include <addr_map.h>
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+#include <asm/system.h>
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+
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+void init_addr_map(void)
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+{
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+ mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
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+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
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+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
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+ DCACHE_OFF);
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+
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+ /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
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+ addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
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+ /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
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+ addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
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+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
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+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
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+}
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+#endif
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+
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void enable_caches(void)
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{
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dcache_enable();
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--
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2.27.0
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