60 lines
2.5 KiB
Diff
60 lines
2.5 KiB
Diff
From ed5a66c3f22d0f01c4f71371714af4180e65b37d Mon Sep 17 00:00:00 2001
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Message-Id: <ed5a66c3f22d0f01c4f71371714af4180e65b37d.1607085588.git.stefan@agner.ch>
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In-Reply-To: <a04331a6ba7334282836bbaa76e979c4e6be3900.1607085588.git.stefan@agner.ch>
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References: <a04331a6ba7334282836bbaa76e979c4e6be3900.1607085588.git.stefan@agner.ch>
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Date: Thu, 19 Nov 2020 18:48:17 +0100
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Subject: [PATCH 11/16] pci: pcie-brcmstb: Fix inbound window configurations
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So far we've assumed a fixed configuration for inbound windows as we had
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a single user for this controller. But the controller's DMA constraints
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were improved starting with BCM2711's B1 revision of the SoC, notably
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available in CM4 and Pi400. They allow for wider inbound windows. We can
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now cover the whole address space, whereas before we where limited to
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the lower 3GB.
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This information is passed to us through DT's 'dma-ranges' property and
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it's specially important for us to honor it them since some interactions
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with the board's co-processor assume we're doing so (specifically the
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XHCI firmware load operation, which is handled by the co-processor after
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u-boot has correctly configured the PCIe controller).
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Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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---
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drivers/pci/pcie_brcmstb.c | 12 +++++-------
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1 file changed, 5 insertions(+), 7 deletions(-)
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diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c
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index dade79e9c8..f6e8ad0d0a 100644
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--- a/drivers/pci/pcie_brcmstb.c
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+++ b/drivers/pci/pcie_brcmstb.c
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@@ -432,6 +432,7 @@ static int brcm_pcie_probe(struct udevice *dev)
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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struct brcm_pcie *pcie = dev_get_priv(dev);
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void __iomem *base = pcie->base;
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+ struct pci_region region;
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bool ssc_good = false;
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int num_out_wins = 0;
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u64 rc_bar2_offset, rc_bar2_size;
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@@ -468,13 +469,10 @@ static int brcm_pcie_probe(struct udevice *dev)
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MISC_CTRL_SCB_ACCESS_EN_MASK |
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MISC_CTRL_CFG_READ_UR_MODE_MASK |
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MISC_CTRL_MAX_BURST_SIZE_128);
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- /*
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- * TODO: When support for other SoCs than BCM2711 is added we may
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- * need to use the base address and size(s) provided in the dma-ranges
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- * property.
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- */
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- rc_bar2_offset = 0;
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- rc_bar2_size = 0xc0000000;
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+
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+ pci_get_dma_regions(dev, ®ion, 0);
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+ rc_bar2_offset = region.bus_start - region.phys_start;
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+ rc_bar2_size = 1ULL << fls64(region.size - 1);
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tmp = lower_32_bits(rc_bar2_offset);
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u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
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--
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2.29.2
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