120 lines
4.3 KiB
Diff
120 lines
4.3 KiB
Diff
diff -ur a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
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--- a/drivers/gpu/drm/meson/meson_vclk.c 2018-06-02 20:21:48.000000000 +0200
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+++ b/drivers/gpu/drm/meson/meson_vclk.c 2018-06-02 20:16:44.008061996 +0200
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@@ -428,9 +428,9 @@
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.vclk_div = 2,
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},
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[MESON_VCLK_HDMI_32000] = {
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- .pll_base_freq = 2560000,
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+ .pll_base_freq = 5120000,
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.pll_od1 = 4,
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- .pll_od2 = 2,
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+ .pll_od2 = 4,
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.pll_od3 = 1,
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.vid_pll_div = VID_PLL_DIV_5,
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.vclk_div = 2,
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@@ -520,27 +520,6 @@
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
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switch (base) {
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- case 2560000:
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000235);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
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-
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- /* Enable and unreset */
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- regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
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- 0x7 << 28, 0x4 << 28);
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-
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- /* Poll for lock bit */
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- regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
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- val, (val & HDMI_PLL_LOCK), 10, 0);
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-
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- /* div_frac */
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- regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
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- 0xFFFF, 0x4555);
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- break;
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-
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case 2700000:
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000238);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
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@@ -722,6 +701,27 @@
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val, (val & HDMI_PLL_LOCK), 10, 0);
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break;
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+ case 5120000:
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800026a);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x135c5091);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
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+
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+ /* unreset */
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+ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
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+ BIT(28), 0);
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+
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+ /* Poll for lock bit */
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+ regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
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+ val, (val & HDMI_PLL_LOCK), 10, 0);
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+
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+ /* div_frac */
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+ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
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+ 0xFFFF, 0x4aab);
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+ break;
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+
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case 5940000:
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800027b);
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regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
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@@ -760,15 +760,6 @@
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} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
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meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
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switch (base) {
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- case 2560000:
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000026a);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb2ab);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
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- regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
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- break;
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-
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case 2700000:
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000270);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb200);
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@@ -847,6 +838,15 @@
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
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+ break;
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+
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+ case 5120000:
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002d5);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb155);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
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+ regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
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break;
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diff -ur a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
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--- a/drivers/gpu/drm/meson/meson_venc.c 2018-06-02 16:39:27.777402009 +0200
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+++ b/drivers/gpu/drm/meson/meson_venc.c 2018-06-02 20:23:23.744646670 +0200
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@@ -713,6 +713,12 @@
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968, 1056, 0, 600, 601, 605, 628, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
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},
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+ /* 1024x600@43Hz */
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+ {
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+ { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 32000, 1024,
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+ 1064, 1112, 1152, 0, 600, 613, 616, 645, 0,
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+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
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+ },
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/* 1024x768@60Hz */
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{
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{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024,
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