b3530d1ce1
* Allow easy move data partition * Cleanup handling systemd * Improve handling * fix pipeline * pipeline * fix shell handling * fix scripts * Add bin folder * fix lint * Fix service handling * Fix loading * hide output * Fix handling
40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
From 81b290367d59103d1f041709c56a3de1c360e102 Mon Sep 17 00:00:00 2001
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From: Jerome Brunet <jbrunet@baylibre.com>
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Date: Mon, 13 May 2019 14:45:31 +0200
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Subject: [PATCH] FROMLIST: clk: meson: g12a: fix gp0 and hifi ranges
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While some SoC samples are able to lock with a PLL factor of 55, others
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samples can't. ATM, a minimum of 60 appears to work on all the samples
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I have tried.
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Even with 60, it sometimes takes a long time for the PLL to eventually
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lock. The documentation says that the minimum rate of these PLLs DCO
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should be 3GHz, a factor of 125. Let's use that to be on the safe side.
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With factor range changed, the PLL seems to lock quickly (enough) so far.
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It is still unclear if the range was the only reason for the delay.
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Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
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Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/clk/meson/g12a.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
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index b3af61cc6fb9..66cf791bfc8c 100644
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--- a/drivers/clk/meson/g12a.c
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+++ b/drivers/clk/meson/g12a.c
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@@ -1591,7 +1591,7 @@ static struct clk_regmap g12b_cpub_clk_trace = {
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};
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static const struct pll_mult_range g12a_gp0_pll_mult_range = {
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- .min = 55,
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+ .min = 125,
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.max = 255,
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};
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--
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2.17.1
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