84 lines
2.5 KiB
Diff
84 lines
2.5 KiB
Diff
From 6eeaf4d2452ec8b1ece58776812140734fc2e088 Mon Sep 17 00:00:00 2001
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From: Frank Hartung <supervisedthinking@gmail.com>
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Date: Sat, 14 Sep 2019 06:49:40 +0400
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Subject: [PATCH] arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B
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Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs
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are equal; the A53s cores are weaker than the A72s.
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Include capacity-dmips-mhz properties to tell the OS there is a difference
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in processing capacity. The dmips values are based on similar submissions for
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other A53/A72 SoCs: HiSilicon 3660 [1] and Rockchip RK3399 [2].
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This change is particularly beneficial for use-cases like retro gaming where
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emulators often run on a single core. The OS now chooses an A72 core instead
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of an A53 core.
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[1] https://lore.kernel.org/patchwork/patch/862742/
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[2] https://patchwork.kernel.org/patch/10836577/
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Signed-off-by: Frank Hartung <supervisedthinking@gmail.com>
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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
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Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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Reviewed-by: Kevin Hilman <khilman@baylibre.com>
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Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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---
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arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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index a9e1db0f1158..b3f9e3a02963 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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@@ -48,6 +48,7 @@
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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+ capacity-dmips-mhz = <592>;
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next-level-cache = <&l2>;
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};
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@@ -56,6 +57,7 @@
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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+ capacity-dmips-mhz = <592>;
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next-level-cache = <&l2>;
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};
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@@ -64,6 +66,7 @@
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compatible = "arm,cortex-a73";
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reg = <0x0 0x100>;
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enable-method = "psci";
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+ capacity-dmips-mhz = <1024>;
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next-level-cache = <&l2>;
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};
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@@ -72,6 +75,7 @@
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compatible = "arm,cortex-a73";
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reg = <0x0 0x101>;
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enable-method = "psci";
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+ capacity-dmips-mhz = <1024>;
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next-level-cache = <&l2>;
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};
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@@ -80,6 +84,7 @@
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compatible = "arm,cortex-a73";
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reg = <0x0 0x102>;
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enable-method = "psci";
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+ capacity-dmips-mhz = <1024>;
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next-level-cache = <&l2>;
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};
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@@ -88,6 +93,7 @@
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compatible = "arm,cortex-a73";
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reg = <0x0 0x103>;
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enable-method = "psci";
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+ capacity-dmips-mhz = <1024>;
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next-level-cache = <&l2>;
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};
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--
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2.17.1
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