78152db78f
* Backport USB PCIe/XHCI patches to U-Boot 2020.07 Backport relevant patches required to make PCIe/USB XHCI work. * Backport/integrate PCIe device tree changes from upstream Linux U-Boot uses the device tree provided by upstream Linux. Make sure the device tree has the relevant chanages to make VL805 USB controller reset work. * Document RPi 4 USB mass storage support (#746)
131 lines
4.3 KiB
Diff
131 lines
4.3 KiB
Diff
From 82a944e4d1356e9ab3c87e6dc57b1b7213cbb233 Mon Sep 17 00:00:00 2001
|
|
Message-Id: <82a944e4d1356e9ab3c87e6dc57b1b7213cbb233.1595101389.git.stefan@agner.ch>
|
|
In-Reply-To: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
|
|
References: <040a141f84f2f84bf8be18f85b4cdb34bf066df0.1595101389.git.stefan@agner.ch>
|
|
From: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
Date: Wed, 3 Jun 2020 14:43:42 +0200
|
|
Subject: [PATCH 17/20] arm: provide a function for boards init code to modify
|
|
MMU virtual-physical map
|
|
|
|
Provide function for setting arbitrary virtual-physical MMU mapping
|
|
and cache settings for the given region.
|
|
|
|
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
|
|
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
---
|
|
arch/arm/include/asm/mmu.h | 8 ++++++++
|
|
arch/arm/include/asm/system.h | 13 +++++++++++++
|
|
arch/arm/lib/cache-cp15.c | 24 ++++++++++++++++++------
|
|
3 files changed, 39 insertions(+), 6 deletions(-)
|
|
create mode 100644 arch/arm/include/asm/mmu.h
|
|
|
|
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
|
|
new file mode 100644
|
|
index 0000000000..9ac16f599e
|
|
--- /dev/null
|
|
+++ b/arch/arm/include/asm/mmu.h
|
|
@@ -0,0 +1,8 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0+ */
|
|
+
|
|
+#ifndef __ASM_ARM_MMU_H
|
|
+#define __ASM_ARM_MMU_H
|
|
+
|
|
+void init_addr_map(void);
|
|
+
|
|
+#endif
|
|
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
|
|
index 0243f76e76..f9290fa9b6 100644
|
|
--- a/arch/arm/include/asm/system.h
|
|
+++ b/arch/arm/include/asm/system.h
|
|
@@ -585,6 +585,19 @@ s32 psci_features(u32 function_id, u32 psci_fid);
|
|
*/
|
|
void save_boot_params_ret(void);
|
|
|
|
+/**
|
|
+ * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
|
|
+ *
|
|
+ * Change the virt/phys mapping and cache settings for a region.
|
|
+ *
|
|
+ * @virt: virtual start address of memory region to change
|
|
+ * @phys: physical address for the memory region to set
|
|
+ * @size: size of memory region to change
|
|
+ * @option: dcache option to select
|
|
+ */
|
|
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
|
|
+ size_t size, enum dcache_option option);
|
|
+
|
|
/**
|
|
* mmu_set_region_dcache_behaviour() - set cache settings
|
|
*
|
|
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
|
|
index 1da2e92fe2..39717610d4 100644
|
|
--- a/arch/arm/lib/cache-cp15.c
|
|
+++ b/arch/arm/lib/cache-cp15.c
|
|
@@ -25,7 +25,8 @@ __weak void arm_init_domains(void)
|
|
{
|
|
}
|
|
|
|
-void set_section_dcache(int section, enum dcache_option option)
|
|
+static void set_section_phys(int section, phys_addr_t phys,
|
|
+ enum dcache_option option)
|
|
{
|
|
#ifdef CONFIG_ARMV7_LPAE
|
|
u64 *page_table = (u64 *)gd->arch.tlb_addr;
|
|
@@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option)
|
|
#endif
|
|
|
|
/* Add the page offset */
|
|
- value |= ((u32)section << MMU_SECTION_SHIFT);
|
|
+ value |= phys;
|
|
|
|
/* Add caching bits */
|
|
value |= option;
|
|
@@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option)
|
|
page_table[section] = value;
|
|
}
|
|
|
|
+void set_section_dcache(int section, enum dcache_option option)
|
|
+{
|
|
+ set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
|
|
+}
|
|
+
|
|
__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
|
|
{
|
|
debug("%s: Warning: not implemented\n", __func__);
|
|
}
|
|
|
|
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
- enum dcache_option option)
|
|
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
|
|
+ size_t size, enum dcache_option option)
|
|
{
|
|
#ifdef CONFIG_ARMV7_LPAE
|
|
u64 *page_table = (u64 *)gd->arch.tlb_addr;
|
|
@@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
|
|
option);
|
|
#endif
|
|
- for (upto = start; upto < end; upto++)
|
|
- set_section_dcache(upto, option);
|
|
+ for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
|
|
+ set_section_phys(upto, phys, option);
|
|
|
|
/*
|
|
* Make sure range is cache line aligned
|
|
@@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
mmu_page_table_flush(startpt, stoppt);
|
|
}
|
|
|
|
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
+ enum dcache_option option)
|
|
+{
|
|
+ mmu_set_region_dcache_behaviour_phys(start, start, size, option);
|
|
+}
|
|
+
|
|
__weak void dram_bank_mmu_setup(int bank)
|
|
{
|
|
bd_t *bd = gd->bd;
|
|
--
|
|
2.27.0
|
|
|