From d4ee727abd9ef7d25be34aab68fe06ee977d9815 Mon Sep 17 00:00:00 2001 From: d-two Date: Tue, 28 Mar 2023 22:51:41 +0200 Subject: [PATCH] =?UTF-8?q?Dateien=20hochladen=20nach=20=E2=80=9Ebuildroot?= =?UTF-8?q?-external/board/amlogic/patches/uboot=E2=80=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../amlogic/patches/uboot/000_amlogic.patch | 1632 +++++++++++++++++ 1 file changed, 1632 insertions(+) create mode 100644 buildroot-external/board/amlogic/patches/uboot/000_amlogic.patch diff --git a/buildroot-external/board/amlogic/patches/uboot/000_amlogic.patch b/buildroot-external/board/amlogic/patches/uboot/000_amlogic.patch new file mode 100644 index 000000000..bef1d4b1c --- /dev/null +++ b/buildroot-external/board/amlogic/patches/uboot/000_amlogic.patch @@ -0,0 +1,1632 @@ +diff -ruN u-boot-2022.01/arch/arm/dts/Makefile u-boot-master/arch/arm/dts/Makefile +--- u-boot-2022.01/arch/arm/dts/Makefile 2022-01-10 19:46:34.000000000 +0100 ++++ u-boot-master/arch/arm/dts/Makefile 2022-03-27 09:06:29.000000000 +0200 +@@ -196,7 +196,10 @@ + meson-sm1-khadas-vim3l.dtb \ + meson-sm1-odroid-c4.dtb \ + meson-sm1-odroid-hc4.dtb \ +- meson-sm1-sei610.dtb ++ meson-sm1-sei610.dtb \ ++ meson-sm1-x96-max-plus.dtb \ ++ meson-sm1-hk1box-vontar-x3.dtb \ ++ meson-sm1-h96-max-x3.dtb + dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-ac2xx.dtsi u-boot-master/arch/arm/dts/meson-sm1-ac2xx.dtsi +--- u-boot-2022.01/arch/arm/dts/meson-sm1-ac2xx.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-ac2xx.dtsi 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,300 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre SAS. All rights reserved. ++ * Copyright (c) 2020 Christian Hewitt ++ * ++ * AC200/AC202 = S905D3 ++ * AC213/AC214 = S905X3 ++ * ++ */ ++ ++#include "meson-sm1.dtsi" ++#include ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart_AO; ++ ethernet0 = ðmac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ emmc_pwrseq: emmc-pwrseq { ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ cvbs-connector { ++ compatible = "composite-video-connector"; ++ ++ port { ++ cvbs_connector_in: endpoint { ++ remote-endpoint = <&cvbs_vdac_out>; ++ }; ++ }; ++ }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_connector_in: endpoint { ++ remote-endpoint = <&hdmi_tx_tmds_out>; ++ }; ++ }; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x0 0x40000000>; ++ }; ++ ++ ao_5v: regulator-ao_5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "AO_5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_in>; ++ regulator-always-on; ++ }; ++ ++ dc_in: regulator-dc_in { ++ compatible = "regulator-fixed"; ++ regulator-name = "DC_IN"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ emmc_1v8: regulator-emmc_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "EMMC_1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ vddao_3v3: regulator-vddao_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDAO_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_in>; ++ regulator-always-on; ++ }; ++ ++ vddcpu: regulator-vddcpu { ++ compatible = "pwm-regulator"; ++ ++ regulator-name = "VDDCPU"; ++ regulator-min-microvolt = <690000>; ++ regulator-max-microvolt = <1050000>; ++ ++ vin-supply = <&dc_in>; ++ ++ pwms = <&pwm_AO_cd 1 1500 0>; ++ pwm-dutycycle-range = <100 0>; ++ ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vddio_ao1v8: regulator-vddio_ao1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDDIO_AO1V8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vddao_3v3>; ++ regulator-always-on; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; ++ clocks = <&wifi32k>; ++ clock-names = "ext_clock"; ++ }; ++ ++ wifi32k: wifi32k { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ ++ }; ++}; ++ ++&cec_AO { ++ pinctrl-0 = <&cec_ao_a_h_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++&cecb_AO { ++ pinctrl-0 = <&cec_ao_b_h_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ hdmi-phandle = <&hdmi_tx>; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU1_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU2_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vddcpu>; ++ operating-points-v2 = <&cpu_opp_table>; ++ clocks = <&clkc CLKID_CPU3_CLK>; ++ clock-latency = <50000>; ++}; ++ ++&cvbs_vdac_port { ++ cvbs_vdac_out: endpoint { ++ remote-endpoint = <&cvbs_connector_in>; ++ }; ++}; ++ ++&hdmi_tx { ++ status = "okay"; ++ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&hdmi_tx_tmds_port { ++ hdmi_tx_tmds_out: endpoint { ++ remote-endpoint = <&hdmi_connector_in>; ++ }; ++}; ++ ++&ir { ++ status = "okay"; ++ pinctrl-0 = <&remote_input_ao_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&pwm_AO_ab { ++ status = "okay"; ++ pinctrl-0 = <&pwm_ao_a_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin0"; ++}; ++ ++&pwm_AO_cd { ++ pinctrl-0 = <&pwm_ao_d_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin1"; ++ status = "okay"; ++}; ++ ++&pwm_ef { ++ status = "okay"; ++ pinctrl-0 = <&pwm_e_pins>; ++ pinctrl-names = "default"; ++ clocks = <&xtal>; ++ clock-names = "clkin0"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vddio_ao1v8>; ++}; ++ ++/* SDIO */ ++&sd_emmc_a { ++ status = "okay"; ++ pinctrl-0 = <&sdio_pins>; ++ pinctrl-1 = <&sdio_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr104; ++ max-frequency = <200000000>; ++ ++ non-removable; ++ disable-wp; ++ ++ /* WiFi firmware requires power to be kept while in suspend */ ++ keep-power-in-suspend; ++ ++ mmc-pwrseq = <&sdio_pwrseq>; ++ ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddio_ao1v8>; ++}; ++ ++/* SD Card */ ++&sd_emmc_b { ++ status = "okay"; ++ pinctrl-0 = <&sdcard_c_pins>; ++ pinctrl-1 = <&sdcard_clk_gate_c_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <4>; ++ cap-sd-highspeed; ++ /* CRC errors are observed at 50MHz */ ++ max-frequency = <35000000>; ++ disable-wp; ++ ++ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&vddao_3v3>; ++}; ++ ++/* eMMC */ ++&sd_emmc_c { ++ status = "okay"; ++ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; ++ pinctrl-1 = <&emmc_clk_gate_pins>; ++ pinctrl-names = "default", "clk-gate"; ++ ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ max-frequency = <200000000>; ++ non-removable; ++ disable-wp; ++ ++ mmc-pwrseq = <&emmc_pwrseq>; ++ vmmc-supply = <&vddao_3v3>; ++ vqmmc-supply = <&emmc_1v8>; ++}; ++ ++&uart_AO { ++ status = "okay"; ++ pinctrl-0 = <&uart_ao_a_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&usb { ++ status = "okay"; ++ dr_mode = "otg"; ++}; +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-h96-max-x3.dts u-boot-master/arch/arm/dts/meson-sm1-h96-max-x3.dts +--- u-boot-2022.01/arch/arm/dts/meson-sm1-h96-max-x3.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-h96-max-x3.dts 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,178 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre SAS. All rights reserved. ++ * Copyright (c) 2020 Christian Hewitt ++ * Copyright (c) 2021 flippy ++ */ ++ ++/dts-v1/; ++ ++#include "meson-sm1-ac2xx.dtsi" ++#include ++#include ++ ++/ { ++ compatible = "amlogic,h96max-x3", "amlogic,sm1"; ++ model = "H96 Max X3"; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "H96-MAX"; ++ audio-aux-devs = <&tdmout_b>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ }; ++ ++ /* hdmi glue */ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++ ++ vddgpu: regulator-vddgpu { ++ compatible = "regulator-fixed"; ++ regulator-name = "mali"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ vin-supply = <&ao_5v>; ++ regulator-always-on; ++ }; ++}; ++ ++&vddcpu { ++ regulator-min-microvolt = <721000>; ++ regulator-max-microvolt = <1022000>; ++ pwms = <&pwm_AO_cd 1 1250 0>; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++ðmac { ++ status = "okay"; ++ ++ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ phy-mode = "rgmii"; ++ phy-handle = <&external_phy>; ++ ++ amlogic,tx-delay-ns = <2>; ++}; ++ ++&ext_mdio { ++ external_phy: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ max-speed = <1000>; ++ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <80000>; ++ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_14 */ ++ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&uart_A { ++ status = "okay"; ++ ++ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; ++ max-speed = <2000000>; ++ clocks = <&wifi32k>; ++ clock-names = "lpo"; ++ }; ++}; ++ ++&mali { ++ mali-supply=<&vddgpu>; ++}; ++ ++/* SDIO */ ++&sd_emmc_a { ++ /delete-property/ sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ max-frequency = <100000000>; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ max-frequency = <50000000>; ++}; +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-h96-max-x3-u-boot.dtsi u-boot-master/arch/arm/dts/meson-sm1-h96-max-x3-u-boot.dtsi +--- u-boot-2022.01/arch/arm/dts/meson-sm1-h96-max-x3-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-h96-max-x3-u-boot.dtsi 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS. ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-sm1-u-boot.dtsi" +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-hk1box-vontar-x3.dts u-boot-master/arch/arm/dts/meson-sm1-hk1box-vontar-x3.dts +--- u-boot-2022.01/arch/arm/dts/meson-sm1-hk1box-vontar-x3.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-hk1box-vontar-x3.dts 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,177 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre SAS. All rights reserved. ++ * Copyright (c) 2020 Christian Hewitt ++ * Copyright (c) 2021 flippy ++ */ ++ ++/dts-v1/; ++ ++#include "meson-sm1-ac2xx.dtsi" ++#include ++ ++/ { ++ compatible = "amlogic,hk1box", "amlogic,sm1"; ++ model = "HK1 Box/Vontar X3"; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "HK1-BOX"; ++ audio-aux-devs = <&tdmout_b>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ }; ++ ++ /* hdmi glue */ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++ ++ vddgpu: regulator-vddgpu { ++ compatible = "regulator-fixed"; ++ regulator-name = "mali"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ vin-supply = <&ao_5v>; ++ regulator-always-on; ++ }; ++}; ++ ++&vddcpu { ++ regulator-min-microvolt = <721000>; ++ regulator-max-microvolt = <1022000>; ++ pwms = <&pwm_AO_cd 1 1250 0>; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++ðmac { ++ status = "okay"; ++ ++ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ phy-mode = "rgmii"; ++ phy-handle = <&external_phy>; ++ ++ amlogic,tx-delay-ns = <2>; ++}; ++ ++&ext_mdio { ++ external_phy: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ max-speed = <1000>; ++ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <80000>; ++ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_14 */ ++ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&uart_A { ++ status = "okay"; ++ ++ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; ++ max-speed = <2000000>; ++ clocks = <&wifi32k>; ++ clock-names = "lpo"; ++ }; ++}; ++ ++&mali { ++ mali-supply=<&vddgpu>; ++}; ++ ++/* SDIO */ ++&sd_emmc_a { ++ /delete-property/ sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ max-frequency = <100000000>; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ max-frequency = <50000000>; ++}; +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-hk1box-vontar-x3-u-boot.dtsi u-boot-master/arch/arm/dts/meson-sm1-hk1box-vontar-x3-u-boot.dtsi +--- u-boot-2022.01/arch/arm/dts/meson-sm1-hk1box-vontar-x3-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-hk1box-vontar-x3-u-boot.dtsi 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS. ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-sm1-u-boot.dtsi" +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-x96-max-plus.dts u-boot-master/arch/arm/dts/meson-sm1-x96-max-plus.dts +--- u-boot-2022.01/arch/arm/dts/meson-sm1-x96-max-plus.dts 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-x96-max-plus.dts 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,186 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre SAS. All rights reserved. ++ * Copyright (c) 2020 Christian Hewitt ++ * Copyright (c) 2021 flippy ++ */ ++ ++/dts-v1/; ++ ++#include "meson-sm1-ac2xx.dtsi" ++#include ++ ++/ { ++ compatible = "amediatech,x96-max-plus", "amlogic,sm1"; ++ //model = "Shenzhen Amediatech Technology Co., Ltd X96 Max+"; ++ model = "AMedia X96 Max+"; ++ ++ sound { ++ compatible = "amlogic,axg-sound-card"; ++ model = "X96-MAX"; ++ audio-aux-devs = <&tdmout_b>; ++ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", ++ "TDMOUT_B IN 1", "FRDDR_B OUT 1", ++ "TDMOUT_B IN 2", "FRDDR_C OUT 1", ++ "TDM_B Playback", "TDMOUT_B OUT"; ++ ++ assigned-clocks = <&clkc CLKID_MPLL2>, ++ <&clkc CLKID_MPLL0>, ++ <&clkc CLKID_MPLL1>; ++ assigned-clock-parents = <0>, <0>, <0>; ++ assigned-clock-rates = <294912000>, ++ <270950400>, ++ <393216000>; ++ status = "okay"; ++ ++ dai-link-0 { ++ sound-dai = <&frddr_a>; ++ }; ++ ++ dai-link-1 { ++ sound-dai = <&frddr_b>; ++ }; ++ ++ dai-link-2 { ++ sound-dai = <&frddr_c>; ++ }; ++ ++ /* 8ch hdmi interface */ ++ dai-link-3 { ++ sound-dai = <&tdmif_b>; ++ dai-format = "i2s"; ++ dai-tdm-slot-tx-mask-0 = <1 1>; ++ dai-tdm-slot-tx-mask-1 = <1 1>; ++ dai-tdm-slot-tx-mask-2 = <1 1>; ++ dai-tdm-slot-tx-mask-3 = <1 1>; ++ mclk-fs = <256>; ++ ++ codec { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; ++ }; ++ }; ++ ++ /* hdmi glue */ ++ dai-link-4 { ++ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; ++ ++ codec { ++ sound-dai = <&hdmi_tx>; ++ }; ++ }; ++ }; ++ ++ vddgpu: regulator-vddgpu { ++ compatible = "regulator-fixed"; ++ regulator-name = "mali"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ vin-supply = <&ao_5v>; ++ regulator-always-on; ++ }; ++}; ++ ++&vddcpu { ++ regulator-min-microvolt = <721000>; ++ regulator-max-microvolt = <1022000>; ++ pwms = <&pwm_AO_cd 1 1250 0>; ++}; ++ ++&arb { ++ status = "okay"; ++}; ++ ++&clkc_audio { ++ status = "okay"; ++}; ++ ++ðmac { ++ status = "okay"; ++ ++ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; ++ pinctrl-names = "default"; ++ phy-mode = "rgmii"; ++ phy-handle = <&external_phy>; ++ ++ amlogic,tx-delay-ns = <2>; ++}; ++ ++&ext_mdio { ++ external_phy: ethernet-phy@0 { ++ /* Realtek RTL8211F (0x001cc916) */ ++ reg = <0>; ++ max-speed = <1000>; ++ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <80000>; ++ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; ++ ++ interrupt-parent = <&gpio_intc>; ++ /* MAC_INTR on GPIOZ_14 */ ++ interrupts = <26 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++&frddr_a { ++ status = "okay"; ++}; ++ ++&frddr_b { ++ status = "okay"; ++}; ++ ++&frddr_c { ++ status = "okay"; ++}; ++ ++&ir { ++ linux,rc-map-name = "rc-x96max"; ++}; ++ ++&tdmif_b { ++ status = "okay"; ++}; ++ ++&tdmout_b { ++ status = "okay"; ++}; ++ ++&tohdmitx { ++ status = "okay"; ++}; ++ ++&uart_A { ++ status = "okay"; ++ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ interrupt-parent = <&gpio_intc>; ++ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "host-wakeup"; ++ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; ++ max-speed = <2000000>; ++ clocks = <&wifi32k>; ++ clock-names = "lpo"; ++ vbat-supply = <&vddao_3v3>; ++ vddio-supply = <&vddio_ao1v8>; ++ }; ++}; ++ ++&mali { ++ mali-supply=<&vddgpu>; ++}; ++ ++/* SDIO */ ++&sd_emmc_a { ++ /delete-property/ sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ max-frequency = <100000000>; ++}; ++ ++/* SD card */ ++&sd_emmc_b { ++ max-frequency = <25000000>; ++}; +diff -ruN u-boot-2022.01/arch/arm/dts/meson-sm1-x96-max-plus-u-boot.dtsi u-boot-master/arch/arm/dts/meson-sm1-x96-max-plus-u-boot.dtsi +--- u-boot-2022.01/arch/arm/dts/meson-sm1-x96-max-plus-u-boot.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/arch/arm/dts/meson-sm1-x96-max-plus-u-boot.dtsi 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 BayLibre, SAS. ++ * Author: Neil Armstrong ++ */ ++ ++#include "meson-sm1-u-boot.dtsi" +diff -ruN u-boot-2022.01/board/amlogic/ac2xx/ac2xx.c u-boot-master/board/amlogic/ac2xx/ac2xx.c +--- u-boot-2022.01/board/amlogic/ac2xx/ac2xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/board/amlogic/ac2xx/ac2xx.c 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020 BayLibre, SAS ++ * Author: Neil Armstrong ++ * Editor: flippy ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define EFUSE_MAC_OFFSET 0 ++#define EFUSE_MAC_SIZE 12 ++#define MAC_ADDR_LEN 6 ++ ++int misc_init_r(void) ++{ ++ u8 mac_addr[MAC_ADDR_LEN]; ++ char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3]; ++ ssize_t len; ++ ++ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { ++ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, ++ efuse_mac_addr, EFUSE_MAC_SIZE); ++ if (len != EFUSE_MAC_SIZE) ++ return 0; ++ ++ /* MAC is stored in ASCII format, 1bytes = 2characters */ ++ for (int i = 0; i < 6; i++) { ++ tmp[0] = efuse_mac_addr[i * 2]; ++ tmp[1] = efuse_mac_addr[i * 2 + 1]; ++ tmp[2] = '\0'; ++ mac_addr[i] = hextoul(tmp, NULL); ++ } ++ ++ if (is_valid_ethaddr(mac_addr)) ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ else ++ meson_generate_serial_ethaddr(); ++ ++ eth_env_get_enetaddr("ethaddr", mac_addr); ++ } ++ ++ return 0; ++} +diff -ruN u-boot-2022.01/board/amlogic/ac2xx/Makefile u-boot-master/board/amlogic/ac2xx/Makefile +--- u-boot-2022.01/board/amlogic/ac2xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/board/amlogic/ac2xx/Makefile 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2020 BayLibre, SAS ++# Author: Neil Armstrong ++# Editor: flippy ++ ++obj-y := ac2xx.o +diff -ruN u-boot-2022.01/configs/h96max-x3_defconfig u-boot-master/configs/h96max-x3_defconfig +--- u-boot-2022.01/configs/h96max-x3_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/configs/h96max-x3_defconfig 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,90 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="ac2xx" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-h96-max-x3" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" h96max-x3" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_ADC=y ++CONFIG_SARADC_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MESON_G12A=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_VIDEO_BMP_RLE8=y ++CONFIG_BMP_16BPP=y ++CONFIG_BMP_24BPP=y ++CONFIG_BMP_32BPP=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++# custom options ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_FS_BTRFS=y ++CONFIG_EXT4_WRITE=y ++CONFIG_RBTREE=y ++CONFIG_SHA256=y ++CONFIG_CRC32C=y ++CONFIG_XXHASH=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_OFFSET=0x1fe000 ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_MMC_ENV_DEV=2 ++CONFIG_SYS_MMC_ENV_PART=0 +diff -ruN u-boot-2022.01/configs/hk1box_defconfig u-boot-master/configs/hk1box_defconfig +--- u-boot-2022.01/configs/hk1box_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/configs/hk1box_defconfig 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,90 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="ac2xx" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-hk1box-vontar-x3" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" hk1box" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_ADC=y ++CONFIG_SARADC_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MESON_G12A=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_VIDEO_BMP_RLE8=y ++CONFIG_BMP_16BPP=y ++CONFIG_BMP_24BPP=y ++CONFIG_BMP_32BPP=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++# custom options ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_FS_BTRFS=y ++CONFIG_EXT4_WRITE=y ++CONFIG_RBTREE=y ++CONFIG_SHA256=y ++CONFIG_CRC32C=y ++CONFIG_XXHASH=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_OFFSET=0x1fe000 ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_MMC_ENV_DEV=2 ++CONFIG_SYS_MMC_ENV_PART=0 +diff -ruN u-boot-2022.01/configs/x96max-plus_defconfig u-boot-master/configs/x96max-plus_defconfig +--- u-boot-2022.01/configs/x96max-plus_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/configs/x96max-plus_defconfig 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,90 @@ ++CONFIG_ARM=y ++CONFIG_SYS_BOARD="ac2xx" ++CONFIG_ARCH_MESON=y ++CONFIG_SYS_TEXT_BASE=0x01000000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DM_GPIO=y ++CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-x96-max-plus" ++CONFIG_MESON_G12A=y ++CONFIG_DEBUG_UART_BASE=0xff803000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_IDENT_STRING=" x96max-plus" ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x1000000 ++CONFIG_OF_BOARD_SETUP=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_MISC_INIT_R=y ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_IMI is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++CONFIG_OF_CONTROL=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_ADC=y ++CONFIG_SARADC_MESON=y ++CONFIG_MMC_MESON_GX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MDIO_MUX=y ++CONFIG_ETH_DESIGNWARE_MESON8B=y ++CONFIG_MDIO_MUX_MESON_G12A=y ++CONFIG_MESON_G12A_USB_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCTRL_MESON_G12A=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MESON_EE_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_ANNOUNCE=y ++CONFIG_DEBUG_UART_SKIP_INIT=y ++CONFIG_MESON_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_DWC3_MESON_G12A=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e ++CONFIG_USB_GADGET_PRODUCT_NUM=0xfada ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++# CONFIG_VIDEO_BPP16 is not set ++CONFIG_SYS_WHITE_ON_BLACK=y ++CONFIG_VIDEO_MESON=y ++CONFIG_VIDEO_DT_SIMPLEFB=y ++CONFIG_SPLASH_SCREEN=y ++CONFIG_SPLASH_SCREEN_ALIGN=y ++CONFIG_VIDEO_BMP_RLE8=y ++CONFIG_BMP_16BPP=y ++CONFIG_BMP_24BPP=y ++CONFIG_BMP_32BPP=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++# custom options ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_FS_BTRFS=y ++CONFIG_EXT4_WRITE=y ++CONFIG_RBTREE=y ++CONFIG_SHA256=y ++CONFIG_CRC32C=y ++CONFIG_XXHASH=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_OFFSET=0x1fe000 ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_MMC_ENV_DEV=2 ++CONFIG_SYS_MMC_ENV_PART=0 +diff -ruN u-boot-2022.01/doc/board/amlogic/h96max-x3.rst u-boot-master/doc/board/amlogic/h96max-x3.rst +--- u-boot-2022.01/doc/board/amlogic/h96max-x3.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/doc/board/amlogic/h96max-x3.rst 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,122 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++U-Boot for H96 Max X3 ++========================= ++ ++H96 Max X3 (gbit ethernet) is a android tvbox ++specifications: ++ ++ - Amlogic S905X3 ARM Cortex-A55 quad-core SoC ++ - 4GB DDR4 SDRAM ++ - 1Gbps Ethernet (External PHY) ++ - 1 x USB 3.0 HOST ++ - 1 x USB 2.0 OTG ++ - eMMC ++ - SDcard ++ - Infrared receiver ++ - SDIO WiFi Module ++ ++U-Boot compilation ++------------------ ++ ++.. code-block:: bash ++ ++ $ export CROSS_COMPILE=aarch64-none-elf- ++ $ make h96max-x3_defconfig ++ $ make ++ ++Image creation ++-------------- ++ ++Amlogic does not provide a source of firmware and the required tools ++to create a bootloader image, so it is necessary to extract acs.bin ++from the bootloader binary of the Android firmware released by the ++vendor, and copy the other relevant files from existing similar ++hardware (e.g. from khadas-vim3l). ++ ++This work has been done by flippy , see: ++https://github.com/unifreq/amlogic-boot-fip/tree/master/h96max-x3 ++ ++The general principle is: open the bootloader provided by the manufacturer ++with a hexadecimal editor, intercept the 4096 bytes content starting at ++offset 0xf200, and save it as acs.bin. ++ ++(Special attention is: If the manufacturer's bootloader is encrypted, then ++this method is invalid!) ++ ++ ++.. code-block:: bash ++ ++ $ git clone https://github.com/unifreq/amlogic-boot-fip ++ $ export FIPDIR=${PWD}/amlogic-boot-fip/h96max-x3 ++ ++Go back to mainline U-Boot source tree then : ++ ++ ++.. code-block:: bash ++ ++ $ mkdir fip ++ $ cp $FIPDIR/* fip/ ++ $ cp u-boot.bin fip/bl33.bin ++ ++ $ bash fip/blx_fix.sh \ ++ fip/bl30.bin \ ++ fip/zero_tmp \ ++ fip/bl30_zero.bin \ ++ fip/bl301.bin \ ++ fip/bl301_zero.bin \ ++ fip/bl30_new.bin \ ++ bl30 ++ ++ $ bash fip/blx_fix.sh \ ++ fip/bl2.bin \ ++ fip/zero_tmp \ ++ fip/bl2_zero.bin \ ++ fip/acs.bin \ ++ fip/bl21_zero.bin \ ++ fip/bl2_new.bin \ ++ bl2 ++ ++ $ $FIPDIR/fip/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ ++ --output fip/bl30_new.bin.g12a.enc \ ++ --level v3 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ ++ --output fip/bl30_new.bin.enc \ ++ --level v3 --type bl30 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ ++ --output fip/bl31.img.enc \ ++ --level v3 --type bl31 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ ++ --output fip/bl33.bin.enc \ ++ --level v3 --type bl33 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ ++ --output fip/bl2.n.bin.sig ++ ++ $ $FIPDIR/aml_encrypt_g12a --bootmk \ ++ --output fip/u-boot.bin \ ++ --bl2 fip/bl2.n.bin.sig \ ++ --bl30 fip/bl30_new.bin.enc \ ++ --bl31 fip/bl31.img.enc \ ++ --bl33 fip/bl33.bin.enc \ ++ --ddrfw1 fip/ddr4_1d.fw \ ++ --ddrfw2 fip/ddr4_2d.fw \ ++ --ddrfw3 fip/ddr3_1d.fw \ ++ --ddrfw4 fip/piei.fw \ ++ --ddrfw5 fip/lpddr4_1d.fw \ ++ --ddrfw6 fip/lpddr4_2d.fw \ ++ --ddrfw7 fip/diag_lpddr4.fw \ ++ --ddrfw8 fip/aml_ddr.fw \ ++ --ddrfw9 fip/lpddr3_1d.fw \ ++ --level v3 ++ ++and then write the image to SD with: ++ ++.. code-block:: bash ++ ++ $ DEV=/dev/your_sd_device ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 +diff -ruN u-boot-2022.01/doc/board/amlogic/hk1box.rst u-boot-master/doc/board/amlogic/hk1box.rst +--- u-boot-2022.01/doc/board/amlogic/hk1box.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/doc/board/amlogic/hk1box.rst 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,122 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++U-Boot for HK1Box/Vontar X3 ++========================= ++ ++HK1Box/Vontar X3 (gbit ethernet) is a android tvbox ++specifications: ++ ++ - Amlogic S905X3 ARM Cortex-A55 quad-core SoC ++ - 4GB DDR4 SDRAM ++ - 1Gbps Ethernet (External PHY) ++ - 1 x USB 3.0 HOST ++ - 1 x USB 2.0 OTG ++ - eMMC ++ - SDcard ++ - Infrared receiver ++ - SDIO WiFi Module ++ ++U-Boot compilation ++------------------ ++ ++.. code-block:: bash ++ ++ $ export CROSS_COMPILE=aarch64-none-elf- ++ $ make hk1box_defconfig ++ $ make ++ ++Image creation ++-------------- ++ ++Amlogic does not provide a source of firmware and the required tools ++to create a bootloader image, so it is necessary to extract acs.bin ++from the bootloader binary of the Android firmware released by the ++vendor, and copy the other relevant files from existing similar ++hardware (e.g. from khadas-vim3l). ++ ++This work has been done by flippy , see: ++https://github.com/unifreq/amlogic-boot-fip/tree/master/hk1box ++ ++The general principle is: open the bootloader provided by the manufacturer ++with a hexadecimal editor, intercept the 4096 bytes content starting at ++offset 0xf200, and save it as acs.bin. ++ ++(Special attention is: If the manufacturer's bootloader is encrypted, then ++this method is invalid!) ++ ++ ++.. code-block:: bash ++ ++ $ git clone https://github.com/unifreq/amlogic-boot-fip ++ $ export FIPDIR=${PWD}/amlogic-boot-fip/hk1box ++ ++Go back to mainline U-Boot source tree then : ++ ++ ++.. code-block:: bash ++ ++ $ mkdir fip ++ $ cp $FIPDIR/* fip/ ++ $ cp u-boot.bin fip/bl33.bin ++ ++ $ bash fip/blx_fix.sh \ ++ fip/bl30.bin \ ++ fip/zero_tmp \ ++ fip/bl30_zero.bin \ ++ fip/bl301.bin \ ++ fip/bl301_zero.bin \ ++ fip/bl30_new.bin \ ++ bl30 ++ ++ $ bash fip/blx_fix.sh \ ++ fip/bl2.bin \ ++ fip/zero_tmp \ ++ fip/bl2_zero.bin \ ++ fip/acs.bin \ ++ fip/bl21_zero.bin \ ++ fip/bl2_new.bin \ ++ bl2 ++ ++ $ $FIPDIR/fip/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ ++ --output fip/bl30_new.bin.g12a.enc \ ++ --level v3 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ ++ --output fip/bl30_new.bin.enc \ ++ --level v3 --type bl30 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ ++ --output fip/bl31.img.enc \ ++ --level v3 --type bl31 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ ++ --output fip/bl33.bin.enc \ ++ --level v3 --type bl33 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ ++ --output fip/bl2.n.bin.sig ++ ++ $ $FIPDIR/aml_encrypt_g12a --bootmk \ ++ --output fip/u-boot.bin \ ++ --bl2 fip/bl2.n.bin.sig \ ++ --bl30 fip/bl30_new.bin.enc \ ++ --bl31 fip/bl31.img.enc \ ++ --bl33 fip/bl33.bin.enc \ ++ --ddrfw1 fip/ddr4_1d.fw \ ++ --ddrfw2 fip/ddr4_2d.fw \ ++ --ddrfw3 fip/ddr3_1d.fw \ ++ --ddrfw4 fip/piei.fw \ ++ --ddrfw5 fip/lpddr4_1d.fw \ ++ --ddrfw6 fip/lpddr4_2d.fw \ ++ --ddrfw7 fip/diag_lpddr4.fw \ ++ --ddrfw8 fip/aml_ddr.fw \ ++ --ddrfw9 fip/lpddr3_1d.fw \ ++ --level v3 ++ ++and then write the image to SD with: ++ ++.. code-block:: bash ++ ++ $ DEV=/dev/your_sd_device ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 +diff -ruN u-boot-2022.01/doc/board/amlogic/x96max-plus.rst u-boot-master/doc/board/amlogic/x96max-plus.rst +--- u-boot-2022.01/doc/board/amlogic/x96max-plus.rst 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-master/doc/board/amlogic/x96max-plus.rst 2022-03-27 09:06:29.000000000 +0200 +@@ -0,0 +1,123 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++U-Boot for X96Max Plus ++========================= ++ ++X96Max plus (gbit ethernet) is a android tvbox manufactured by Shenzhen ++Amediatech Technology Co., Ltd ++specifications: ++ ++ - Amlogic S905X3 ARM Cortex-A55 quad-core SoC ++ - 4GB DDR4 SDRAM ++ - 1Gbps Ethernet (External PHY) ++ - 1 x USB 3.0 OTG ++ - 1 x USB 2.0 HOST ++ - eMMC ++ - SDcard ++ - Infrared receiver ++ - SDIO WiFi Module ++ ++U-Boot compilation ++------------------ ++ ++.. code-block:: bash ++ ++ $ export CROSS_COMPILE=aarch64-none-elf- ++ $ make x96max-plus_defconfig ++ $ make ++ ++Image creation ++-------------- ++ ++Amlogic does not provide a source of firmware and the required tools ++to create a bootloader image, so it is necessary to extract acs.bin ++from the bootloader binary of the Android firmware released by the ++vendor, and copy the other relevant files from existing similar ++hardware (e.g. from khadas-vim3l). ++ ++This work has been done by flippy , see: ++https://github.com/unifreq/amlogic-boot-fip/tree/master/x96max-plus ++ ++The general principle is: open the bootloader provided by the manufacturer ++with a hexadecimal editor, intercept the 4096 bytes content starting at ++offset 0xf200, and save it as acs.bin. ++ ++(Special attention is: If the manufacturer's bootloader is encrypted, then ++this method is invalid!) ++ ++ ++.. code-block:: bash ++ ++ $ git clone https://github.com/unifreq/amlogic-boot-fip ++ $ export FIPDIR=${PWD}/amlogic-boot-fip/x96max-plus ++ ++Go back to mainline U-Boot source tree then : ++ ++ ++.. code-block:: bash ++ ++ $ mkdir fip ++ $ cp $FIPDIR/* fip/ ++ $ cp u-boot.bin fip/bl33.bin ++ ++ $ bash fip/blx_fix.sh \ ++ fip/bl30.bin \ ++ fip/zero_tmp \ ++ fip/bl30_zero.bin \ ++ fip/bl301.bin \ ++ fip/bl301_zero.bin \ ++ fip/bl30_new.bin \ ++ bl30 ++ ++ $ bash fip/blx_fix.sh \ ++ fip/bl2.bin \ ++ fip/zero_tmp \ ++ fip/bl2_zero.bin \ ++ fip/acs.bin \ ++ fip/bl21_zero.bin \ ++ fip/bl2_new.bin \ ++ bl2 ++ ++ $ $FIPDIR/fip/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ ++ --output fip/bl30_new.bin.g12a.enc \ ++ --level v3 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ ++ --output fip/bl30_new.bin.enc \ ++ --level v3 --type bl30 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ ++ --output fip/bl31.img.enc \ ++ --level v3 --type bl31 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ ++ --output fip/bl33.bin.enc \ ++ --level v3 --type bl33 ++ ++ $ $FIPDIR/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ ++ --output fip/bl2.n.bin.sig ++ ++ $ $FIPDIR/aml_encrypt_g12a --bootmk \ ++ --output fip/u-boot.bin \ ++ --bl2 fip/bl2.n.bin.sig \ ++ --bl30 fip/bl30_new.bin.enc \ ++ --bl31 fip/bl31.img.enc \ ++ --bl33 fip/bl33.bin.enc \ ++ --ddrfw1 fip/ddr4_1d.fw \ ++ --ddrfw2 fip/ddr4_2d.fw \ ++ --ddrfw3 fip/ddr3_1d.fw \ ++ --ddrfw4 fip/piei.fw \ ++ --ddrfw5 fip/lpddr4_1d.fw \ ++ --ddrfw6 fip/lpddr4_2d.fw \ ++ --ddrfw7 fip/diag_lpddr4.fw \ ++ --ddrfw8 fip/aml_ddr.fw \ ++ --ddrfw9 fip/lpddr3_1d.fw \ ++ --level v3 ++ ++and then write the image to SD with: ++ ++.. code-block:: bash ++ ++ $ DEV=/dev/your_sd_device ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 ++ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444