Allow easy move data partition (#651)

* Allow easy move data partition

* Cleanup handling systemd

* Improve handling

* fix pipeline

* pipeline

* fix shell handling

* fix scripts

* Add bin folder

* fix lint

* Fix service handling

* Fix loading

* hide output

* Fix handling

buildroot-external/board/hardkernel/patches/linux/0001-FROMLIST-clk-meson-g12a-fix-gp0-and-hifi-ranges.patch

@@ -0,0 +1,39 @@
+From 81b290367d59103d1f041709c56a3de1c360e102 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 13 May 2019 14:45:31 +0200
+Subject: [PATCH] FROMLIST: clk: meson: g12a: fix gp0 and hifi ranges
+
+While some SoC samples are able to lock with a PLL factor of 55, others
+samples can't. ATM, a minimum of 60 appears to work on all the samples
+I have tried.
+
+Even with 60, it sometimes takes a long time for the PLL to eventually
+lock. The documentation says that the minimum rate of these PLLs DCO
+should be 3GHz, a factor of 125. Let's use that to be on the safe side.
+
+With factor range changed, the PLL seems to lock quickly (enough) so far.
+It is still unclear if the range was the only reason for the delay.
+
+Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/clk/meson/g12a.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
+index b3af61cc6fb9..66cf791bfc8c 100644
+--- a/drivers/clk/meson/g12a.c
++++ b/drivers/clk/meson/g12a.c
+@@ -1591,7 +1591,7 @@ static struct clk_regmap g12b_cpub_clk_trace = {
+ };
+ 
+ static const struct pll_mult_range g12a_gp0_pll_mult_range = {
+-	.min = 55,
++	.min = 125,
+ 	.max = 255,
+ };
+ 
+-- 
+2.17.1
+