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Update buildroot 2020.02.01 (#622)

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* Update buildroot 2020.02.01

Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>

* Fix LN

* Fix wpa

Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>

* Fix lint

Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>

* fix-network

Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>

* Fix script

Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
This commit is contained in:
Pascal Vizeli
2020-04-16 20:03:01 +02:00
committed by GitHub
parent 0c2b5aff65
commit 5a6678147e
6201 changed files with 73436 additions and 70757 deletions
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1
buildroot/board/andes/ae3xx/ae3xx.fragment Normal file
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@@ -0,0 +1 @@
CONFIG_NDS32_BUILTIN_DTB="ae3xx"

28
buildroot/board/andes/patches/linux/0001-nds32-Fix-boot-messages-garbled.patch Normal file
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@@ -0,0 +1,28 @@
From 90d52d180dcc5d1300dc352ca709eb6453894143 Mon Sep 17 00:00:00 2001
From: Nylon Chen <nylon7@andestech.com>
Date: Wed, 28 Nov 2018 16:26:46 +0800
Subject: [PATCH] nds32: Fix boot messages garbled
In order to display uart correctly we have to pass the correct setting of uart to kernel by bootarg.
This patch will provide such settings to set the correct uart baud rate.
Signed-off-by: Nylon Chen <nylon7@andestech.com>
---
arch/nds32/boot/dts/ae3xx.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
index bb39749a6673..aefe2090926a 100644
--- a/arch/nds32/boot/dts/ae3xx.dts
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -6,6 +6,7 @@
interrupt-parent = <&intc>;
chosen {
+ bootargs = "memblock=debug earlycon console=ttyS0,38400n8 debug loglevel=7";
stdout-path = &serial0;
};
--
2.18.0

49
buildroot/board/andes/readme.txt Normal file
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@@ -0,0 +1,49 @@
Intro
=====
Andestech(nds32) AE3XX Platform
The AE3XX prototype demonstrates the AE3XX example platform on the FPGA.
It is composed of one Andestech(nds32) processor and AE3XX.
How to build it
===============
Configure Buildroot
-------------------
The andes_ae3xx_defconfig configuration is a sample configuration with
all that is required to bring the FPGA Development Board:
$ make andes_ae3xx_defconfig
Build everything
----------------
Note: you will need to have access to the network, since Buildroot will
download the packages' sources.
$ make
Result of the build
-------------------
After building, you should obtain this tree:
output/images/
+-- vmlinux
+-- rootfs.cpio
+-- rootfs.tar
How to run it
=============
Run
---
Setup the Console with the rate 38400/8-N-1.
$ cd output/images
$ ../host/bin/nds32le-linux-gdb vmlinux
$ target remote [your host]
$ lo
$ c