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Buildroot 2018-11 (#258)

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* Update to buildroot 2018.11

* containerd update

* runc update

* runc docker engine

* runc docker proxy

* update rpi firmware

* update network manager

* update dhcpd

* update wait on network

* update rpi wifi

* revert glibc
This commit is contained in:
Pascal Vizeli
2018-11-26 11:04:01 +01:00
committed by GitHub
parent a9bbc7babe
commit 4411307353
3154 changed files with 41316 additions and 24203 deletions
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36
buildroot/arch/Config.in
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@@ -15,9 +15,6 @@ config BR2_ARCH_HAS_MMU_MANDATORY
config BR2_ARCH_HAS_MMU_OPTIONAL
bool
config BR2_ARCH_HAS_FDPIC_SUPPORT
bool
choice
prompt "Target Architecture"
default BR2_i386
@@ -201,6 +198,17 @@ config BR2_powerpc64le
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_riscv
bool "RISCV"
select BR2_ARCH_HAS_MMU_MANDATORY
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
help
RISC-V is an open, free Instruction Set Architecture created
by the UC Berkeley Architecture Research group and supported
and promoted by RISC-V Foundation.
https://riscv.org/
https://en.wikipedia.org/wiki/RISC-V
config BR2_sh
bool "SuperH"
select BR2_ARCH_HAS_MMU_OPTIONAL
@@ -282,6 +290,10 @@ config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
# The following string values are defined by the individual
# Config.in.$ARCH files
config BR2_ARCH
@@ -305,9 +317,6 @@ config BR2_GCC_TARGET_FP32_MODE
config BR2_GCC_TARGET_CPU
string
config BR2_GCC_TARGET_CPU_REVISION
string
# The value of this option will be passed as --with-fpu=<value> when
# building gcc (internal backend) or -mfpu=<value> in the toolchain
# wrapper (external toolchain)
@@ -340,7 +349,6 @@ config BR2_READELF_ARCH_NAME
choice
prompt "Target Binary Format"
default BR2_BINFMT_ELF if BR2_USE_MMU
default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
default BR2_BINFMT_FLAT
config BR2_BINFMT_ELF
@@ -352,16 +360,6 @@ config BR2_BINFMT_ELF
and executables used across different architectures and
operating systems.
config BR2_BINFMT_FDPIC
bool "FDPIC"
depends on BR2_ARCH_HAS_FDPIC_SUPPORT
select BR2_BINFMT_SUPPORTS_SHARED
help
ELF FDPIC binaries are based on ELF, but allow the individual
load segments of a binary to be located in memory
independently of each other. This makes this format ideal for
use in environments where no MMU is available.
config BR2_BINFMT_FLAT
bool "FLAT"
depends on !BR2_USE_MMU
@@ -433,6 +431,10 @@ if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
source "arch/Config.in.powerpc"
endif
if BR2_riscv
source "arch/Config.in.riscv"
endif
if BR2_sh
source "arch/Config.in.sh"
endif

82
buildroot/arch/Config.in.arm
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@@ -6,12 +6,21 @@ config BR2_ARM_CPU_HAS_NEON
config BR2_ARM_CPU_MAYBE_HAS_NEON
bool
# For some cores, the FPU is optional
config BR2_ARM_CPU_MAYBE_HAS_FPU
bool
config BR2_ARM_CPU_HAS_FPU
bool
# for some cores, VFPv2 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV2
bool
select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_VFPV2
bool
select BR2_ARM_CPU_HAS_FPU
# for some cores, VFPv3 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV3
@@ -31,6 +40,24 @@ config BR2_ARM_CPU_HAS_VFPV4
bool
select BR2_ARM_CPU_HAS_VFPV3
# FPv4 is always optional
config BR2_ARM_CPU_MAYBE_HAS_FPV4
bool
select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_FPV4
bool
select BR2_ARM_CPU_HAS_FPU
# FPv5 is always optional
config BR2_ARM_CPU_MAYBE_HAS_FPV5
bool
select BR2_ARM_CPU_MAYBE_HAS_FPV4
config BR2_ARM_CPU_HAS_FPV5
bool
select BR2_ARM_CPU_HAS_FPV4
config BR2_ARM_CPU_HAS_FP_ARMV8
bool
select BR2_ARM_CPU_HAS_VFPV4
@@ -240,7 +267,14 @@ config BR2_cortex_m3
config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_ARMV7M
config BR2_cortex_m7
bool "cortex-M7"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_ARMV7M
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
endif # !BR2_ARCH_IS_64
comment "armv8 cores"
@@ -445,7 +479,9 @@ config BR2_ARM_ENABLE_NEON
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
depends on BR2_ARM_CPU_MAYBE_HAS_FPU
select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
@@ -456,7 +492,7 @@ config BR2_ARM_ENABLE_VFP
choice
prompt "Target ABI"
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU
default BR2_ARM_EABI
depends on BR2_arm || BR2_armeb
help
@@ -491,7 +527,7 @@ config BR2_ARM_EABI
config BR2_ARM_EABIHF
bool "EABIhf"
depends on BR2_ARM_CPU_HAS_VFPV2
depends on BR2_ARM_CPU_HAS_FPU
help
The EABIhf is an extension of EABI which supports the 'hard'
floating point model. This model uses the floating point
@@ -512,10 +548,12 @@ endchoice
choice
prompt "Floating point strategy"
default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5
default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU
config BR2_ARM_SOFT_FLOAT
bool "Soft float"
@@ -622,6 +660,38 @@ config BR2_ARM_FPU_NEON_VFPV4
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
NEON is optional.
config BR2_ARM_FPU_FPV4D16
bool "FPv4-D16"
depends on BR2_ARM_CPU_HAS_FPV4
help
This option allows to use the FPv4-SP (single precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M4).
config BR2_ARM_FPU_FPV5D16
bool "FPv5-D16"
depends on BR2_ARM_CPU_HAS_FPV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
help
This option allows to use the FPv5-SP (single precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M7).
Note that if you want binary code that works on the earlier
Cortex-M4, you should instead select FPv4-D16.
config BR2_ARM_FPU_FPV5DPD16
bool "FPv5-DP-D16"
depends on BR2_ARM_CPU_HAS_FPV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
help
This option allows to use the FPv5-DP (double precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M7).
Note that if you want binary code that works on the earlier
Cortex-M4, you should instead select FPv4-D16.
config BR2_ARM_FPU_FP_ARMV8
bool "FP-ARMv8"
depends on BR2_ARM_CPU_HAS_FP_ARMV8
@@ -716,6 +786,7 @@ config BR2_GCC_TARGET_CPU
# armv7m
default "cortex-m3" if BR2_cortex_m3
default "cortex-m4" if BR2_cortex_m4
default "cortex-m7" if BR2_cortex_m7
# armv8a
default "cortex-a32" if BR2_cortex_a32
default "cortex-a35" if BR2_cortex_a35
@@ -753,6 +824,9 @@ config BR2_GCC_TARGET_FPU
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16
default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
depends on BR2_arm || BR2_armeb

102
buildroot/arch/Config.in.riscv Normal file
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@@ -0,0 +1,102 @@
# RISC-V CPU ISA extensions.
config BR2_RISCV_ISA_RVI
bool
config BR2_RISCV_ISA_RVM
bool
config BR2_RISCV_ISA_RVA
bool
config BR2_RISCV_ISA_RVF
bool
config BR2_RISCV_ISA_RVD
bool
config BR2_RISCV_ISA_RVC
bool
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
config BR2_riscv_g
bool "General purpose (G)"
select BR2_RISCV_ISA_RVI
select BR2_RISCV_ISA_RVM
select BR2_RISCV_ISA_RVA
select BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
help
General purpose (G) is equivalent to IMAFD.
config BR2_riscv_custom
bool "Custom architecture"
select BR2_RISCV_ISA_RVI
select BR2_RISCV_ISA_CUSTOM_RVA
endchoice
if BR2_riscv_custom
comment "Instruction Set Extensions"
config BR2_RISCV_ISA_CUSTOM_RVM
bool "Integer Multiplication and Division (M)"
select BR2_RISCV_ISA_RVM
config BR2_RISCV_ISA_CUSTOM_RVA
bool "Atomic Instructions (A)"
select BR2_RISCV_ISA_RVA
config BR2_RISCV_ISA_CUSTOM_RVF
bool "Single-precision Floating-point (F)"
select BR2_RISCV_ISA_RVF
config BR2_RISCV_ISA_CUSTOM_RVD
bool "Double-precision Floating-point (D)"
depends on BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_CUSTOM_RVC
bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
endif
config BR2_RISCV_64
bool
default y
select BR2_ARCH_IS_64
choice
prompt "Target ABI"
default BR2_RISCV_ABI_LP64
config BR2_RISCV_ABI_LP64
bool "lp64"
depends on BR2_ARCH_IS_64
config BR2_RISCV_ABI_LP64F
bool "lp64f"
depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
config BR2_RISCV_ABI_LP64D
bool "lp64d"
depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
endchoice
config BR2_ARCH
default "riscv64" if BR2_ARCH_IS_64
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_ABI
default "lp64" if BR2_RISCV_ABI_LP64
default "lp64f" if BR2_RISCV_ABI_LP64F
default "lp64d" if BR2_RISCV_ABI_LP64D
config BR2_READELF_ARCH_NAME
default "RISC-V"

22
buildroot/arch/arch.mk Normal file
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@@ -0,0 +1,22 @@
################################################################################
#
# Architecture-specific definitions
#
################################################################################
# Allow GCC target configuration settings to be optionally
# overwritten by architecture specific makefiles.
# Makefiles must use the GCC_TARGET_* variables below instead
# of the BR2_GCC_TARGET_* versions.
GCC_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
GCC_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
GCC_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
GCC_TARGET_FP32_MODE := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
GCC_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU))
GCC_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
GCC_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
GCC_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
# Include any architecture specific makefiles.
-include $(sort $(wildcard arch/arch.mk.*))

28
buildroot/arch/arch.mk.riscv Normal file
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@@ -0,0 +1,28 @@
#
# Configure the GCC_TARGET_ARCH variable and append the
# appropriate RISC-V ISA extensions.
#
ifeq ($(BR2_riscv),y)
ifeq ($(BR2_ARCH_IS_64),y)
GCC_TARGET_ARCH := rv64i
endif
ifeq ($(BR2_RISCV_ISA_RVM),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
endif
ifeq ($(BR2_RISCV_ISA_RVA),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
endif
ifeq ($(BR2_RISCV_ISA_RVF),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
endif
ifeq ($(BR2_RISCV_ISA_RVD),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
endif
ifeq ($(BR2_RISCV_ISA_RVC),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
endif
endif